SystemZ: mischeduler enabled

[jonpa]

Summary

pre-RA mischeduler enabled + tests updates

[uweigand]

Hmm. Some of those changes look like regressions, we should try to at least understand why this happens. Maybe there's a simple way to fix those again.

test/CodeGen/SystemZ/alloca-01.ll

41

This causes an extra copy later, right? We need to get the value into %r3 since it's used as function argument.

Can we find out why this extra copy happens and possibly avoid it?

test/CodeGen/SystemZ/backchain.ll

115

I don't think we need to check all this detail. I looks like if you just change the original test to use CHECK-DAG instead of CHECK, in particular in those four lines:

; CHECK: lgr [[SAVESP:%r[0-9]+]], %r15
; CHECK: lg [[BC:%r[0-9]+]], 0(%r15)
; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15
; CHECK: lgr %r15, [[NEWSP]]

everything should pass as-is.

test/CodeGen/SystemZ/call-03.ll

74

Another extra copy here ... can we avoid this?

test/CodeGen/SystemZ/fp-cmp-04.ll

215

Is there a reason why this cannot be CHECK-NEXT any more?

309

Another extra copy.

332

And again.

test/CodeGen/SystemZ/fp-conv-02.ll

74

Can we find out why this no longer happens?

test/CodeGen/SystemZ/fp-copysign-02.ll

39–41

Using a second variable is fine, of course, but hard-coding it to %v0 doesn't seem to make much sense. Why don't you just use [[REG2:%v[0-9]+]] ?

57

Likewise.

test/CodeGen/SystemZ/int-cmp-44.ll

736 ↗

(On Diff #115639)

Again, it would be good to understand why this isn't matched any more.

[jonpa]

Tests further updated per review

test/CodeGen/SystemZ/alloca-01.ll

41

Seems to relate mostly to the sourc-order isel sched handling the call PSEUDOs.

test/CodeGen/SystemZ/backchain.ll

115

I actually had to do CHECK-DAG all the way down to the last STG...

test/CodeGen/SystemZ/call-03.ll

74

regalloc fails to see that %r1 is actually a better choice - perhaps %r1 could be hinted.

test/CodeGen/SystemZ/fp-cmp-04.ll

215

Those instructions swapped places, but it should be CHECK-DAG.

309

SystemZElimCompare does no longer catch this.

332

same as for f15

test/CodeGen/SystemZ/fp-conv-02.ll

74

This relates to spill weight and foldable operands. I have a patch IP on this.

test/CodeGen/SystemZ/fp-copysign-02.ll

39–41

Sure (I guess I was happy just capturing the fact that the three instructions used the same reg)

test/CodeGen/SystemZ/int-cmp-44.ll

736 ↗

(On Diff #115639)

SystemZElimCompare can no longer transform, since the COPY is put after the compare with the mischeduler enabled.

[jonpa]

The test in fp-conv-02.ll that checked for LDEB has been rewritten to a .mir test with fp-conv-17.mir.

[jonpa]

The following test changes have been reverted since they are no longer failing due to the improved handling in optimizeCompareZer() as of r313877:

fp-cmp-04.ll (f11 slightly updated still with -DAG estensions)
int-cmp-44.ll

[jonpa]

Comments have been added to alloca-01.ll and call-03.ll making note of the extra copys.

[uweigand]

Have you looked into what's going on with the vec-cmp-cmp-logic-select.ll and vec-cmpsel.ll test cases? I see several of the tests now adding spill/reload code when they didn't before -- ideally this shouldn't happen if the misched does proper register pressure analysis ...

(As a general note, I'm not sure these fully auto-generated tests are very useful -- the changes from regenerating them are not very readable. In the future, it may be preferable to write explicit tests using -DAG and regular expressions to make the test survive scheduling / register allocation changes without rewriting it all the time.)

[jonpa]

vec-cmpsel.ll and vec-cmp-cmp-logic-select.ll reworked.
"CHECK" in comment in alloca-01.ll removed.

[uweigand]

OK, this now looks all good to me, thanks!

[jonpa]

Commited as trunk@315063

At final rebase, the following trivial test updates were also made:

diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll
index 9fa082c..b3084ad 100644
--- a/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -60,8 +60,8 @@ define i8 @f2(i8 *%src) {
 define i32 @f3(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN-LABEL: f3:
 ; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
-; CHECK-MAIN: sll %r3, 3
-; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-MAIN-DAG: sll %r3, 3
+; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
 ; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r3)
 ; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll
index 8330d09..e2ca7f4 100644
--- a/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -60,8 +60,8 @@ define i16 @f2(i16 *%src) {
 define i32 @f3(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN-LABEL: f3:
 ; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
-; CHECK-MAIN: sll %r3, 3
-; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-MAIN-DAG: sll %r3, 3
+; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
 ; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 16(%r3)
 ; CHECK-MAIN: risbg %r4, [[TMP]], 32, 47, 0

lib/Target/SystemZ/SystemZSubtarget.h

public:
   }
   const SystemZTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
+  // True if the subtarget should run MachineScheduler after aggressive
+  // coalescing. This currently replaces the SelectionDAG scheduler with the
+  // "source" order scheduler.
+  bool enableMachineScheduler() const override { return true; }
+
   // This is important for reducing register pressure in vector code.
   bool useAA() const override { return true; }
 
   // Always enable the early if-conversion pass.
   bool enableEarlyIfConversion() const override { return true; }
 
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);

test/CodeGen/SystemZ/alloca-01.ll

 ; Test variable-sized allocas and addresses based on them in cases where
 ; stack arguments are needed.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-D
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP
 
 declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g)
 
 ; Allocate %length bytes and take addresses based on the result.
 ; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
 ; is added to the copy of %r15.
+;
+; NOTE: 'la %r0, 177(%r1)' is actually an expected fail as it would
+; be better (and possible) to load into %r3 directly.
+;
 define i64 @f1(i64 %length, i64 %index) {
 ; FIXME: a better sequence would be:
 ;
 ;    lgr %r1, %r15
 ;    sgr %r1, %r2
 ;    nill %r1, 0xfff8
 ;    lgr %r15, %r1
 ;
 ; CHECK-LABEL: f1:
 ; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
 ; CHECK-DAG: nill [[REG1]], 65528
 ; CHECK-DAG: lgr [[REG2:%r[0-5]]], %r15
 ; CHECK: sgr [[REG2]], [[REG1]]
 ; CHECK: lgr %r15, [[REG2]]
 ;
 ; CHECK-A-LABEL: f1:
-; CHECK-A: lgr %r15, %r1
-; CHECK-A: la %r2, 176(%r1)
+; CHECK-A-DAG: lgr %r15, %r1
+; CHECK-A-DAG: la %r2, 176(%r1)
 ;
 ; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, %r1
-; CHECK-B: la %r3, 177(%r1)
+; CHECK-B: la %r0, 177(%r1)
 ;
 ; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, %r1
 ; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
 ;
 ; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, %r1
 ; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})

test/CodeGen/SystemZ/alloca-02.ll

 ; Make sure that the alloca offset isn't lost when the alloca result is
 ; used directly in a load or store.  There must always be an LA or LAY.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-D
 
 declare i64 @bar(i8 *%a)
 
 define i64 @f1(i64 %length, i64 %index) {
 ; CHECK-A-LABEL: f1:
-; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
-; CHECK-A: la %r2, 160([[ADDR]])
+; CHECK-A-DAG: lgr %r15, [[ADDR:%r[1-5]]]
+; CHECK-A-DAG: la %r2, 160([[ADDR]])
 ; CHECK-A: mvi 0(%r2), 0
 ;
 ; CHECK-B-LABEL: f1:
-; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
-; CHECK-B: la %r2, 160([[ADDR]])
+; CHECK-B-DAG: lgr %r15, [[ADDR:%r[1-5]]]
+; CHECK-B-DAG: la %r2, 160([[ADDR]])
 ; CHECK-B: mvi 4095(%r2), 1
 ;
 ; CHECK-C-LABEL: f1:
-; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
+; CHECK-C-DAG: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-C-DAG: la %r2, 160([[ADDR]])
 ; CHECK-C-DAG: lhi [[TMP:%r[0-5]]], 2
 ; CHECK-C: stc [[TMP]], 0({{%r3,%r2|%r2,%r3}})
 ;
 ; CHECK-D-LABEL: f1:
-; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
+; CHECK-D-DAG: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-D-DAG: la %r2, 160([[ADDR]])
 ; CHECK-D-DAG: lhi [[TMP:%r[0-5]]], 3
 ; CHECK-D: stc [[TMP]], 4095({{%r3,%r2|%r2,%r3}})
 ;
 ; CHECK-E-LABEL: f1:
-; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
+; CHECK-E-DAG: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-E-DAG: la %r2, 160([[ADDR]])
 ; CHECK-E-DAG: lhi [[TMP:%r[0-5]]], 4
 ; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}})
   %a = alloca i8, i64 %length
   store volatile i8 0, i8 *%a
   %b = getelementptr i8, i8 *%a, i64 4095
   store volatile i8 1, i8 *%b
   %c = getelementptr i8, i8 *%a, i64 %index

test/CodeGen/SystemZ/alloca-03.ll

; CHECK: aghi %r15, 168
   %x = alloca i64
   store volatile i64 10, i64* %x
   ret void
 }
 
 ; Allocate %len * 8, no need to align stack.
 define void @f1(i64 %len) {
 ; CHECK-LABEL: f1:
-; CHECK: sllg    %r0, %r2, 3
-; CHECK: lgr     %r1, %r15
+; CHECK-DAG: sllg    %r0, %r2, 3
+; CHECK-DAG: lgr     %r1, %r15
 ; CHECK: sgr     %r1, %r0
 ; CHECK-NOT: ngr
-; CHECK: lgr     %r15, %r1
-; CHECK: la      %r1, 160(%r1)
-; CHECK: mvghi   0(%r1), 10
+; CHECK-DAG: lgr     %r15, %r1
+; CHECK-DAG: la      %r2, 160(%r1)
+; CHECK: mvghi   0(%r2), 10
   %x = alloca i64, i64 %len
   store volatile i64 10, i64* %x
   ret void
 }
 
 ; Static alloca, align 128.
 define void @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: aghi    %r1, -128
-; CHECK: lgr     %r15, %r1
-; CHECK: la      %r1, 280(%r1)
-; CHECK: nill  %r1, 65408
-; CHECK: mvghi   0(%r1), 10
+; CHECK-DAG: lgr     %r15, %r1
+; CHECK-DAG: la      %r2, 280(%r1)
+; CHECK-DAG: nill    %r2, 65408
+; CHECK: mvghi   0(%r2), 10
   %x = alloca i64, i64 1, align 128
   store volatile i64 10, i64* %x, align 128
   ret void
 }
 
 ; Dynamic alloca, align 128.
 define void @f3(i64 %len) {
 ; CHECK-LABEL: f3:
-; CHECK: sllg %r1, %r2, 3
-; CHECK: la %r0, 120(%r1)
-; CHECK: lgr  %r1, %r15
+; CHECK-DAG: sllg %r2, %r2, 3
+; CHECK-DAG: la %r0, 120(%r2)
+; CHECK-DAG: lgr  %r1, %r15
 ; CHECK: sgr  %r1, %r0
+; CHECK: la %r2, 280(%r1)
+; CHECK: nill %r2, 65408
 ; CHECK: lgr  %r15, %r1
-; CHECK: la %r1, 280(%r1)
-; CHECK: nill %r1, 65408
-; CHECK: mvghi  0(%r1), 10
+; CHECK: mvghi  0(%r2), 10
   %x = alloca i64, i64 %len, align 128
   store volatile i64 10, i64* %x, align 128
   ret void
 }
 
 ; Static alloca w/out alignment - part of frame.
 define void @f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: aghi    %r15, -168
 ; CHECK: mvhi    164(%r15), 10
 ; CHECK: aghi    %r15, 168
   %x = alloca i32
   store volatile i32 10, i32* %x
   ret void
 }
 
 ; Static alloca of one i32, aligned by 128.
 define void @f5() {
 ; CHECK-LABEL: f5:
 
 ; CHECK: lgr  %r1, %r15
 ; CHECK: aghi %r1, -128
+; CHECK: la %r2, 280(%r1)
+; CHECK: nill %r2, 65408
 ; CHECK: lgr  %r15, %r1
-; CHECK: la %r1, 280(%r1)
-; CHECK: nill %r1, 65408
-; CHECK: mvhi 0(%r1), 10
+; CHECK: mvhi 0(%r2), 10
   %x = alloca i32, i64 1, align 128
   store volatile i32 10, i32* %x
   ret void
 }
 

test/CodeGen/SystemZ/args-06.ll

 ; Test the padding of unextended integer stack parameters.  These are used
 ; to pass structures.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
 ; CHECK-LABEL: f1:
+; CHECK: lb {{%r[0-5]}}, 175(%r15)
+; CHECK: lb {{%r[0-5]}}, 167(%r15)
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
 ; CHECK: ar %r2, %r6
-; CHECK: lb {{%r[0-5]}}, 167(%r15)
-; CHECK: lb {{%r[0-5]}}, 175(%r15)
 ; CHECK: br %r14
   %addb = add i8 %a, %b
   %addc = add i8 %addb, %c
   %addd = add i8 %addc, %d
   %adde = add i8 %addd, %e
   %addf = add i8 %adde, %f
   %addg = add i8 %addf, %g
   ret i8 %addg

test/CodeGen/SystemZ/atomicrmw-add-01.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg %r1, %r2, 0, 189, 0{{$}}
-; CHECK: sll [[SHIFT:%r[0-9]+]], 3
-; CHECK: l [[OLD:%r[0-9]+]], 0(%r1)
+; CHECK-DAG: sll [[SHIFT:%r[0-9]+]], 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0(%r1)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r1)
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-add-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-and-01.ll

; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nilh [[ROT]], 33023
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-and-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-minmax-01.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]
; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check signed maximum.
 define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]
; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check unsigned minimum.
 define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]
; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check unsigned maximum.
 define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f4:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]

test/CodeGen/SystemZ/atomicrmw-minmax-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]
; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check signed maximum.
 define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]
; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check unsigned minimum.
 define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]
; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check unsigned maximum.
 define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f4:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LOOP]]

test/CodeGen/SystemZ/atomicrmw-minmax-04.ll

; CHECK: ber %r14
   %ptr = inttoptr i64 %add to i64 *
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check that constants are handled.
 define i64 @f10(i64 %dummy, i64 *%ptr) {
 ; CHECK-LABEL: f10:
-; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
-; CHECK: lg %r2, 0(%r3)
+; CHECK-DAG: lghi [[LIMIT:%r[0-9]+]], 42
+; CHECK-DAG: lg %r2, 0(%r3)
 ; CHECK: j [[LOOP:\.[^:]*]]
 ; CHECK: [[BB1:\.[^:]*]]:
 ; CHECK: csg %r2, [[NEW:%r[0-9]+]], 0(%r3)
 ; CHECK: ber %r14
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]]
 ; CHECK: lghi [[NEW]], 42
 ; CHECK: j [[BB1]]
   %res = atomicrmw min i64 *%ptr, i64 42 seq_cst
   ret i64 %res
 }

test/CodeGen/SystemZ/atomicrmw-nand-01.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nilh [[ROT]], 33023
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)

test/CodeGen/SystemZ/atomicrmw-nand-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: nilh [[ROT]], 32768
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)

test/CodeGen/SystemZ/atomicrmw-or-01.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-or-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-sub-01.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-sub-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-xchg-01.ll

 ; Test 8-bit atomic exchange.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
 
 ; Check exchange with a variable.
 ; - CHECK is for the main loop.
 ; - CHECK-SHIFT makes sure that the negated shift count used by the second
 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.  CHECK-SHIFT also checks that %r3 is not modified before
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-xchg-02.ll

 ; Test 16-bit atomic exchange.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
 
 ; Check exchange with a variable.
 ; - CHECK is for the main loop.
 ; - CHECK-SHIFT makes sure that the negated shift count used by the second
 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.  CHECK-SHIFT also checks that %r3 is not modified before
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-xchg-03.ll

; CHECK: br %r14
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i32 @f10(i32 %dummy, i32 *%src) {
 ; CHECK-LABEL: f10:
-; CHECK: llill [[VALUE:%r[0-9+]]], 40000
-; CHECK: l %r2, 0(%r3)
+; CHECK-DAG: llill [[VALUE:%r[0-9+]]], 40000
+; CHECK-DAG: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, [[VALUE]], 0(%r3)
 ; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i32 *%src, i32 40000 seq_cst
   ret i32 %res
 }
 

test/CodeGen/SystemZ/atomicrmw-xchg-04.ll

; CHECK: br %r14
   %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i64 @f7(i64 %dummy, i64 *%ptr) {
 ; CHECK-LABEL: f7:
-; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
-; CHECK: lg %r2, 0(%r3)
+; CHECK-DAG: llilf [[VALUE:%r[0-9+]]], 3000000000
+; CHECK-DAG: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, [[VALUE]], 0(%r3)
 ; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i64 *%ptr, i64 3000000000 seq_cst
   ret i64 %res
 }

test/CodeGen/SystemZ/atomicrmw-xor-01.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 %b seq_cst
   ret i8 %res
 }
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/atomicrmw-xor-02.ll

 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.
 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14
; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 %b seq_cst
   ret i16 %res
 }
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
-; CHECK: sll %r2, 3
-; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-DAG: sll %r2, 3
+; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16(%r2)
 ; CHECK: br %r14

test/CodeGen/SystemZ/backchain.ll

 ; check that llvm.stackrestore restores the backchain
 define void @f5(i32 %count1, i32 %count2) "backchain" {
 ; CHECK-LABEL: f5:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: lgr %r1, %r15
 ; CHECK: aghi %r15, -160
 ; CHECK: stg %r1, 0(%r15)
 ; CHECK: lgr %r11, %r15
-; CHECK: lgr [[SAVESP:%r[0-9]+]], %r15
-; CHECK: lg [[BC:%r[0-9]+]], 0(%r15)
-; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15
-; CHECK: lgr %r15, [[NEWSP]]
-; CHECK: stg [[BC]], 0([[NEWSP]])
-; CHECK: lg [[BC2:%r[0-9]+]], 0(%r15)
-; CHECK: lgr %r15, [[SAVESP]]
-; CHECK: stg [[BC2]], 0([[SAVESP]])
-; CHECK: lg [[BC3:%r[0-9]+]], 0(%r15)
-; CHECK: lgr [[NEWSP2:%r[0-9]+]], %r15
-; CHECK: lgr %r15, [[NEWSP2]]
-; CHECK: stg [[BC3]], 0([[NEWSP2]])
+; CHECK-DAG: lgr [[SAVESP:%r[0-9]+]], %r15
+; CHECK-DAG: lg [[BC:%r[0-9]+]], 0(%r15)
+; CHECK-DAG: lgr [[NEWSP:%r[0-9]+]], %r15
+; CHECK-DAG: lgr %r15, [[NEWSP]]
+; CHECK-DAG: stg [[BC]], 0([[NEWSP]])
+; CHECK-DAG: lg [[BC2:%r[0-9]+]], 0(%r15)
+; CHECK-DAG: lgr %r15, [[SAVESP]]
+; CHECK-DAG: stg [[BC2]], 0([[SAVESP]])
+; CHECK-DAG: lg [[BC3:%r[0-9]+]], 0(%r15)
+; CHECK-DAG: lgr [[NEWSP2:%r[0-9]+]], %r15
+; CHECK-DAG: lgr %r15, [[NEWSP2]]
+; CHECK-DAG: stg [[BC3]], 0([[NEWSP2]])
 ; CHECK: lmg %r11, %r15, 248(%r11)
 ; CHECK: br %r14
   %src = call i8 *@llvm.stacksave()
   %array1 = alloca i8, i32 %count1
   store volatile i8 0, i8 *%array1
   call void @llvm.stackrestore(i8 *%src)
   %array2 = alloca i8, i32 %count2
   store volatile i8 0, i8 *%array2
   ret void
 }

test/CodeGen/SystemZ/call-03.ll

 ; CHECK: br %r14
   tail call void @uses_stack(float 0.0, float 0.0, float 0.0, float 0.0,
                              float 0.0)
   ret void
 }
 
 ; Check an indirect call.  In this case the only acceptable choice for
 ; the target register is %r1.
+;
+; NOTE: the extra copy 'lgr %r1, %r0' is a coalescing failure.
 define void @f5(void(i32, i32, i32, i32) *%foo) {
 ; CHECK-LABEL: f5:
-; CHECK: lgr %r1, %r2
+; CHECK: lgr %r0, %r2
 ; CHECK-DAG: lhi %r2, 1
 ; CHECK-DAG: lhi %r3, 2
 ; CHECK-DAG: lhi %r4, 3
 ; CHECK-DAG: lhi %r5, 4
+; CHECK: lgr %r1, %r0
 ; CHECK: br %r1
   tail call void %foo(i32 1, i32 2, i32 3, i32 4)
   ret void
 }
 
 ; Check an indirect call that will be forced into a call-saved GPR
 ; (which should be %r13, the highest GPR not used for anything else).
 define void @f6(void(i32) *%foo) {

test/CodeGen/SystemZ/cmpxchg-01.ll

 ; Test 8-bit compare and swap.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
 
 ; Check compare and swap with a variable.
 ; - CHECK is for the main loop.
 ; - CHECK-SHIFT makes sure that the negated shift count used by the second
 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.  CHECK-SHIFT also checks that %r3 is not modified before
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
-; CHECK-MAIN: sll %r3, 3
-; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-MAIN-DAG: sll %r3, 3
+; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
 ; CHECK-MAIN: rll %r2, [[OLD]], 8(%r3)
 ; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0
 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
 ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK-MAIN: jl [[LOOP]]

test/CodeGen/SystemZ/cmpxchg-02.ll

 ; Test 16-bit compare and swap.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
 
 ; Check compare and swap with a variable.
 ; - CHECK is for the main loop.
 ; - CHECK-SHIFT makes sure that the negated shift count used by the second
 ;   RLL is set up correctly.  The negation is independent of the NILL and L
 ;   tested in CHECK.  CHECK-SHIFT also checks that %r3 is not modified before
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
-; CHECK-MAIN: sll %r3, 3
-; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
+; CHECK-MAIN-DAG: sll %r3, 3
+; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
 ; CHECK-MAIN: rll %r2, [[OLD]], 16(%r3)
 ; CHECK-MAIN: risbg %r4, %r2, 32, 47, 0
 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
 ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
 ; CHECK-MAIN: jl [[LOOP]]

test/CodeGen/SystemZ/cmpxchg-05.ll

define zeroext i8 @f5(i8* nocapture, i8 zeroext, i8 zeroext) {
   %res = extractvalue { i8, i1 } %cx, 1
   %xres = sext i1 %res to i8
   ret i8 %xres
 }
 
 ; Now use the comparison result and zero-extended old value.
 ; CHECK-LABEL: f6
 ; CHECK: llcr [[REG:%r[0-9]+]], [[RES:%r[0-9]+]]
-; CHECK: st [[REG]], 0(%r5)
-; CHECK: cr [[REG]], %r3
+; CHECK-DAG: st [[REG]], 0(%r5)
+; CHECK-DAG: cr [[REG]], %r3
 define zeroext i8 @f6(i8* nocapture, i8 zeroext, i8 zeroext, i32*) {
   %cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst
   %old = extractvalue { i8, i1 } %cx, 0
   %xold = zext i8 %old to i32
   store i32 %xold, i32* %3
   %res = extractvalue { i8, i1 } %cx, 1
   %xres = sext i1 %res to i8
   ret i8 %xres
 }

test/CodeGen/SystemZ/fp-add-03.ll

 ; Test 128-bit floating-point addition.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; There is no memory form of 128-bit addition.
 define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK-LABEL: f1:
-; CHECK: lxebr %f0, %f0
-; CHECK: ld %f1, 0(%r2)
-; CHECK: ld %f3, 8(%r2)
-; CHECK: axbr %f1, %f0
-; CHECK: std %f1, 0(%r2)
-; CHECK: std %f3, 8(%r2)
+; CHECK-DAG: lxebr %f0, %f0
+; CHECK-DAG: ld %f1, 0(%r2)
+; CHECK-DAG: ld %f3, 8(%r2)
+; CHECK: axbr %f0, %f1
+; CHECK: std %f0, 0(%r2)
+; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
   %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %sum = fadd fp128 %f1, %f2x
   store fp128 %sum, fp128 *%ptr
   ret void
 }

test/CodeGen/SystemZ/fp-cmp-03.ll

 ; Test 128-bit floating-point comparison.  The tests assume a z10 implementation
 ; of select, using conditional branches rather than LOCGR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; There is no memory form of 128-bit comparison.
 define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
 ; CHECK-LABEL: f1:
-; CHECK: lxebr %f0, %f0
-; CHECK: ld %f1, 0(%r4)
-; CHECK: ld %f3, 8(%r4)
+; CHECK-DAG: lxebr %f0, %f0
+; CHECK-DAG: ld %f1, 0(%r4)
+; CHECK-DAG: ld %f3, 8(%r4)
 ; CHECK: cxbr %f1, %f0
 ; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f2x = fpext float %f2 to fp128
   %f1 = load fp128 , fp128 *%ptr
   %cond = fcmp oeq fp128 %f1, %f2x
   %res = select i1 %cond, i64 %a, i64 %b

test/CodeGen/SystemZ/fp-cmp-04.ll

 }
 
 ; Test a case where CC is set based on a different register from the
 ; compare input.
 define float @f11(float %a, float %b, float %c, float *%dest1, float *%dest2) {
 ; CHECK-LABEL: f11:
 ; CHECK: aebr %f0, %f2
 ; CHECK-NEXT: sebr %f4, %f0
-; CHECK-NEXT: ste %f4, 0(%r2)
-; CHECK-NEXT: ltebr %f0, %f0
+; CHECK-DAG: ste %f4, 0(%r2)
+; CHECK-DAG: ltebr %f0, %f0
 ; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %add = fadd float %a, %b
   %sub = fsub float %c, %add
   store float %sub, float *%dest1
   %cmp = fcmp oeq float %add, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %sub, float *%dest2
exit:
   ret void
 }
 
 ; Test a case where it is the source rather than destination of LER that
 ; we need.
 define float @f15(float %val, float %dummy, float *%dest) {
 ; CHECK-LABEL: f15:
 ; CHECK: ltebr %f2, %f0
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %f2
 ; CHECK-NEXT: #NO_APP
 ; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{f2}"(float %val)
   %cmp = fcmp olt float %val, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %val, float *%dest
   br label %exit
 
 exit:
   ret float %val
 }
 
 ; Test a case where it is the source rather than destination of LDR that
 ; we need.
 define double @f16(double %val, double %dummy, double *%dest) {
 ; CHECK-LABEL: f16:
 ; CHECK: ltdbr %f2, %f0
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %f2
 ; CHECK-NEXT: #NO_APP
 ; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{f2}"(double %val)
   %cmp = fcmp olt double %val, 0.0
   br i1 %cmp, label %exit, label %store

test/CodeGen/SystemZ/fp-conv-02.ll

 ; CHECK: ldeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
   %ptr1 = getelementptr float, float *%base, i64 %index
   %ptr2 = getelementptr float, float *%ptr1, i64 100
   %val = load float , float *%ptr2
   %res = fpext float %val to double
   ret double %res
 }
 
-; Test a case where we spill the source of at least one LDEBR.  We want
-; to use LDEB if possible.
-define void @f7(double *%ptr1, float *%ptr2) {
-; CHECK-LABEL: f7:
-; CHECK-SCALAR: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
-; CHECK: br %r14
-  %val0 = load volatile float , float *%ptr2
-  %val1 = load volatile float , float *%ptr2
-  %val2 = load volatile float , float *%ptr2
-  %val3 = load volatile float , float *%ptr2
-  %val4 = load volatile float , float *%ptr2
-  %val5 = load volatile float , float *%ptr2
-  %val6 = load volatile float , float *%ptr2
-  %val7 = load volatile float , float *%ptr2
-  %val8 = load volatile float , float *%ptr2
-  %val9 = load volatile float , float *%ptr2
-  %val10 = load volatile float , float *%ptr2
-  %val11 = load volatile float , float *%ptr2
-  %val12 = load volatile float , float *%ptr2
-  %val13 = load volatile float , float *%ptr2
-  %val14 = load volatile float , float *%ptr2
-  %val15 = load volatile float , float *%ptr2
-  %val16 = load volatile float , float *%ptr2
-
-  %ext0 = fpext float %val0 to double
-  %ext1 = fpext float %val1 to double
-  %ext2 = fpext float %val2 to double
-  %ext3 = fpext float %val3 to double
-  %ext4 = fpext float %val4 to double
-  %ext5 = fpext float %val5 to double
-  %ext6 = fpext float %val6 to double
-  %ext7 = fpext float %val7 to double
-  %ext8 = fpext float %val8 to double
-  %ext9 = fpext float %val9 to double
-  %ext10 = fpext float %val10 to double
-  %ext11 = fpext float %val11 to double
-  %ext12 = fpext float %val12 to double
-  %ext13 = fpext float %val13 to double
-  %ext14 = fpext float %val14 to double
-  %ext15 = fpext float %val15 to double
-  %ext16 = fpext float %val16 to double
-
-  store volatile float %val0, float *%ptr2
-  store volatile float %val1, float *%ptr2
-  store volatile float %val2, float *%ptr2
-  store volatile float %val3, float *%ptr2
-  store volatile float %val4, float *%ptr2
-  store volatile float %val5, float *%ptr2
-  store volatile float %val6, float *%ptr2
-  store volatile float %val7, float *%ptr2
-  store volatile float %val8, float *%ptr2
-  store volatile float %val9, float *%ptr2
-  store volatile float %val10, float *%ptr2
-  store volatile float %val11, float *%ptr2
-  store volatile float %val12, float *%ptr2
-  store volatile float %val13, float *%ptr2
-  store volatile float %val14, float *%ptr2
-  store volatile float %val15, float *%ptr2
-  store volatile float %val16, float *%ptr2
-
-  store volatile double %ext0, double *%ptr1
-  store volatile double %ext1, double *%ptr1
-  store volatile double %ext2, double *%ptr1
-  store volatile double %ext3, double *%ptr1
-  store volatile double %ext4, double *%ptr1
-  store volatile double %ext5, double *%ptr1
-  store volatile double %ext6, double *%ptr1
-  store volatile double %ext7, double *%ptr1
-  store volatile double %ext8, double *%ptr1
-  store volatile double %ext9, double *%ptr1
-  store volatile double %ext10, double *%ptr1
-  store volatile double %ext11, double *%ptr1
-  store volatile double %ext12, double *%ptr1
-  store volatile double %ext13, double *%ptr1
-  store volatile double %ext14, double *%ptr1
-  store volatile double %ext15, double *%ptr1
-  store volatile double %ext16, double *%ptr1
-
-  ret void
-}

test/CodeGen/SystemZ/fp-conv-17.mir

+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -start-before=greedy %s -o - \
+# RUN:   | FileCheck %s
+--- |
+  define void @f0(double* %ptr1, float* %ptr2) {
+    %val0 = load volatile float, float* %ptr2
+    %val1 = load volatile float, float* %ptr2
+    %val2 = load volatile float, float* %ptr2
+    %val3 = load volatile float, float* %ptr2
+    %val4 = load volatile float, float* %ptr2
+    %val5 = load volatile float, float* %ptr2
+    %val6 = load volatile float, float* %ptr2
+    %val7 = load volatile float, float* %ptr2
+    %val8 = load volatile float, float* %ptr2
+    %val9 = load volatile float, float* %ptr2
+    %val10 = load volatile float, float* %ptr2
+    %val11 = load volatile float, float* %ptr2
+    %val12 = load volatile float, float* %ptr2
+    %val13 = load volatile float, float* %ptr2
+    %val14 = load volatile float, float* %ptr2
+    %val15 = load volatile float, float* %ptr2
+    %val16 = load volatile float, float* %ptr2
+    %ext0 = fpext float %val0 to double
+    %ext1 = fpext float %val1 to double
+    %ext2 = fpext float %val2 to double
+    %ext3 = fpext float %val3 to double
+    %ext4 = fpext float %val4 to double
+    %ext5 = fpext float %val5 to double
+    %ext6 = fpext float %val6 to double
+    %ext7 = fpext float %val7 to double
+    %ext8 = fpext float %val8 to double
+    %ext9 = fpext float %val9 to double
+    %ext10 = fpext float %val10 to double
+    %ext11 = fpext float %val11 to double
+    %ext12 = fpext float %val12 to double
+    %ext13 = fpext float %val13 to double
+    %ext14 = fpext float %val14 to double
+    %ext15 = fpext float %val15 to double
+    %ext16 = fpext float %val16 to double
+    store volatile float %val0, float* %ptr2
+    store volatile float %val1, float* %ptr2
+    store volatile float %val2, float* %ptr2
+    store volatile float %val3, float* %ptr2
+    store volatile float %val4, float* %ptr2
+    store volatile float %val5, float* %ptr2
+    store volatile float %val6, float* %ptr2
+    store volatile float %val7, float* %ptr2
+    store volatile float %val8, float* %ptr2
+    store volatile float %val9, float* %ptr2
+    store volatile float %val10, float* %ptr2
+    store volatile float %val11, float* %ptr2
+    store volatile float %val12, float* %ptr2
+    store volatile float %val13, float* %ptr2
+    store volatile float %val14, float* %ptr2
+    store volatile float %val15, float* %ptr2
+    store volatile float %val16, float* %ptr2
+    store volatile double %ext0, double* %ptr1
+    store volatile double %ext1, double* %ptr1
+    store volatile double %ext2, double* %ptr1
+    store volatile double %ext3, double* %ptr1
+    store volatile double %ext4, double* %ptr1
+    store volatile double %ext5, double* %ptr1
+    store volatile double %ext6, double* %ptr1
+    store volatile double %ext7, double* %ptr1
+    store volatile double %ext8, double* %ptr1
+    store volatile double %ext9, double* %ptr1
+    store volatile double %ext10, double* %ptr1
+    store volatile double %ext11, double* %ptr1
+    store volatile double %ext12, double* %ptr1
+    store volatile double %ext13, double* %ptr1
+    store volatile double %ext14, double* %ptr1
+    store volatile double %ext15, double* %ptr1
+    store volatile double %ext16, double* %ptr1
+    ret void
+  }
+  
+...
+
+# CHECK-LABEL: f0:
+# CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
+# CHECK: br %r14
+
+---
+name:            f0
+alignment:       2
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: addr64bit }
+  - { id: 1, class: addr64bit }
+  - { id: 2, class: fp32bit }
+  - { id: 3, class: fp32bit }
+  - { id: 4, class: fp32bit }
+  - { id: 5, class: fp32bit }
+  - { id: 6, class: fp32bit }
+  - { id: 7, class: fp32bit }
+  - { id: 8, class: fp32bit }
+  - { id: 9, class: fp32bit }
+  - { id: 10, class: fp32bit }
+  - { id: 11, class: fp32bit }
+  - { id: 12, class: fp32bit }
+  - { id: 13, class: fp32bit }
+  - { id: 14, class: fp32bit }
+  - { id: 15, class: fp32bit }
+  - { id: 16, class: fp32bit }
+  - { id: 17, class: fp32bit }
+  - { id: 18, class: fp32bit }
+  - { id: 19, class: fp64bit }
+  - { id: 20, class: fp64bit }
+  - { id: 21, class: fp64bit }
+  - { id: 22, class: fp64bit }
+  - { id: 23, class: fp64bit }
+  - { id: 24, class: fp64bit }
+  - { id: 25, class: fp64bit }
+  - { id: 26, class: fp64bit }
+  - { id: 27, class: fp64bit }
+  - { id: 28, class: fp64bit }
+  - { id: 29, class: fp64bit }
+  - { id: 30, class: fp64bit }
+  - { id: 31, class: fp64bit }
+  - { id: 32, class: fp64bit }
+  - { id: 33, class: fp64bit }
+  - { id: 34, class: fp64bit }
+  - { id: 35, class: fp64bit }
+liveins:         
+  - { reg: '%r2d', virtual-reg: '%0' }
+  - { reg: '%r3d', virtual-reg: '%1' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %r2d, %r3d
+  
+    %1 = COPY %r3d
+    %0 = COPY %r2d
+    %2 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %3 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %4 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %5 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %6 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %7 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %8 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %9 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %10 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %11 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %12 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %13 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %14 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %15 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %16 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %17 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    %18 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
+    STE %2, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %3, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %4, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %5, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %6, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %7, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %8, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %9, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %10, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %11, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %12, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %13, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %14, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %15, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %16, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %17, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    STE %18, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    %19 = LDEBR %2
+    STD %19, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %20 = LDEBR %3
+    STD %20, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %21 = LDEBR %4
+    STD %21, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %22 = LDEBR %5
+    STD %22, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %23 = LDEBR %6
+    STD %23, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %24 = LDEBR %7
+    STD %24, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %25 = LDEBR %8
+    STD %25, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %26 = LDEBR %9
+    STD %26, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %27 = LDEBR %10
+    STD %27, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %28 = LDEBR %11
+    STD %28, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %29 = LDEBR %12
+    STD %29, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %30 = LDEBR %13
+    STD %30, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %31 = LDEBR %14
+    STD %31, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %32 = LDEBR %15
+    STD %32, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %33 = LDEBR %16
+    STD %33, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %34 = LDEBR %17
+    STD %34, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    %35 = LDEBR %18
+    STD %35, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    Return
+
+...

test/CodeGen/SystemZ/fp-copysign-02.ll

; CHECK: br %r14
   ret double %res
 }
 
 ; Test f128 copies in which the sign comes from an f32.
 define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
 ; CHECK-LABEL: f7:
 ; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
 ; CHECK: tmlh
-; CHECK: wflnxb [[REG1]], [[REG1]]
-; CHECK: wflpxb [[REG1]], [[REG1]]
-; CHECK: vst [[REG1]], 0(%r2)
+; CHECK: wflnxb [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: wflpxb [[REG2]], [[REG1]]
+; CHECK: vst [[REG2]], 0(%r2)
 ; CHECK: br %r14
   %a = load volatile fp128, fp128 *%aptr
   %b = fpext float %bf to fp128
   %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
   store fp128 %c, fp128 *%cptr
   ret void
 }
 
 ; As above, but the sign comes from an f64.
 define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
 ; CHECK-LABEL: f8:
 ; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
 ; CHECK: tmhh
-; CHECK: wflnxb [[REG1]], [[REG1]]
-; CHECK: wflpxb [[REG1]], [[REG1]]
-; CHECK: vst [[REG1]], 0(%r2)
+; CHECK: wflnxb [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: wflpxb [[REG2]], [[REG1]]
+; CHECK: vst [[REG2]], 0(%r2)
 ; CHECK: br %r14
   %a = load volatile fp128, fp128 *%aptr
   %b = fpext double %bd to fp128
   %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
   store fp128 %c, fp128 *%cptr
   ret void
 }
 

test/CodeGen/SystemZ/fp-div-03.ll

 ; Test 128-bit floating-point division.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; There is no memory form of 128-bit division.
 define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK-LABEL: f1:
-; CHECK: lxebr %f0, %f0
-; CHECK: ld %f1, 0(%r2)
-; CHECK: ld %f3, 8(%r2)
+; CHECK-DAG: lxebr %f0, %f0
+; CHECK-DAG: ld %f1, 0(%r2)
+; CHECK-DAG: ld %f3, 8(%r2)
 ; CHECK: dxbr %f1, %f0
 ; CHECK: std %f1, 0(%r2)
 ; CHECK: std %f3, 8(%r2)
 ; CHECK: br %r14
   %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %sum = fdiv fp128 %f1, %f2x
   store fp128 %sum, fp128 *%ptr
   ret void
 }

test/CodeGen/SystemZ/fp-mul-05.ll

 ; Test multiplication of two f128s.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; There is no memory form of 128-bit multiplication.
 define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK-LABEL: f1:
-; CHECK: lxebr %f0, %f0
-; CHECK: ld %f1, 0(%r2)
-; CHECK: ld %f3, 8(%r2)
-; CHECK: mxbr %f1, %f0
-; CHECK: std %f1, 0(%r2)
-; CHECK: std %f3, 8(%r2)
+; CHECK-DAG: lxebr %f0, %f0
+; CHECK-DAG: ld %f1, 0(%r2)
+; CHECK-DAG: ld %f3, 8(%r2)
+; CHECK: mxbr %f0, %f1
+; CHECK: std %f0, 0(%r2)
+; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
   %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %diff = fmul fp128 %f1, %f2x
   store fp128 %diff, fp128 *%ptr
   ret void
 }

test/CodeGen/SystemZ/fp-sub-03.ll

 ; Test 128-bit floating-point subtraction.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; There is no memory form of 128-bit subtraction.
 define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK-LABEL: f1:
-; CHECK: lxebr %f0, %f0
-; CHECK: ld %f1, 0(%r2)
-; CHECK: ld %f3, 8(%r2)
+; CHECK-DAG: lxebr %f0, %f0
+; CHECK-DAG: ld %f1, 0(%r2)
+; CHECK-DAG: ld %f3, 8(%r2)
 ; CHECK: sxbr %f1, %f0
 ; CHECK: std %f1, 0(%r2)
 ; CHECK: std %f3, 8(%r2)
 ; CHECK: br %r14
   %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %sum = fsub fp128 %f1, %f2x
   store fp128 %sum, fp128 *%ptr
   ret void
 }

test/CodeGen/SystemZ/pr32505.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s
 
 target triple = "s390x-ibm-linux"
 
 define <2 x float> @pr32505(<2 x i8> * %a) {
 ; CHECK-LABEL: pr32505:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    lbh %r0, 0(%r2)
-; CHECK-NEXT:    ldgr %f0, %r0
 ; CHECK-NEXT:    lbh %r0, 1(%r2)
+; CHECK-NEXT:    lbh %r1, 0(%r2)
+; CHECK-NEXT:    ldgr %f0, %r1
 ; CHECK-NEXT:    ldgr %f2, %r0
 ; CHECK-NEXT:    # kill: %F0S<def> %F0S<kill> %F0D<kill>
 ; CHECK-NEXT:    # kill: %F2S<def> %F2S<kill> %F2D<kill>
 ; CHECK-NEXT:    br %r14
   %L17 = load <2 x i8>, <2 x i8>* %a
   %Se21 = sext <2 x i8> %L17 to <2 x i32>
   %BC = bitcast <2 x i32> %Se21 to <2 x float>
   ret <2 x float> %BC
 }

test/CodeGen/SystemZ/swift-return.ll

 ; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s
 
 @var = global i32 0
 
 ; Test how llvm handles return type of {i16, i8}. The return value will be
 ; passed in %r2 and %r3.
 ; CHECK-LABEL: test:
 ; CHECK: st %r2
 ; CHECK: brasl %r14, gen
-; CHECK-DAG: lhr %r2, %r2
-; CHECK-DAG: lbr %[[REG1:r[0-9]+]], %r3
-; CHECK: ar %r2, %[[REG1]]
+; CHECK-DAG: lhr %{{r[0,2]+}}, %r2
+; CHECK-DAG: lbr %{{r[0,2]+}}, %r3
+; CHECK: ar %r2, %r0
 ; CHECK-O0-LABEL: test
 ; CHECK-O0: st %r2
 ; CHECK-O0: brasl %r14, gen
 ; CHECK-O0-DAG: lhr %[[REG1:r[0-9]+]], %r2
 ; CHECK-O0-DAG: lbr %[[REG2:r[0-9]+]], %r3
 ; CHECK-O0: ar %[[REG1]], %[[REG2]]
 ; CHECK-O0: lr %r2, %[[REG1]]
 define i16 @test(i32 %key) {

test/CodeGen/SystemZ/tdc-06.ll

 ; Test the Test Data Class instruction, as used by fpclassify.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ;
 
 declare float @llvm.fabs.f32(float)
 declare double @llvm.fabs.f64(double)
 declare fp128 @llvm.fabs.f128(fp128)
 
 define i32 @fpc(double %x) {
 entry:
 ; CHECK-LABEL: fpc
-; CHECK: lhi %r2, 5
-; CHECK: ltdbr %f0, %f0
+; CHECK-DAG: lhi %r2, 5
+; CHECK-DAG: ltdbr %f0, %f0
 ; CHECK: je [[RET:.L.*]]
   %testeq = fcmp oeq double %x, 0.000000e+00
   br i1 %testeq, label %ret, label %nonzero, !prof !1
 
 nonzero:
-; CHECK: lhi %r2, 1
-; CHECK: cdbr %f0, %f0
+; CHECK-DAG: lhi %r2, 1
+; CHECK-DAG: cdbr %f0, %f0
 ; CHECK: jo [[RET]]
   %testnan = fcmp uno double %x, 0.000000e+00
   br i1 %testnan, label %ret, label %nonzeroord, !prof !1
 
 nonzeroord:
-; CHECK: lhi %r2, 2
-; CHECK: tcdb %f0, 48
+; CHECK-DAG: lhi %r2, 2
+; CHECK-DAG: tcdb %f0, 48
 ; CHECK: jl [[RET]]
   %abs = tail call double @llvm.fabs.f64(double %x)
   %testinf = fcmp oeq double %abs, 0x7FF0000000000000
   br i1 %testinf, label %ret, label %finite, !prof !1
 
 finite:
-; CHECK: lhi %r2, 3
-; CHECK: tcdb %f0, 831
+; CHECK-DAG: lhi %r2, 3
+; CHECK-DAG: tcdb %f0, 831
 ; CHECK: blr %r14
 ; CHECK: lhi %r2, 4
   %testnormal = fcmp uge double %abs, 0x10000000000000
   %finres = select i1 %testnormal, i32 3, i32 4
   br label %ret
 
 ret:
 ; CHECK: [[RET]]:
 ; CHECK: br %r14
   %res = phi i32 [ 5, %entry ], [ 1, %nonzero ], [ 2, %nonzeroord ], [ %finres, %finite ]
   ret i32 %res
 }
 
 !1 = !{!"branch_weights", i32 1, i32 1}

test/CodeGen/SystemZ/tls-01.ll

 ; Test local-exec TLS accesses.
 ;
 ; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
 ; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP
 
 @x = thread_local global i32 0
 
 ; The offset must be loaded from the constant pool.  It doesn't really
 ; matter whether we use LARL/AG or LGRL/AGR for the last part.
 define i32 *@foo() {
 ; CHECK-CP: .LCP{{.*}}:
 ; CHECK-CP: .quad x@NTPOFF
 ;
 ; CHECK-MAIN-LABEL: foo:
 ; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
 ; CHECK-MAIN: sllg %r2, [[HIGH]], 32
-; CHECK-MAIN: ear %r2, %a1
-; CHECK-MAIN: larl %r1, .LCP{{.*}}
+; CHECK-MAIN-DAG: ear %r2, %a1
+; CHECK-MAIN-DAG: larl %r1, .LCP{{.*}}
 ; CHECK-MAIN: ag %r2, 0(%r1)
 ; CHECK-MAIN: br %r14
   ret i32 *@x
 }

test/CodeGen/SystemZ/tls-02.ll

 ; Test initial-exec TLS accesses.
 ;
 ; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN
 
 @x = thread_local(initialexec) global i32 0
 
 ; The offset must be loaded from the GOT.  This TLS access model does
 ; not use literal pool constants.
 define i32 *@foo() {
 ; CHECK-MAIN-LABEL: foo:
 ; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
 ; CHECK-MAIN: sllg %r2, [[HIGH]], 32
-; CHECK-MAIN: ear %r2, %a1
-; CHECK-MAIN: larl %r1, x@INDNTPOFF
+; CHECK-MAIN-DAG: ear %r2, %a1
+; CHECK-MAIN-DAG: larl %r1, x@INDNTPOFF
 ; CHECK-MAIN: ag %r2, 0(%r1)
 ; CHECK-MAIN: br %r14
   ret i32 *@x
 }

test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;
 ; Test that a vector select with a logic combination of two compares do not
 ; produce any unnecessary pack, unpack or shift instructions.
 ; And, Or and Xor are tested.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13   | FileCheck %s
-
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CHECK-Z14
 
 define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
 ; CHECK-LABEL: fun0:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
+; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i8> %val1, %val2
   %cmp1 = icmp eq <2 x i8> %val3, %val4
   %and = and <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
   ret <2 x i8> %sel
 }
 
 define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
 ; CHECK-LABEL: fun1:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
+; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
 ; CHECK-NEXT:    vuphb %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i8> %val1, %val2
   %cmp1 = icmp eq <2 x i8> %val3, %val4
   %and = and <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
   ret <2 x i16> %sel
 }
 
-define <2 x i8> @fun2(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i8> %val5, <2 x i8> %val6) {
+define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
 ; CHECK-LABEL: fun2:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v1, %v28, %v30
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vpkh %v1, %v1, %v1
-; CHECK-NEXT:    vn %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v30, %v27
+; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v25
+; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vpkh [[REG3:%v[0-9]+]], [[REG1]], [[REG0]]
+; CHECK-NEXT:    vo %v0, [[REG2]], [[REG3]]
+; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
+  %cmp0 = icmp eq <16 x i8> %val1, %val2
+  %cmp1 = icmp eq <16 x i16> %val3, %val4
+  %and = or <16 x i1> %cmp0, %cmp1
+  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
+  ret <16 x i8> %sel
 }
 
-define <2 x i32> @fun3(<2 x i8> %val1, <2 x i8> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i32> %val5, <2 x i32> %val6) {
+define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
 ; CHECK-LABEL: fun3:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vuphb [[REG2:%v[0-9]+]], [[REG0]]
+; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
+; CHECK-DAG:     vuphb [[REG1]], [[REG1]]
+; CHECK-DAG:     vceqh [[REG3:%v[0-9]+]], %v28, %v25
+; CHECK-DAG:     vceqh [[REG4:%v[0-9]+]], %v30, %v27
+; CHECK-DAG:     vl [[REG5:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vo [[REG7:%v[0-9]+]], %v2, [[REG4]]
+; CHECK-DAG:     vo [[REG8:%v[0-9]+]], [[REG2]], [[REG3]]
+; CHECK-DAG:     vsel %v24, %v29, [[REG6]], [[REG8]]
+; CHECK-DAG:     vsel %v26, %v31, [[REG5]], [[REG7]]
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
+  %cmp0 = icmp eq <16 x i8> %val1, %val2
+  %cmp1 = icmp eq <16 x i16> %val3, %val4
+  %and = or <16 x i1> %cmp0, %cmp1
+  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
+  ret <16 x i16> %sel
 }
 
-define <2 x i32> @fun4(<2 x i8> %val1, <2 x i8> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
+define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
 ; CHECK-LABEL: fun4:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
+; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v25, %v29
+; CHECK-DAG:     vceqb [[REG3:%v[0-9]+]], %v27, %v31
+; CHECK-DAG:     vl [[REG4:%v[0-9]+]], 208(%r15)
+; CHECK-DAG:     vl [[REG5:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 192(%r15)
+; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vx [[REG8:%v[0-9]+]], [[REG1]], [[REG3]]
+; CHECK-DAG:     vx [[REG9:%v[0-9]+]], [[REG0]], [[REG2]]
+; CHECK-DAG:     vsel %v24, [[REG7]], [[REG6]], [[REG9]]
+; CHECK-DAG:     vsel %v26, [[REG5]], [[REG4]], [[REG8]]
+; CHECK-NEXT:    br %r14
+  %cmp0 = icmp eq <32 x i8> %val1, %val2
+  %cmp1 = icmp eq <32 x i8> %val3, %val4
+  %and = xor <32 x i1> %cmp0, %cmp1
+  %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
+  ret <32 x i8> %sel
 }
 
-define <2 x i16> @fun5(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i16> %val5, <2 x i16> %val6) {
+define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
 ; CHECK-LABEL: fun5:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i64> @fun6(<2 x i8> %val1, <2 x i8> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun6:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i8> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun7:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vpkh [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
+; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v28, %v30
+; CHECK-DAG:     vo %v0, [[REG1]], [[REG2]]
+; CHECK-DAG:     vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
+  %cmp1 = icmp eq <2 x i8> %val3, %val4
+  %and = or <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
   ret <2 x i8> %sel
 }
 
-define <2 x i16> @fun8(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun8:
+define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
+; CHECK-LABEL: fun6:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
+; CHECK-NEXT:    vceqb %v1, %v28, %v30
+; CHECK-NEXT:    vceqh %v0, %v24, %v26
+; CHECK-NEXT:    vuphb %v1, %v1
+; CHECK-NEXT:    vo %v0, %v0, %v1
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
+  %cmp1 = icmp eq <2 x i8> %val3, %val4
+  %and = or <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
   ret <2 x i16> %sel
 }
 
-define <2 x i32> @fun9(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun9:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i8> @fun10(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun10:
+define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i32> %val5, <2 x i32> %val6) {
+; CHECK-LABEL: fun7:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v28, %v30
+; CHECK-NEXT:    vceqb %v1, %v28, %v30
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vpkf %v1, %v1, %v1
-; CHECK-NEXT:    vn %v0, %v0, %v1
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i8> @fun11(<2 x i16> %val1, <2 x i16> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun11:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI11_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x double> @fun12(<2 x i16> %val1, <2 x i16> %val2, <2 x float> %val3, <2 x float> %val4, <2 x double> %val5, <2 x double> %val6) {
-; CHECK-LABEL: fun12:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
-  ret <2 x double> %sel
-}
-
-define <2 x i16> @fun13(<2 x i16> %val1, <2 x i16> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun13:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI13_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
+; CHECK-NEXT:    vuphb %v1, %v1
+; CHECK-NEXT:    vo %v0, %v0, %v1
+; CHECK-NEXT:    vuphh %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i16> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun14:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun15:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i64> @fun16(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun16:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i64> @fun17(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun17:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i16> @fun18(<2 x i32> %val1, <2 x i32> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun18:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x float> @fun19(<2 x i32> %val1, <2 x i32> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
-; CHECK-LABEL: fun19:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v1, %v28, %v30
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vpkg %v1, %v1, %v1
-; CHECK-NEXT:    vn %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
-  ret <2 x float> %sel
-}
-
-define <2 x i16> @fun20(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun20:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI20_0
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i64> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun21:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun22:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i16> @fun23(<2 x i64> %val1, <2 x i64> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun23:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI23_0
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x float> @fun24(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4, <2 x float> %val5, <2 x float> %val6) {
-; CHECK-LABEL: fun24:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <2 x float> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
-  ret <2 x float> %sel
-}
-
-define <2 x i32> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun25:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v28, %v30
-; CHECK-NEXT:    vpkg %v1, %v1, %v1
-; CHECK-NEXT:    vn %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <2 x float> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = and <2 x i1> %cmp0, %cmp1
+  %cmp1 = icmp eq <2 x i8> %val3, %val4
+  %and = or <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
   ret <2 x i32> %sel
 }
 
-define <4 x i16> @fun26(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun26:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x i32> @fun27(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun27:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun28(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun28:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x i32> @fun29(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun29:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v30, %v27
-; CHECK-NEXT:    vceqg %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i16> @fun30(<4 x i32> %val1, <4 x i32> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun30:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x i8> @fun31(<4 x i32> %val1, <4 x i32> %val2, <4 x double> %val3, <4 x double> %val4, <4 x i8> %val5, <4 x i8> %val6) {
-; CHECK-LABEL: fun31:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v27
-; CHECK-NEXT:    vfchdb %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI31_0
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i8> %val5, <4 x i8> %val6
-  ret <4 x i8> %sel
-}
-
-define <4 x i32> @fun32(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun32:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v29
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun33(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun33:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v25, %v29
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqg %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x i64> @fun34(<4 x i64> %val1, <4 x i64> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun34:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v2, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x float> @fun35(<4 x i64> %val1, <4 x i64> %val2, <4 x double> %val3, <4 x double> %val4, <4 x float> %val5, <4 x float> %val6) {
-; CHECK-LABEL: fun35:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v29
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
-  ret <4 x float> %sel
-}
-
-define <4 x i16> @fun36(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun36:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x float> @fun37(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
-; CHECK-LABEL: fun37:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
-  ret <4 x float> %sel
-}
-
-define <4 x double> @fun38(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
-; CHECK-LABEL: fun38:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6
-  ret <4 x double> %sel
-}
-
-define <4 x i8> @fun39(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4, <4 x i8> %val5, <4 x i8> %val6) {
-; CHECK-LABEL: fun39:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v27
-; CHECK-NEXT:    vfchdb %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    larl %r1, .LCPI39_0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = and <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i8> %val5, <4 x i8> %val6
-  ret <4 x i8> %sel
-}
-
-define <8 x i8> @fun40(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
-; CHECK-LABEL: fun40:
+define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
+; CHECK-LABEL: fun8:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
+; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
 ; CHECK-NEXT:    vpkh %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <8 x i16> %val1, %val2
   %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
+  %and = xor <8 x i1> %cmp0, %cmp1
   %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
   ret <8 x i8> %sel
 }
 
-define <8 x i16> @fun41(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
-; CHECK-LABEL: fun41:
+define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
+; CHECK-LABEL: fun9:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
+; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <8 x i16> %val1, %val2
   %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
+  %and = xor <8 x i1> %cmp0, %cmp1
   %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
   ret <8 x i16> %sel
 }
 
-define <8 x i32> @fun42(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun42:
+define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
+; CHECK-LABEL: fun10:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
+; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vx [[REG2:%v[0-9]+]], [[REG0]], [[REG1]]
+; CHECK-DAG:     vuphh [[REG3:%v[0-9]+]], [[REG2]]
+; CHECK-DAG:     vmrlg [[REG4:%v[0-9]+]], [[REG2]], [[REG2]]
+; CHECK-DAG:     vuphh [[REG5:%v[0-9]+]], [[REG4]]
+; CHECK-NEXT:    vsel %v24, %v25, %v29, [[REG3]]
+; CHECK-NEXT:    vsel %v26, %v27, %v31, [[REG5]]
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <8 x i16> %val1, %val2
   %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun43(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i64> %val5, <8 x i64> %val6) {
-; CHECK-LABEL: fun43:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vceqf %v0, %v28, %v25
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v31, %v2, %v0
-; CHECK-NEXT:    vceqf %v0, %v30, %v27
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i32> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i64> %val5, <8 x i64> %val6
-  ret <8 x i64> %sel
-}
-
-define <8 x i8> @fun44(<8 x i16> %val1, <8 x i16> %val2, <8 x i64> %val3, <8 x i64> %val4, <8 x i8> %val5, <8 x i8> %val6) {
-; CHECK-LABEL: fun44:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v30, %v31
-; CHECK-NEXT:    vceqg %v2, %v28, %v29
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vlrepg %v1, 200(%r15)
-; CHECK-NEXT:    vlrepg %v2, 192(%r15)
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i64> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun45(<8 x i16> %val1, <8 x i16> %val2, <8 x float> %val3, <8 x float> %val4, <8 x i16> %val5, <8 x i16> %val6) {
-; CHECK-LABEL: fun45:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <8 x float> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun46(<8 x i16> %val1, <8 x i16> %val2, <8 x double> %val3, <8 x double> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun46:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x i32> @fun47(<8 x i32> %val1, <8 x i32> %val2, <8 x i64> %val3, <8 x i64> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun47:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = icmp eq <8 x i64> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
+  %and = xor <8 x i1> %cmp0, %cmp1
   %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
   ret <8 x i32> %sel
 }
 
-define <8 x double> @fun48(<8 x i32> %val1, <8 x i32> %val2, <8 x float> %val3, <8 x float> %val4, <8 x double> %val5, <8 x double> %val6) {
-; CHECK-LABEL: fun48:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v29, %v29
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v29, %v29
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v31, %v31
-; CHECK-NEXT:    vmrlf %v2, %v27, %v27
-; CHECK-NEXT:    vmrhf %v3, %v27, %v27
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v31, %v31
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vceqf %v2, %v26, %v30
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <8 x float> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x double> %val5, <8 x double> %val6
-  ret <8 x double> %sel
-}
-
-define <8 x double> @fun49(<8 x i32> %val1, <8 x i32> %val2, <8 x double> %val3, <8 x double> %val4, <8 x double> %val5, <8 x double> %val6) {
-; CHECK-LABEL: fun49:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vfchdb %v0, %v25, %v0
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vceqf %v2, %v26, %v30
-; CHECK-NEXT:    vfchdb %v0, %v29, %v0
-; CHECK-NEXT:    vuphf %v3, %v2
-; CHECK-NEXT:    vn %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x double> %val5, <8 x double> %val6
-  ret <8 x double> %sel
-}
-
-define <8 x i64> @fun50(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x i64> %val5, <8 x i64> %val6) {
-; CHECK-LABEL: fun50:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 224(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vn %v1, %v1, %v2
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vfchdb %v3, %v29, %v3
-; CHECK-NEXT:    vn %v2, %v2, %v3
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v27, %v2
-; CHECK-NEXT:    vn %v0, %v0, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vfchdb %v1, %v31, %v1
-; CHECK-NEXT:    vn %v0, %v0, %v1
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <8 x float> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = and <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i64> %val5, <8 x i64> %val6
-  ret <8 x i64> %sel
-}
-
-define <16 x i8> @fun51(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun51:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i8> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun52(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun52:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i8> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i64> @fun53(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun53:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vceqh %v0, %v28, %v25
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vuphh %v2, %v0
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v24, %v29, %v3, %v2
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v26, %v31, %v3, %v2
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v3, 288(%r15)
-; CHECK-NEXT:    vl %v4, 160(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v0, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vceqh %v2, %v30, %v27
-; CHECK-NEXT:    vlr %v30, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vn %v1, %v1, %v2
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v25, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v3, 336(%r15)
-; CHECK-NEXT:    vl %v4, 208(%r15)
-; CHECK-NEXT:    vpkg %v2, %v1, %v1
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v27, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vmrlg %v2, %v1, %v1
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v1, %v1, %v1, 12
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v29, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i64> @fun54(<16 x i8> %val1, <16 x i8> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun54:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vceqf %v0, %v28, %v29
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vl %v3, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vpkg %v2, %v1, %v1
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vl %v5, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vmrlg %v3, %v1, %v1
-; CHECK-NEXT:    vuphb %v3, %v3
-; CHECK-NEXT:    vceqf %v2, %v25, %v2
-; CHECK-NEXT:    vuphh %v3, %v3
-; CHECK-NEXT:    vn %v2, %v3, %v2
-; CHECK-NEXT:    vuphf %v3, %v2
-; CHECK-NEXT:    vsldb %v1, %v1, %v1, 12
-; CHECK-NEXT:    vsel %v25, %v5, %v4, %v3
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vl %v4, 416(%r15)
-; CHECK-NEXT:    vl %v5, 288(%r15)
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vceqf %v3, %v27, %v3
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v1, %v1, %v3
-; CHECK-NEXT:    vuphf %v3, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v5, %v4, %v3
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vl %v4, 240(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i32> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i64> @fun55(<16 x i8> %val1, <16 x i8> %val2, <16 x i64> %val3, <16 x i64> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun55:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vceqg %v1, %v28, %v0
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 448(%r15)
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vpkf %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v30, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 464(%r15)
-; CHECK-NEXT:    vl %v3, 336(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v1
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 480(%r15)
-; CHECK-NEXT:    vsel %v28, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 6
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v27, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 496(%r15)
-; CHECK-NEXT:    vsel %v30, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v3, 384(%r15)
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 512(%r15)
-; CHECK-NEXT:    vsel %v25, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v3, 400(%r15)
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 10
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v31, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 528(%r15)
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 288(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vl %v3, 416(%r15)
-; CHECK-NEXT:    vceqg %v1, %v2, %v1
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 12
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 14
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 544(%r15)
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 432(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vn %v0, %v0, %v1
-; CHECK-NEXT:    vl %v1, 560(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i64> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i16> @fun56(<16 x i8> %val1, <16 x i8> %val2, <16 x float> %val3, <16 x float> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun56:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vmrlf %v4, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v29, %v29
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vmrlf %v2, %v0, %v0
-; CHECK-NEXT:    vmrlf %v3, %v27, %v27
-; CHECK-NEXT:    vmrhf %v0, %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vmrhf %v3, %v27, %v27
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v0, %v3, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v2
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vpkf %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <16 x float> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i8> @fun57(<16 x i8> %val1, <16 x i8> %val2, <16 x double> %val3, <16 x double> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun57:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 288(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v31, %v1
-; CHECK-NEXT:    vfchdb %v2, %v29, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v27, %v1
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v30, %v2
-; CHECK-NEXT:    vfchdb %v3, %v28, %v3
-; CHECK-NEXT:    vpkg %v2, %v3, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <16 x double> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i8> @fun58(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun58:
+define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
+; CHECK-LABEL: fun11:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v27, %v31
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v25, %v29
-; CHECK-NEXT:    vceqh %v2, %v24, %v28
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
+; CHECK-DAG:     vl [[REG0:%v[0-9]+]], 192(%r15)
+; CHECK-DAG:     vl [[REG1:%v[0-9]+]], 208(%r15)
+; CHECK-DAG:     vl [[REG2:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vl [[REG3:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vceqf [[REG4:%v[0-9]+]], %v27, [[REG3]]
+; CHECK-DAG:     vceqf [[REG5:%v[0-9]+]], %v25, [[REG2]]
+; CHECK-DAG:     vceqf [[REG6:%v[0-9]+]], %v31, [[REG1]]
+; CHECK-DAG:     vceqf [[REG7:%v[0-9]+]], %v29, [[REG0]]
+; CHECK-DAG:     vceqh [[REG8:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vceqh [[REG9:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vpkf [[REG10:%v[0-9]+]], [[REG5]], [[REG4]]
+; CHECK-DAG:     vpkf [[REG11:%v[0-9]+]], [[REG7]], [[REG6]]
+; CHECK-DAG:     vn [[REG12:%v[0-9]+]], [[REG9]], [[REG11]]
+; CHECK-DAG:     vn [[REG13:%v[0-9]+]], [[REG8]], [[REG10]]
+; CHECK-DAG:     vl [[REG14:%v[0-9]+]], 240(%r15)
+; CHECK-DAG:     vl [[REG15:%v[0-9]+]], 224(%r15)
+; CHECK-DAG:     vpkh [[REG16:%v[0-9]+]], [[REG13]], [[REG12]]
+; CHECK-NEXT:    vsel %v24, [[REG15]], [[REG14]], [[REG16]]
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
+  %cmp1 = icmp eq <16 x i32> %val3, %val4
   %and = and <16 x i1> %cmp0, %cmp1
   %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
   ret <16 x i8> %sel
 }
 
-define <16 x i16> @fun59(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun59:
+define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i16> %val5, <16 x i16> %val6) {
+; CHECK-LABEL: fun12:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v25, %v29
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqh %v0, %v27, %v31
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
+; CHECK-DAG:     vl [[REG0:%v[0-9]+]], 192(%r15)
+; CHECK-DAG:     vl [[REG1:%v[0-9]+]], 208(%r15)
+; CHECK-DAG:     vl [[REG2:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vl [[REG3:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vceqf [[REG4:%v[0-9]+]], %v27, [[REG3]]
+; CHECK-DAG:     vceqf [[REG5:%v[0-9]+]], %v25, [[REG2]]
+; CHECK-DAG:     vceqf [[REG6:%v[0-9]+]], %v31, [[REG1]]
+; CHECK-DAG:     vceqf [[REG7:%v[0-9]+]], %v29, [[REG0]]
+; CHECK-DAG:     vceqh [[REG8:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vceqh [[REG9:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vpkf [[REG10:%v[0-9]+]], [[REG5]], [[REG4]]
+; CHECK-DAG:     vpkf [[REG11:%v[0-9]+]], [[REG7]], [[REG6]]
+; CHECK-DAG:     vl [[REG12:%v[0-9]+]], 272(%r15)
+; CHECK-DAG:     vl [[REG13:%v[0-9]+]], 240(%r15)
+; CHECK-DAG:     vl [[REG14:%v[0-9]+]], 256(%r15)
+; CHECK-DAG:     vl [[REG15:%v[0-9]+]], 224(%r15)
+; CHECK-DAG:     vn [[REG16:%v[0-9]+]], [[REG9]], [[REG11]]
+; CHECK-DAG:     vn [[REG17:%v[0-9]+]], [[REG8]], [[REG10]]
+; CHECK-DAG:     vsel %v24, [[REG15]], [[REG14]], [[REG17]]
+; CHECK-DAG:     vsel %v26, [[REG13]], [[REG12]], [[REG16]]
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
+  %cmp1 = icmp eq <16 x i32> %val3, %val4
   %and = and <16 x i1> %cmp0, %cmp1
   %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
   ret <16 x i16> %sel
 }
 
-define <16 x i32> @fun60(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun60:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v25, %v29
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v27, %v31
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <16 x i8> @fun61(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun61:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqf %v0, %v31, %v0
-; CHECK-NEXT:    vceqf %v1, %v29, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqf %v1, %v27, %v1
-; CHECK-NEXT:    vceqf %v2, %v25, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vceqh %v2, %v24, %v28
-; CHECK-NEXT:    vn %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i32> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i32> @fun62(<16 x i16> %val1, <16 x i16> %val2, <16 x i64> %val3, <16 x i64> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun62:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 416(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqg %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vceqg %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vuphh %v3, %v2
-; CHECK-NEXT:    vn %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 448(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v3, %v29, %v3
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v3, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 336(%r15)
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vceqg %v1, %v3, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i64> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <16 x double> @fun63(<16 x i16> %val1, <16 x i16> %val2, <16 x float> %val3, <16 x float> %val4, <16 x double> %val5, <16 x double> %val6) {
-; CHECK-LABEL: fun63:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vmrlf %v1, %v0, %v0
-; CHECK-NEXT:    vmrlf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v0, %v0, %v0
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vl %v5, 416(%r15)
-; CHECK-NEXT:    vl %v6, 288(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vsel %v24, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrlf %v4, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v27, %v27
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vl %v3, 384(%r15)
-; CHECK-NEXT:    vn %v1, %v1, %v2
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrlf %v4, %v29, %v29
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vceqh %v3, %v26, %v30
-; CHECK-NEXT:    vuphh %v4, %v3
-; CHECK-NEXT:    vn %v2, %v4, %v2
-; CHECK-NEXT:    vuphf %v4, %v2
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vl %v4, 208(%r15)
-; CHECK-NEXT:    vmrlf %v5, %v4, %v4
-; CHECK-NEXT:    vmrlf %v6, %v31, %v31
-; CHECK-NEXT:    vmrhf %v4, %v4, %v4
-; CHECK-NEXT:    vmrlg %v3, %v3, %v3
-; CHECK-NEXT:    vuphh %v3, %v3
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v5, %v6, %v5
-; CHECK-NEXT:    vmrhf %v6, %v31, %v31
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v4, %v6, %v4
-; CHECK-NEXT:    vl %v6, 320(%r15)
-; CHECK-NEXT:    vpkg %v4, %v4, %v5
-; CHECK-NEXT:    vl %v5, 448(%r15)
-; CHECK-NEXT:    vn %v3, %v3, %v4
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v29, %v6, %v5, %v4
-; CHECK-NEXT:    vl %v4, 368(%r15)
-; CHECK-NEXT:    vl %v5, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v5, %v4, %v0
-; CHECK-NEXT:    vl %v4, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v4, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v2, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v3, %v3
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <16 x float> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x double> %val5, <16 x double> %val6
-  ret <16 x double> %sel
-}
-
-define <16 x i32> @fun64(<16 x i16> %val1, <16 x i16> %val2, <16 x double> %val3, <16 x double> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun64:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vn %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 416(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vuphh %v3, %v2
-; CHECK-NEXT:    vn %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 448(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v3, %v29, %v3
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v3, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 336(%r15)
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v3, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vn %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <16 x double> %val3, %val4
-  %and = and <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <2 x i8> @fun65(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun65:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i8> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i16> @fun66(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun66:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i8> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i8> @fun67(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun67:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v1, %v28, %v30
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vpkh %v1, %v1, %v1
-; CHECK-NEXT:    vo %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i32> @fun68(<2 x i8> %val1, <2 x i8> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun68:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i32> @fun69(<2 x i8> %val1, <2 x i8> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun69:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i16> @fun70(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun70:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i64> @fun71(<2 x i8> %val1, <2 x i8> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun71:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i8> @fun72(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun72:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i16> @fun73(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun73:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun74(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun74:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i8> @fun75(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun75:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v28, %v30
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vpkf %v1, %v1, %v1
-; CHECK-NEXT:    vo %v0, %v0, %v1
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i8> @fun76(<2 x i16> %val1, <2 x i16> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun76:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI76_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x double> @fun77(<2 x i16> %val1, <2 x i16> %val2, <2 x float> %val3, <2 x float> %val4, <2 x double> %val5, <2 x double> %val6) {
-; CHECK-LABEL: fun77:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
-  ret <2 x double> %sel
-}
-
-define <2 x i16> @fun78(<2 x i16> %val1, <2 x i16> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun78:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI78_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i16> @fun79(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun79:
+define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
+; CHECK-LABEL: fun13:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
+; CHECK-NEXT:    vceqg %v1, %v28, %v30
+; CHECK-NEXT:    vceqf %v0, %v24, %v26
+; CHECK-NEXT:    vpkg %v1, %v1, %v1
+; CHECK-NEXT:    vx %v0, %v0, %v1
 ; CHECK-NEXT:    vpkf %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun80(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun80:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i64> @fun81(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun81:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i64> @fun82(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun82:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
   %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i16> @fun83(<2 x i32> %val1, <2 x i32> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun83:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
+  %and = xor <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
   ret <2 x i16> %sel
 }
 
-define <2 x float> @fun84(<2 x i32> %val1, <2 x i32> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
-; CHECK-LABEL: fun84:
+define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
+; CHECK-LABEL: fun14:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v1, %v28, %v30
+; CHECK-NEXT:    vceqg %v1, %v28, %v30
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkg %v1, %v1, %v1
-; CHECK-NEXT:    vo %v0, %v0, %v1
+; CHECK-NEXT:    vx %v0, %v0, %v1
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
-  ret <2 x float> %sel
-}
-
-define <2 x i16> @fun85(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun85:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI85_0
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
   %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
+  %and = xor <2 x i1> %cmp0, %cmp1
+  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
+  ret <2 x i32> %sel
 }
 
-define <2 x i64> @fun86(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun86:
+define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
+; CHECK-LABEL: fun15:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
+; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vuphf [[REG1:%v[0-9]+]], [[REG0]]
+; CHECK-DAG:     vceqg [[REG2:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vx %v0, [[REG1]], [[REG2]]
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
+  %cmp0 = icmp eq <2 x i32> %val1, %val2
   %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i64> @fun87(<2 x i64> %val1, <2 x i64> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun87:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
+  %and = xor <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
   ret <2 x i64> %sel
 }
 
-define <2 x i16> @fun88(<2 x i64> %val1, <2 x i64> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun88:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI88_0
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x float> @fun89(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4, <2 x float> %val5, <2 x float> %val6) {
-; CHECK-LABEL: fun89:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <2 x float> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
-  ret <2 x float> %sel
-}
-
-define <2 x i32> @fun90(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun90:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v28, %v30
-; CHECK-NEXT:    vpkg %v1, %v1, %v1
-; CHECK-NEXT:    vo %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <2 x float> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = or <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <4 x i16> @fun91(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun91:
+define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i16> %val5, <4 x i16> %val6) {
+; CHECK-LABEL: fun16:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
+; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vpkf [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
+; CHECK-DAG:     vceqh [[REG2:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vn %v0, [[REG1]], [[REG2]]
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
+  %cmp1 = icmp eq <4 x i16> %val3, %val4
+  %and = and <4 x i1> %cmp0, %cmp1
   %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
   ret <4 x i16> %sel
 }
 
-define <4 x i32> @fun92(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun92:
+define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i32> %val5, <4 x i32> %val6) {
+; CHECK-LABEL: fun17:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
+; CHECK-NEXT:    vceqh %v1, %v28, %v30
+; CHECK-NEXT:    vceqf %v0, %v24, %v26
+; CHECK-NEXT:    vuphh %v1, %v1
+; CHECK-NEXT:    vn %v0, %v0, %v1
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun93(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun93:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x i32> @fun94(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun94:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v30, %v27
-; CHECK-NEXT:    vceqg %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
+  %cmp1 = icmp eq <4 x i16> %val3, %val4
+  %and = and <4 x i1> %cmp0, %cmp1
   %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
   ret <4 x i32> %sel
 }
 
-define <4 x i16> @fun95(<4 x i32> %val1, <4 x i32> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun95:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x i8> @fun96(<4 x i32> %val1, <4 x i32> %val2, <4 x double> %val3, <4 x double> %val4, <4 x i8> %val5, <4 x i8> %val6) {
-; CHECK-LABEL: fun96:
+define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i64> %val5, <4 x i64> %val6) {
+; CHECK-LABEL: fun18:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v27
-; CHECK-NEXT:    vfchdb %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI96_0
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
+; CHECK-NEXT:    vceqh %v1, %v28, %v30
+; CHECK-NEXT:    vceqf %v0, %v24, %v26
+; CHECK-NEXT:    vuphh %v1, %v1
+; CHECK-NEXT:    vn %v0, %v0, %v1
+; CHECK-DAG:     vuphf [[REG0:%v[0-9]+]], %v0
+; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
+; CHECK-DAG:     vuphf [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK-NEXT:    vsel %v24, %v25, %v29, [[REG0]]
+; CHECK-NEXT:    vsel %v26, %v27, %v31, [[REG2]]
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i8> %val5, <4 x i8> %val6
-  ret <4 x i8> %sel
-}
-
-define <4 x i32> @fun97(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun97:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v29
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun98(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun98:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v25, %v29
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqg %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x i64> @fun99(<4 x i64> %val1, <4 x i64> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun99:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v2, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
+  %cmp1 = icmp eq <4 x i16> %val3, %val4
+  %and = and <4 x i1> %cmp0, %cmp1
   %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
   ret <4 x i64> %sel
 }
 
-define <4 x float> @fun100(<4 x i64> %val1, <4 x i64> %val2, <4 x double> %val3, <4 x double> %val4, <4 x float> %val5, <4 x float> %val6) {
-; CHECK-LABEL: fun100:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v29
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
-  ret <4 x float> %sel
-}
-
-define <4 x i16> @fun101(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun101:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x float> @fun102(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
-; CHECK-LABEL: fun102:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
-  ret <4 x float> %sel
-}
-
-define <4 x double> @fun103(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
-; CHECK-LABEL: fun103:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6
-  ret <4 x double> %sel
-}
-
-define <4 x i8> @fun104(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4, <4 x i8> %val5, <4 x i8> %val6) {
-; CHECK-LABEL: fun104:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v27
-; CHECK-NEXT:    vfchdb %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    larl %r1, .LCPI104_0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = or <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i8> %val5, <4 x i8> %val6
-  ret <4 x i8> %sel
-}
-
-define <8 x i8> @fun105(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
-; CHECK-LABEL: fun105:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun106(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
-; CHECK-LABEL: fun106:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun107(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun107:
+define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i16> %val5, <8 x i16> %val6) {
+; CHECK-LABEL: fun19:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
+; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqf [[REG2:%v[0-9]+]], %v25, %v29
+; CHECK-DAG:     vceqf [[REG3:%v[0-9]+]], %v27, %v31
+; CHECK-DAG:     vo [[REG4:%v[0-9]+]], [[REG1]], [[REG3]]
+; CHECK-DAG:     vo [[REG5:%v[0-9]+]], [[REG0]], [[REG2]]
+; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vpkf [[REG8:%v[0-9]+]], [[REG5]], [[REG4]]
+; CHECK-NEXT:    vsel %v24, [[REG7]], [[REG6]], [[REG8]]
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun108(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i64> %val5, <8 x i64> %val6) {
-; CHECK-LABEL: fun108:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vceqf %v0, %v28, %v25
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v31, %v2, %v0
-; CHECK-NEXT:    vceqf %v0, %v30, %v27
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
+  %cmp0 = icmp eq <8 x i32> %val1, %val2
   %cmp1 = icmp eq <8 x i32> %val3, %val4
   %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i64> %val5, <8 x i64> %val6
-  ret <8 x i64> %sel
-}
-
-define <8 x i8> @fun109(<8 x i16> %val1, <8 x i16> %val2, <8 x i64> %val3, <8 x i64> %val4, <8 x i8> %val5, <8 x i8> %val6) {
-; CHECK-LABEL: fun109:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v30, %v31
-; CHECK-NEXT:    vceqg %v2, %v28, %v29
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vlrepg %v1, 200(%r15)
-; CHECK-NEXT:    vlrepg %v2, 192(%r15)
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i64> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun110(<8 x i16> %val1, <8 x i16> %val2, <8 x float> %val3, <8 x float> %val4, <8 x i16> %val5, <8 x i16> %val6) {
-; CHECK-LABEL: fun110:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <8 x float> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
   %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
   ret <8 x i16> %sel
 }
 
-define <8 x i32> @fun111(<8 x i16> %val1, <8 x i16> %val2, <8 x double> %val3, <8 x double> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun111:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x i32> @fun112(<8 x i32> %val1, <8 x i32> %val2, <8 x i64> %val3, <8 x i64> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun112:
+define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i32> %val5, <8 x i32> %val6) {
+; CHECK-LABEL: fun20:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
+; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqf [[REG2:%v[0-9]+]], %v25, %v29
+; CHECK-DAG:     vceqf [[REG3:%v[0-9]+]], %v27, %v31
+; CHECK-DAG:     vl [[REG4:%v[0-9]+]], 208(%r15)
+; CHECK-DAG:     vl [[REG5:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 192(%r15)
+; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vo [[REG8:%v[0-9]+]], [[REG1]], [[REG3]]
+; CHECK-DAG:     vo [[REG9:%v[0-9]+]], [[REG0]], [[REG2]]
+; CHECK-DAG:     vsel %v24, [[REG7]], [[REG6]], [[REG9]]
+; CHECK-DAG:     vsel %v26, [[REG5]], [[REG4]], [[REG8]]
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = icmp eq <8 x i64> %val3, %val4
+  %cmp1 = icmp eq <8 x i32> %val3, %val4
   %and = or <8 x i1> %cmp0, %cmp1
   %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
   ret <8 x i32> %sel
 }
 
-define <8 x double> @fun113(<8 x i32> %val1, <8 x i32> %val2, <8 x float> %val3, <8 x float> %val4, <8 x double> %val5, <8 x double> %val6) {
-; CHECK-LABEL: fun113:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v29, %v29
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v29, %v29
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v31, %v31
-; CHECK-NEXT:    vmrlf %v2, %v27, %v27
-; CHECK-NEXT:    vmrhf %v3, %v27, %v27
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v31, %v31
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vceqf %v2, %v26, %v30
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <8 x float> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x double> %val5, <8 x double> %val6
-  ret <8 x double> %sel
-}
-
-define <8 x double> @fun114(<8 x i32> %val1, <8 x i32> %val2, <8 x double> %val3, <8 x double> %val4, <8 x double> %val5, <8 x double> %val6) {
-; CHECK-LABEL: fun114:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vfchdb %v0, %v25, %v0
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vceqf %v2, %v26, %v30
-; CHECK-NEXT:    vfchdb %v0, %v29, %v0
-; CHECK-NEXT:    vuphf %v3, %v2
-; CHECK-NEXT:    vo %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x double> %val5, <8 x double> %val6
-  ret <8 x double> %sel
-}
-
-define <8 x i64> @fun115(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x i64> %val5, <8 x i64> %val6) {
-; CHECK-LABEL: fun115:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 224(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vo %v1, %v1, %v2
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vfchdb %v3, %v29, %v3
-; CHECK-NEXT:    vo %v2, %v2, %v3
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v27, %v2
-; CHECK-NEXT:    vo %v0, %v0, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vfchdb %v1, %v31, %v1
-; CHECK-NEXT:    vo %v0, %v0, %v1
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <8 x float> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = or <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i64> %val5, <8 x i64> %val6
-  ret <8 x i64> %sel
-}
-
-define <16 x i8> @fun116(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun116:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i8> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun117(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun117:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i8> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i64> @fun118(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun118:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vceqh %v0, %v28, %v25
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vuphh %v2, %v0
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v24, %v29, %v3, %v2
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v26, %v31, %v3, %v2
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v3, 288(%r15)
-; CHECK-NEXT:    vl %v4, 160(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v0, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vceqh %v2, %v30, %v27
-; CHECK-NEXT:    vlr %v30, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vo %v1, %v1, %v2
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v25, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v3, 336(%r15)
-; CHECK-NEXT:    vl %v4, 208(%r15)
-; CHECK-NEXT:    vpkg %v2, %v1, %v1
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v27, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vmrlg %v2, %v1, %v1
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v1, %v1, %v1, 12
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v29, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i64> @fun119(<16 x i8> %val1, <16 x i8> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun119:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vceqf %v0, %v28, %v29
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vl %v3, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vpkg %v2, %v1, %v1
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vl %v5, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vmrlg %v3, %v1, %v1
-; CHECK-NEXT:    vuphb %v3, %v3
-; CHECK-NEXT:    vceqf %v2, %v25, %v2
-; CHECK-NEXT:    vuphh %v3, %v3
-; CHECK-NEXT:    vo %v2, %v3, %v2
-; CHECK-NEXT:    vuphf %v3, %v2
-; CHECK-NEXT:    vsldb %v1, %v1, %v1, 12
-; CHECK-NEXT:    vsel %v25, %v5, %v4, %v3
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vl %v4, 416(%r15)
-; CHECK-NEXT:    vl %v5, 288(%r15)
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vceqf %v3, %v27, %v3
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v1, %v1, %v3
-; CHECK-NEXT:    vuphf %v3, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v5, %v4, %v3
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vl %v4, 240(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i32> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i64> @fun120(<16 x i8> %val1, <16 x i8> %val2, <16 x i64> %val3, <16 x i64> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun120:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vceqg %v1, %v28, %v0
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 448(%r15)
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vpkf %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v30, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 464(%r15)
-; CHECK-NEXT:    vl %v3, 336(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v1
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 480(%r15)
-; CHECK-NEXT:    vsel %v28, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 6
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v27, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 496(%r15)
-; CHECK-NEXT:    vsel %v30, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v3, 384(%r15)
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 512(%r15)
-; CHECK-NEXT:    vsel %v25, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v3, 400(%r15)
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 10
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v31, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 528(%r15)
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 288(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vl %v3, 416(%r15)
-; CHECK-NEXT:    vceqg %v1, %v2, %v1
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 12
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 14
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 544(%r15)
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 432(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vo %v0, %v0, %v1
-; CHECK-NEXT:    vl %v1, 560(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i64> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i16> @fun121(<16 x i8> %val1, <16 x i8> %val2, <16 x float> %val3, <16 x float> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun121:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vmrlf %v4, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v29, %v29
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vmrlf %v2, %v0, %v0
-; CHECK-NEXT:    vmrlf %v3, %v27, %v27
-; CHECK-NEXT:    vmrhf %v0, %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vmrhf %v3, %v27, %v27
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v0, %v3, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v2
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vpkf %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <16 x float> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i8> @fun122(<16 x i8> %val1, <16 x i8> %val2, <16 x double> %val3, <16 x double> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun122:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 288(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v31, %v1
-; CHECK-NEXT:    vfchdb %v2, %v29, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v27, %v1
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v30, %v2
-; CHECK-NEXT:    vfchdb %v3, %v28, %v3
-; CHECK-NEXT:    vpkg %v2, %v3, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <16 x double> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i8> @fun123(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun123:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v27, %v31
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v25, %v29
-; CHECK-NEXT:    vceqh %v2, %v24, %v28
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun124(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun124:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v25, %v29
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqh %v0, %v27, %v31
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun125(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun125:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v25, %v29
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v27, %v31
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <16 x i8> @fun126(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun126:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqf %v0, %v31, %v0
-; CHECK-NEXT:    vceqf %v1, %v29, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqf %v1, %v27, %v1
-; CHECK-NEXT:    vceqf %v2, %v25, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vceqh %v2, %v24, %v28
-; CHECK-NEXT:    vo %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i32> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i32> @fun127(<16 x i16> %val1, <16 x i16> %val2, <16 x i64> %val3, <16 x i64> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun127:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 416(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqg %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vceqg %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vuphh %v3, %v2
-; CHECK-NEXT:    vo %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 448(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v3, %v29, %v3
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v3, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 336(%r15)
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vceqg %v1, %v3, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i64> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <16 x double> @fun128(<16 x i16> %val1, <16 x i16> %val2, <16 x float> %val3, <16 x float> %val4, <16 x double> %val5, <16 x double> %val6) {
-; CHECK-LABEL: fun128:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vmrlf %v1, %v0, %v0
-; CHECK-NEXT:    vmrlf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v0, %v0, %v0
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vl %v5, 416(%r15)
-; CHECK-NEXT:    vl %v6, 288(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vsel %v24, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrlf %v4, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v27, %v27
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vl %v3, 384(%r15)
-; CHECK-NEXT:    vo %v1, %v1, %v2
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrlf %v4, %v29, %v29
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vceqh %v3, %v26, %v30
-; CHECK-NEXT:    vuphh %v4, %v3
-; CHECK-NEXT:    vo %v2, %v4, %v2
-; CHECK-NEXT:    vuphf %v4, %v2
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vl %v4, 208(%r15)
-; CHECK-NEXT:    vmrlf %v5, %v4, %v4
-; CHECK-NEXT:    vmrlf %v6, %v31, %v31
-; CHECK-NEXT:    vmrhf %v4, %v4, %v4
-; CHECK-NEXT:    vmrlg %v3, %v3, %v3
-; CHECK-NEXT:    vuphh %v3, %v3
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v5, %v6, %v5
-; CHECK-NEXT:    vmrhf %v6, %v31, %v31
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v4, %v6, %v4
-; CHECK-NEXT:    vl %v6, 320(%r15)
-; CHECK-NEXT:    vpkg %v4, %v4, %v5
-; CHECK-NEXT:    vl %v5, 448(%r15)
-; CHECK-NEXT:    vo %v3, %v3, %v4
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v29, %v6, %v5, %v4
-; CHECK-NEXT:    vl %v4, 368(%r15)
-; CHECK-NEXT:    vl %v5, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v5, %v4, %v0
-; CHECK-NEXT:    vl %v4, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v4, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v2, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v3, %v3
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <16 x float> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x double> %val5, <16 x double> %val6
-  ret <16 x double> %sel
-}
-
-define <16 x i32> @fun129(<16 x i16> %val1, <16 x i16> %val2, <16 x double> %val3, <16 x double> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun129:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vo %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 416(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vuphh %v3, %v2
-; CHECK-NEXT:    vo %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 448(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v3, %v29, %v3
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v3, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 336(%r15)
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v3, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vo %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <16 x double> %val3, %val4
-  %and = or <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <2 x i8> @fun130(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun130:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i8> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i16> @fun131(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun131:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i8> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i8> @fun132(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun132:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v1, %v28, %v30
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vpkh %v1, %v1, %v1
-; CHECK-NEXT:    vx %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i32> @fun133(<2 x i8> %val1, <2 x i8> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun133:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i32> @fun134(<2 x i8> %val1, <2 x i8> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun134:
+define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
+; CHECK-LABEL: fun21:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vuphb %v1, %v1
+; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
 ; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i16> @fun135(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun135:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i64> @fun136(<2 x i8> %val1, <2 x i8> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun136:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i8> @fun137(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun137:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i16> @fun138(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun138:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun139(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun139:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i16> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <2 x i8> @fun140(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun140:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v28, %v30
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vpkf %v1, %v1, %v1
-; CHECK-NEXT:    vx %v0, %v0, %v1
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x i8> @fun141(<2 x i16> %val1, <2 x i16> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i8> %val5, <2 x i8> %val6) {
-; CHECK-LABEL: fun141:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI141_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
+  %cmp0 = icmp eq <2 x i64> %val1, %val2
   %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
-  ret <2 x i8> %sel
-}
-
-define <2 x double> @fun142(<2 x i16> %val1, <2 x i16> %val2, <2 x float> %val3, <2 x float> %val4, <2 x double> %val5, <2 x double> %val6) {
-; CHECK-LABEL: fun142:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
-  ret <2 x double> %sel
-}
-
-define <2 x i16> @fun143(<2 x i16> %val1, <2 x i16> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun143:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI143_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i16> @fun144(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun144:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun145(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun145:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
+  %and = and <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
   ret <2 x i32> %sel
 }
 
-define <2 x i64> @fun146(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun146:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i32> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i64> @fun147(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun147:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
-}
-
-define <2 x i16> @fun148(<2 x i32> %val1, <2 x i32> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun148:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x float> @fun149(<2 x i32> %val1, <2 x i32> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
-; CHECK-LABEL: fun149:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v1, %v28, %v30
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vpkg %v1, %v1, %v1
-; CHECK-NEXT:    vx %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
-  ret <2 x float> %sel
-}
-
-define <2 x i16> @fun150(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun150:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI150_0
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
-}
-
-define <2 x i64> @fun151(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun151:
+define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
+; CHECK-LABEL: fun22:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
+; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp0 = icmp eq <2 x i64> %val1, %val2
   %cmp1 = icmp eq <2 x i64> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
+  %and = and <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
   ret <2 x i64> %sel
 }
 
-define <2 x i64> @fun152(<2 x i64> %val1, <2 x i64> %val2, <2 x float> %val3, <2 x float> %val4, <2 x i64> %val5, <2 x i64> %val6) {
-; CHECK-LABEL: fun152:
+define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
+; CHECK-LABEL: fun23:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
+; CHECK-NEXT:    vceqg %v0, %v26, %v30
+; CHECK-NEXT:    vceqg %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-NEXT:    vceqf %v1, %v25, %v27
+; CHECK-NEXT:    vx %v0, %v0, %v1
+; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
-  ret <2 x i64> %sel
+  %cmp0 = icmp eq <4 x i64> %val1, %val2
+  %cmp1 = icmp eq <4 x i32> %val3, %val4
+  %and = xor <4 x i1> %cmp0, %cmp1
+  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
+  ret <4 x i32> %sel
 }
 
-define <2 x i16> @fun153(<2 x i64> %val1, <2 x i64> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i16> %val5, <2 x i16> %val6) {
-; CHECK-LABEL: fun153:
+define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
+; CHECK-LABEL: fun24:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v28, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI153_0
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-NEXT:    vceqf [[REG0:%v[0-9]+]], %v25, %v27
+; CHECK-NEXT:    vuphf [[REG1:%v[0-9]+]], [[REG0]]
+; CHECK-NEXT:    vmrlg [[REG2:%v[0-9]+]], [[REG0]], [[REG0]]
+; CHECK-NEXT:    vceqg [[REG3:%v[0-9]+]], %v24, %v28
+; CHECK-NEXT:    vceqg [[REG4:%v[0-9]+]], %v26, %v30
+; CHECK-NEXT:    vuphf [[REG5:%v[0-9]+]], [[REG2]]
+; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vx [[REG8:%v[0-9]+]], [[REG4]], [[REG5]]
+; CHECK-DAG:     vx [[REG9:%v[0-9]+]], [[REG3]], [[REG1]]
+; CHECK-DAG:     vsel %v24, %v29, [[REG7]], [[REG9]]
+; CHECK-DAG:     vsel %v26, %v31, [[REG6]], [[REG8]]
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <2 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
-  ret <2 x i16> %sel
+  %cmp0 = icmp eq <4 x i64> %val1, %val2
+  %cmp1 = icmp eq <4 x i32> %val3, %val4
+  %and = xor <4 x i1> %cmp0, %cmp1
+  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
+  ret <4 x i64> %sel
 }
 
-define <2 x float> @fun154(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4, <2 x float> %val5, <2 x float> %val6) {
-; CHECK-LABEL: fun154:
+define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
+; CHECK-LABEL: fun25:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
+; CHECK-NEXT:    vmrlf %v0, %v26, %v26
+; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
+; CHECK-NEXT:    vmrhf %v1, %v26, %v26
+; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
+; CHECK-NEXT:    vfchdb %v1, %v28, %v30
+; CHECK-NEXT:    vpkg %v1, %v1, %v1
+; CHECK-NEXT:    vo %v0, %v0, %v1
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
+;
+; CHECK-Z14-LABEL: fun25:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchdb %v1, %v28, %v30
+; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vpkg %v1, %v1, %v1
+; CHECK-Z14-NEXT:    vo %v0, %v0, %v1
+; CHECK-Z14-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-Z14-NEXT:    br %r14
   %cmp0 = fcmp ogt <2 x float> %val1, %val2
-  %cmp1 = fcmp ogt <2 x float> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
+  %cmp1 = fcmp ogt <2 x double> %val3, %val4
+  %and = or <2 x i1> %cmp0, %cmp1
   %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
   ret <2 x float> %sel
 }
 
-define <2 x i32> @fun155(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x i32> %val5, <2 x i32> %val6) {
-; CHECK-LABEL: fun155:
+define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
+; CHECK-LABEL: fun26:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
 ; CHECK-NEXT:    vmrhf %v1, %v26, %v26
 ; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
+; CHECK-NEXT:    vuphf %v0, %v0
 ; CHECK-NEXT:    vfchdb %v1, %v28, %v30
-; CHECK-NEXT:    vpkg %v1, %v1, %v1
-; CHECK-NEXT:    vx %v0, %v0, %v1
+; CHECK-NEXT:    vo %v0, %v0, %v1
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
+;
+; CHECK-Z14-LABEL: fun26:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vuphf %v0, %v0
+; CHECK-Z14-NEXT:    vfchdb %v1, %v28, %v30
+; CHECK-Z14-NEXT:    vo %v0, %v0, %v1
+; CHECK-Z14-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-Z14-NEXT:    br %r14
   %cmp0 = fcmp ogt <2 x float> %val1, %val2
   %cmp1 = fcmp ogt <2 x double> %val3, %val4
-  %and = xor <2 x i1> %cmp0, %cmp1
-  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
-  ret <2 x i32> %sel
-}
-
-define <4 x i16> @fun156(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun156:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x i32> @fun157(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun157:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun158(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun158:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v28, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i32> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x i32> @fun159(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun159:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v30, %v27
-; CHECK-NEXT:    vceqg %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i16> @fun160(<4 x i32> %val1, <4 x i32> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun160:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
-}
-
-define <4 x i8> @fun161(<4 x i32> %val1, <4 x i32> %val2, <4 x double> %val3, <4 x double> %val4, <4 x i8> %val5, <4 x i8> %val6) {
-; CHECK-LABEL: fun161:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v27
-; CHECK-NEXT:    vfchdb %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v26
-; CHECK-NEXT:    larl %r1, .LCPI161_0
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i8> %val5, <4 x i8> %val6
-  ret <4 x i8> %sel
-}
-
-define <4 x i32> @fun162(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i32> %val5, <4 x i32> %val6) {
-; CHECK-LABEL: fun162:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v29
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun163(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun163:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v25, %v29
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqg %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = icmp eq <4 x i64> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x i64> @fun164(<4 x i64> %val1, <4 x i64> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i64> %val5, <4 x i64> %val6) {
-; CHECK-LABEL: fun164:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v2, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
-  ret <4 x i64> %sel
-}
-
-define <4 x float> @fun165(<4 x i64> %val1, <4 x i64> %val2, <4 x double> %val3, <4 x double> %val4, <4 x float> %val5, <4 x float> %val6) {
-; CHECK-LABEL: fun165:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v27, %v31
-; CHECK-NEXT:    vceqg %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v29
-; CHECK-NEXT:    vceqg %v2, %v24, %v28
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <4 x i64> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
-  ret <4 x float> %sel
+  %and = or <2 x i1> %cmp0, %cmp1
+  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
+  ret <2 x double> %sel
 }
 
-define <4 x i16> @fun166(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x i16> %val5, <4 x i16> %val6) {
-; CHECK-LABEL: fun166:
+; Also check a widening select of a vector of floats
+define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x float> %val5, <2 x float> %val6) {
+; CHECK-LABEL: fun27:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
+; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vo %v0, [[REG0]], [[REG1]]
+; CHECK-NEXT:    vuphb %v0, %v0
+; CHECK-NEXT:    vuphh %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x float> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
-  ret <4 x i16> %sel
+  %cmp0 = icmp eq <2 x i8> %val1, %val2
+  %cmp1 = icmp eq <2 x i8> %val3, %val4
+  %and = or <2 x i1> %cmp0, %cmp1
+  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
+  ret <2 x float> %sel
 }
 
-define <4 x float> @fun167(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
-; CHECK-LABEL: fun167:
+define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
+; CHECK-LABEL: fun28:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
+; CHECK-DAG:     vmrlf [[REG0:%v[0-9]+]], %v26, %v26
+; CHECK-DAG:     vmrlf [[REG1:%v[0-9]+]], %v24, %v24
+; CHECK-DAG:     vldeb [[REG2:%v[0-9]+]], [[REG0]]
+; CHECK-DAG:     vldeb [[REG3:%v[0-9]+]], [[REG1]]
+; CHECK-DAG:     vfchdb [[REG4:%v[0-9]+]], [[REG3]], [[REG2]]
+; CHECK-DAG:     vmrhf [[REG5:%v[0-9]+]], %v26, %v26
+; CHECK-DAG:     vmrhf [[REG6:%v[0-9]+]], %v24, %v24
+; CHECK-DAG:     vldeb [[REG7:%v[0-9]+]], [[REG5]]
+; CHECK-DAG:     vmrhf [[REG8:%v[0-9]+]], %v28, %v28
+; CHECK-DAG:     vldeb [[REG9:%v[0-9]+]], [[REG6]]
+; CHECK-DAG:     vfchdb [[REG10:%v[0-9]+]], [[REG9]], [[REG7]]
+; CHECK-DAG:     vpkg [[REG11:%v[0-9]+]], [[REG10]], [[REG4]]
+; CHECK-DAG:     vmrlf [[REG12:%v[0-9]+]], %v30, %v30
+; CHECK-DAG:     vmrlf [[REG13:%v[0-9]+]], %v28, %v28
+; CHECK-DAG:     vldeb [[REG14:%v[0-9]+]], [[REG12]]
+; CHECK-DAG:     vldeb [[REG15:%v[0-9]+]], [[REG13]]
+; CHECK-DAG:     vfchdb [[REG16:%v[0-9]+]], [[REG15]], [[REG14]]
+; CHECK-DAG:     vmrhf [[REG17:%v[0-9]+]], %v30, %v30
+; CHECK-DAG:     vldeb [[REG19:%v[0-9]+]], [[REG17]]
+; CHECK-DAG:     vldeb [[REG20:%v[0-9]+]], [[REG8]]
+; CHECK-NEXT:    vfchdb %v2, [[REG20]], [[REG19]]
+; CHECK-NEXT:    vpkg [[REG21:%v[0-9]+]], %v2, [[REG16]]
+; CHECK-NEXT:    vx %v0, [[REG11]], [[REG21]]
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
+;
+; CHECK-Z14-LABEL: fun28:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vfchsb %v1, %v28, %v30
+; CHECK-Z14-NEXT:    vx %v0, %v0, %v1
+; CHECK-Z14-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-Z14-NEXT:    br %r14
   %cmp0 = fcmp ogt <4 x float> %val1, %val2
   %cmp1 = fcmp ogt <4 x float> %val3, %val4
   %and = xor <4 x i1> %cmp0, %cmp1
   %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
   ret <4 x float> %sel
 }
 
-define <4 x double> @fun168(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
-; CHECK-LABEL: fun168:
+define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
+; CHECK-LABEL: fun29:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
+; CHECK-NEXT:    vmrlf %v0, %v26, %v26
+; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
+; CHECK-NEXT:    vmrhf %v1, %v26, %v26
+; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
+; CHECK-NEXT:    vmrhf %v3, %v28, %v28
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
+; CHECK-NEXT:    vmrlf %v1, %v30, %v30
+; CHECK-NEXT:    vmrlf %v2, %v28, %v28
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
+; CHECK-NEXT:    vmrhf %v2, %v30, %v30
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vldeb %v3, %v3
 ; CHECK-NEXT:    vfchdb %v2, %v3, %v2
 ; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
+; CHECK-NEXT:    vx %v0, %v0, %v1
+; CHECK-NEXT:    vmrlg %v1, %v0, %v0
+; CHECK-NEXT:    vuphf %v1, %v1
 ; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
+; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
+; CHECK-NEXT:    vsel %v26, %v27, %v31, %v1
 ; CHECK-NEXT:    br %r14
+;
+; CHECK-Z14-LABEL: fun29:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vfchsb %v1, %v28, %v30
+; CHECK-Z14-NEXT:    vx %v0, %v0, %v1
+; CHECK-Z14-NEXT:    vmrlg %v1, %v0, %v0
+; CHECK-Z14-NEXT:    vuphf %v1, %v1
+; CHECK-Z14-NEXT:    vuphf %v0, %v0
+; CHECK-Z14-NEXT:    vsel %v24, %v25, %v29, %v0
+; CHECK-Z14-NEXT:    vsel %v26, %v27, %v31, %v1
+; CHECK-Z14-NEXT:    br %r14
   %cmp0 = fcmp ogt <4 x float> %val1, %val2
   %cmp1 = fcmp ogt <4 x float> %val3, %val4
   %and = xor <4 x i1> %cmp0, %cmp1
   %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6
   ret <4 x double> %sel
 }
 
-define <4 x i8> @fun169(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4, <4 x i8> %val5, <4 x i8> %val6) {
-; CHECK-LABEL: fun169:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v27
-; CHECK-NEXT:    vfchdb %v1, %v28, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    larl %r1, .LCPI169_0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = fcmp ogt <4 x float> %val1, %val2
-  %cmp1 = fcmp ogt <4 x double> %val3, %val4
-  %and = xor <4 x i1> %cmp0, %cmp1
-  %sel = select <4 x i1> %and, <4 x i8> %val5, <4 x i8> %val6
-  ret <4 x i8> %sel
-}
-
-define <8 x i8> @fun170(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
-; CHECK-LABEL: fun170:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun171(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
-; CHECK-LABEL: fun171:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun172(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun172:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v28, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i16> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun173(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i64> %val5, <8 x i64> %val6) {
-; CHECK-LABEL: fun173:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vceqf %v0, %v28, %v25
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v31, %v2, %v0
-; CHECK-NEXT:    vceqf %v0, %v30, %v27
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i32> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i64> %val5, <8 x i64> %val6
-  ret <8 x i64> %sel
-}
-
-define <8 x i8> @fun174(<8 x i16> %val1, <8 x i16> %val2, <8 x i64> %val3, <8 x i64> %val4, <8 x i8> %val5, <8 x i8> %val6) {
-; CHECK-LABEL: fun174:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v30, %v31
-; CHECK-NEXT:    vceqg %v2, %v28, %v29
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vlrepg %v1, 200(%r15)
-; CHECK-NEXT:    vlrepg %v2, 192(%r15)
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = icmp eq <8 x i64> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun175(<8 x i16> %val1, <8 x i16> %val2, <8 x float> %val3, <8 x float> %val4, <8 x i16> %val5, <8 x i16> %val6) {
-; CHECK-LABEL: fun175:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <8 x float> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun176(<8 x i16> %val1, <8 x i16> %val2, <8 x double> %val3, <8 x double> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun176:
+define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x float> %val5, <8 x float> %val6) {
+; CHECK-LABEL: fun30:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v26
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
+; CHECK-NEXT:    vmrlf %v16, %v28, %v28
+; CHECK-NEXT:    vmrlf %v17, %v24, %v24
+; CHECK-NEXT:    vldeb %v16, %v16
+; CHECK-NEXT:    vldeb %v17, %v17
+; CHECK-NEXT:    vfchdb %v16, %v17, %v16
+; CHECK-NEXT:    vmrhf %v17, %v28, %v28
+; CHECK-NEXT:    vmrhf %v18, %v24, %v24
+; CHECK-NEXT:    vldeb %v17, %v17
+; CHECK-NEXT:    vl %v4, 192(%r15)
+; CHECK-NEXT:    vldeb %v18, %v18
+; CHECK-NEXT:    vl %v5, 208(%r15)
+; CHECK-NEXT:    vl %v6, 160(%r15)
+; CHECK-NEXT:    vl %v7, 176(%r15)
+; CHECK-NEXT:    vl %v0, 272(%r15)
 ; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x i32> @fun177(<8 x i32> %val1, <8 x i32> %val2, <8 x i64> %val3, <8 x i64> %val4, <8 x i32> %val5, <8 x i32> %val6) {
-; CHECK-LABEL: fun177:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = icmp eq <8 x i64> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
-  ret <8 x i32> %sel
-}
-
-define <8 x double> @fun178(<8 x i32> %val1, <8 x i32> %val2, <8 x float> %val3, <8 x float> %val4, <8 x double> %val5, <8 x double> %val6) {
-; CHECK-LABEL: fun178:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v29, %v29
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v29, %v29
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v31, %v31
-; CHECK-NEXT:    vmrlf %v2, %v27, %v27
-; CHECK-NEXT:    vmrhf %v3, %v27, %v27
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v31, %v31
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vceqf %v2, %v26, %v30
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <8 x float> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x double> %val5, <8 x double> %val6
-  ret <8 x double> %sel
-}
-
-define <8 x double> @fun179(<8 x i32> %val1, <8 x i32> %val2, <8 x double> %val3, <8 x double> %val4, <8 x double> %val5, <8 x double> %val6) {
-; CHECK-LABEL: fun179:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vfchdb %v0, %v25, %v0
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vceqf %v2, %v26, %v30
-; CHECK-NEXT:    vfchdb %v0, %v29, %v0
-; CHECK-NEXT:    vuphf %v3, %v2
-; CHECK-NEXT:    vx %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <8 x i32> %val1, %val2
-  %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x double> %val5, <8 x double> %val6
-  ret <8 x double> %sel
-}
-
-define <8 x i64> @fun180(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x i64> %val5, <8 x i64> %val6) {
-; CHECK-LABEL: fun180:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
+; CHECK-NEXT:    vfchdb %v17, %v18, %v17
+; CHECK-NEXT:    vl %v2, 256(%r15)
 ; CHECK-NEXT:    vl %v3, 224(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vx %v1, %v1, %v2
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vfchdb %v3, %v29, %v3
-; CHECK-NEXT:    vx %v2, %v2, %v3
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v27, %v2
-; CHECK-NEXT:    vx %v0, %v0, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vfchdb %v1, %v31, %v1
-; CHECK-NEXT:    vx %v0, %v0, %v1
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
+; CHECK-NEXT:    vpkg %v16, %v17, %v16
+; CHECK-NEXT:    vmrlf %v17, %v30, %v30
+; CHECK-NEXT:    vmrlf %v18, %v26, %v26
+; CHECK-NEXT:    vmrhf %v19, %v26, %v26
+; CHECK-NEXT:    vfchdb %v7, %v27, %v7
+; CHECK-NEXT:    vfchdb %v6, %v25, %v6
+; CHECK-NEXT:    vfchdb %v5, %v31, %v5
+; CHECK-NEXT:    vfchdb %v4, %v29, %v4
+; CHECK-NEXT:    vpkg %v6, %v6, %v7
+; CHECK-NEXT:    vpkg %v4, %v4, %v5
+; CHECK-NEXT:    vn %v5, %v16, %v6
+; CHECK-NEXT:    vsel %v24, %v3, %v2, %v5
+; CHECK-NEXT:    vldeb %v17, %v17
+; CHECK-NEXT:    vldeb %v18, %v18
+; CHECK-NEXT:    vfchdb %v17, %v18, %v17
+; CHECK-NEXT:    vmrhf %v18, %v30, %v30
+; CHECK-NEXT:    vldeb %v18, %v18
+; CHECK-NEXT:    vldeb %v19, %v19
+; CHECK-NEXT:    vfchdb %v18, %v19, %v18
+; CHECK-NEXT:    vpkg %v17, %v18, %v17
+; CHECK-NEXT:    vn %v4, %v17, %v4
+; CHECK-NEXT:    vsel %v26, %v1, %v0, %v4
 ; CHECK-NEXT:    br %r14
+;
+; CHECK-Z14-LABEL: fun30:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vl %v4, 192(%r15)
+; CHECK-Z14-NEXT:    vl %v5, 208(%r15)
+; CHECK-Z14-NEXT:    vl %v6, 160(%r15)
+; CHECK-Z14-NEXT:    vl %v7, 176(%r15)
+; CHECK-Z14-NEXT:    vfchdb %v7, %v27, %v7
+; CHECK-Z14-NEXT:    vfchdb %v6, %v25, %v6
+; CHECK-Z14-NEXT:    vfchdb %v5, %v31, %v5
+; CHECK-Z14-NEXT:    vfchdb %v4, %v29, %v4
+; CHECK-Z14-NEXT:    vfchsb %v16, %v24, %v28
+; CHECK-Z14-NEXT:    vfchsb %v17, %v26, %v30
+; CHECK-Z14-NEXT:    vpkg %v6, %v6, %v7
+; CHECK-Z14-NEXT:    vpkg %v4, %v4, %v5
+; CHECK-Z14-NEXT:    vl %v0, 272(%r15)
+; CHECK-Z14-NEXT:    vl %v1, 240(%r15)
+; CHECK-Z14-NEXT:    vl %v2, 256(%r15)
+; CHECK-Z14-NEXT:    vl %v3, 224(%r15)
+; CHECK-Z14-NEXT:    vn %v4, %v17, %v4
+; CHECK-Z14-NEXT:    vn %v5, %v16, %v6
+; CHECK-Z14-NEXT:    vsel %v24, %v3, %v2, %v5
+; CHECK-Z14-NEXT:    vsel %v26, %v1, %v0, %v4
+; CHECK-Z14-NEXT:    br %r14
   %cmp0 = fcmp ogt <8 x float> %val1, %val2
   %cmp1 = fcmp ogt <8 x double> %val3, %val4
-  %and = xor <8 x i1> %cmp0, %cmp1
-  %sel = select <8 x i1> %and, <8 x i64> %val5, <8 x i64> %val6
-  ret <8 x i64> %sel
+  %and = and <8 x i1> %cmp0, %cmp1
+  %sel = select <8 x i1> %and, <8 x float> %val5, <8 x float> %val6
+  ret <8 x float> %sel
 }
 
-define <16 x i8> @fun181(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun181:
+define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
+; CHECK-LABEL: fun31:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
+; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
+; CHECK-NEXT:    vpkg %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i8> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun182(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun182:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v28, %v30
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v1
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i8> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i64> @fun183(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun183:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vceqh %v0, %v28, %v25
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vuphh %v2, %v0
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v24, %v29, %v3, %v2
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v26, %v31, %v3, %v2
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v3, 288(%r15)
-; CHECK-NEXT:    vl %v4, 160(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v0, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vceqh %v2, %v30, %v27
-; CHECK-NEXT:    vlr %v30, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vx %v1, %v1, %v2
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v25, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v3, 336(%r15)
-; CHECK-NEXT:    vl %v4, 208(%r15)
-; CHECK-NEXT:    vpkg %v2, %v1, %v1
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v27, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vmrlg %v2, %v1, %v1
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v1, %v1, %v1, 12
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v29, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
-}
-
-define <16 x i64> @fun184(<16 x i8> %val1, <16 x i8> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun184:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vceqf %v0, %v28, %v29
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vl %v3, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vpkg %v2, %v1, %v1
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vl %v5, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vmrlg %v3, %v1, %v1
-; CHECK-NEXT:    vuphb %v3, %v3
-; CHECK-NEXT:    vceqf %v2, %v25, %v2
-; CHECK-NEXT:    vuphh %v3, %v3
-; CHECK-NEXT:    vx %v2, %v3, %v2
-; CHECK-NEXT:    vuphf %v3, %v2
-; CHECK-NEXT:    vsldb %v1, %v1, %v1, 12
-; CHECK-NEXT:    vsel %v25, %v5, %v4, %v3
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vl %v4, 416(%r15)
-; CHECK-NEXT:    vl %v5, 288(%r15)
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vceqf %v3, %v27, %v3
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v1, %v1, %v3
-; CHECK-NEXT:    vuphf %v3, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v5, %v4, %v3
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vl %v4, 240(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i32> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
+  %cmp0 = fcmp ogt <2 x double> %val1, %val2
+  %cmp1 = fcmp ogt <2 x double> %val3, %val4
+  %and = xor <2 x i1> %cmp0, %cmp1
+  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
+  ret <2 x float> %sel
 }
 
-define <16 x i64> @fun185(<16 x i8> %val1, <16 x i8> %val2, <16 x i64> %val3, <16 x i64> %val4, <16 x i64> %val5, <16 x i64> %val6) {
-; CHECK-LABEL: fun185:
+define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
+; CHECK-LABEL: fun32:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vceqg %v1, %v28, %v0
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 448(%r15)
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vpkf %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v30, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 464(%r15)
-; CHECK-NEXT:    vl %v3, 336(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v1
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 480(%r15)
-; CHECK-NEXT:    vsel %v28, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 6
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v27, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 496(%r15)
-; CHECK-NEXT:    vsel %v30, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v3, 384(%r15)
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 512(%r15)
-; CHECK-NEXT:    vsel %v25, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v3, 400(%r15)
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 10
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vceqg %v1, %v31, %v1
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 528(%r15)
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 288(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vl %v3, 416(%r15)
-; CHECK-NEXT:    vceqg %v1, %v2, %v1
-; CHECK-NEXT:    vsldb %v2, %v0, %v0, 12
-; CHECK-NEXT:    vuphb %v2, %v2
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 14
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 544(%r15)
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vceqg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 432(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vx %v0, %v0, %v1
-; CHECK-NEXT:    vl %v1, 560(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
+; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v24, %v26
+; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
+; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = icmp eq <16 x i64> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i64> %val5, <16 x i64> %val6
-  ret <16 x i64> %sel
+  %cmp0 = fcmp ogt <2 x double> %val1, %val2
+  %cmp1 = fcmp ogt <2 x double> %val3, %val4
+  %and = xor <2 x i1> %cmp0, %cmp1
+  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
+  ret <2 x double> %sel
 }
 
-define <16 x i16> @fun186(<16 x i8> %val1, <16 x i8> %val2, <16 x float> %val3, <16 x float> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun186:
+define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
+; CHECK-LABEL: fun33:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vmrlf %v4, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
+; CHECK-NEXT:    vfchdb %v0, %v26, %v30
+; CHECK-NEXT:    vfchdb %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v29, %v29
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
+; CHECK-NEXT:    vmrlf %v1, %v27, %v27
+; CHECK-NEXT:    vmrlf %v2, %v25, %v25
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v29, %v29
+; CHECK-NEXT:    vmrhf %v2, %v27, %v27
+; CHECK-NEXT:    vmrhf %v3, %v25, %v25
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vldeb %v3, %v3
 ; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
 ; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vuphb %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vmrlf %v2, %v0, %v0
-; CHECK-NEXT:    vmrlf %v3, %v27, %v27
-; CHECK-NEXT:    vmrhf %v0, %v0, %v0
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vmrhf %v3, %v27, %v27
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v0, %v3, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v2
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vpkf %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <16 x float> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i8> @fun187(<16 x i8> %val1, <16 x i8> %val2, <16 x double> %val3, <16 x double> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun187:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 288(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v31, %v1
-; CHECK-NEXT:    vfchdb %v2, %v29, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v27, %v1
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v30, %v2
-; CHECK-NEXT:    vfchdb %v3, %v28, %v3
-; CHECK-NEXT:    vpkg %v2, %v3, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vceqb %v1, %v24, %v26
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i8> %val1, %val2
-  %cmp1 = fcmp ogt <16 x double> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i8> @fun188(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun188:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v27, %v31
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v25, %v29
-; CHECK-NEXT:    vceqh %v2, %v24, %v28
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun189(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
-; CHECK-LABEL: fun189:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v25, %v29
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqh %v0, %v27, %v31
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun190(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun190:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v25, %v29
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v27, %v31
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v3, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i16> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <16 x i8> @fun191(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
-; CHECK-LABEL: fun191:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqf %v0, %v31, %v0
-; CHECK-NEXT:    vceqf %v1, %v29, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqf %v1, %v27, %v1
-; CHECK-NEXT:    vceqf %v2, %v25, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vceqh %v2, %v24, %v28
-; CHECK-NEXT:    vx %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i32> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
-  ret <16 x i8> %sel
-}
-
-define <16 x i32> @fun192(<16 x i16> %val1, <16 x i16> %val2, <16 x i64> %val3, <16 x i64> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun192:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 416(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqg %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vceqg %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vuphh %v3, %v2
-; CHECK-NEXT:    vx %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 448(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v3, %v29, %v3
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v3, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 336(%r15)
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vceqg %v1, %v3, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = icmp eq <16 x i64> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
-}
-
-define <16 x double> @fun193(<16 x i16> %val1, <16 x i16> %val2, <16 x float> %val3, <16 x float> %val4, <16 x double> %val5, <16 x double> %val6) {
-; CHECK-LABEL: fun193:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vmrlf %v1, %v0, %v0
-; CHECK-NEXT:    vmrlf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v0, %v0, %v0
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vl %v4, 224(%r15)
-; CHECK-NEXT:    vl %v5, 416(%r15)
-; CHECK-NEXT:    vl %v6, 288(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v1
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vuphf %v2, %v0
-; CHECK-NEXT:    vsel %v24, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrlf %v4, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v27, %v27
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vl %v4, 256(%r15)
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vl %v3, 384(%r15)
-; CHECK-NEXT:    vx %v1, %v1, %v2
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v2
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vmrlf %v3, %v2, %v2
-; CHECK-NEXT:    vmrlf %v4, %v29, %v29
-; CHECK-NEXT:    vmrhf %v2, %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v2, %v4, %v2
-; CHECK-NEXT:    vpkg %v2, %v2, %v3
-; CHECK-NEXT:    vceqh %v3, %v26, %v30
-; CHECK-NEXT:    vuphh %v4, %v3
-; CHECK-NEXT:    vx %v2, %v4, %v2
-; CHECK-NEXT:    vuphf %v4, %v2
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vl %v4, 208(%r15)
-; CHECK-NEXT:    vmrlf %v5, %v4, %v4
-; CHECK-NEXT:    vmrlf %v6, %v31, %v31
-; CHECK-NEXT:    vmrhf %v4, %v4, %v4
-; CHECK-NEXT:    vmrlg %v3, %v3, %v3
-; CHECK-NEXT:    vuphh %v3, %v3
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v5, %v6, %v5
-; CHECK-NEXT:    vmrhf %v6, %v31, %v31
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v4, %v6, %v4
-; CHECK-NEXT:    vl %v6, 320(%r15)
-; CHECK-NEXT:    vpkg %v4, %v4, %v5
-; CHECK-NEXT:    vl %v5, 448(%r15)
-; CHECK-NEXT:    vx %v3, %v3, %v4
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v29, %v6, %v5, %v4
-; CHECK-NEXT:    vl %v4, 368(%r15)
-; CHECK-NEXT:    vl %v5, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v5, %v4, %v0
-; CHECK-NEXT:    vl %v4, 272(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v4, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v2, %v2
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v3, %v3
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
+; CHECK-NEXT:    vn %v0, %v0, %v1
+; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <16 x float> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x double> %val5, <16 x double> %val6
-  ret <16 x double> %sel
+;
+; CHECK-Z14-LABEL: fun33:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchdb %v0, %v26, %v30
+; CHECK-Z14-NEXT:    vfchdb %v1, %v24, %v28
+; CHECK-Z14-NEXT:    vpkg %v0, %v1, %v0
+; CHECK-Z14-NEXT:    vfchsb %v1, %v25, %v27
+; CHECK-Z14-NEXT:    vn %v0, %v0, %v1
+; CHECK-Z14-NEXT:    vsel %v24, %v29, %v31, %v0
+; CHECK-Z14-NEXT:    br %r14
+  %cmp0 = fcmp ogt <4 x double> %val1, %val2
+  %cmp1 = fcmp ogt <4 x float> %val3, %val4
+  %and = and <4 x i1> %cmp0, %cmp1
+  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
+  ret <4 x float> %sel
 }
 
-define <16 x i32> @fun194(<16 x i16> %val1, <16 x i16> %val2, <16 x double> %val3, <16 x double> %val4, <16 x i32> %val5, <16 x i32> %val6) {
-; CHECK-LABEL: fun194:
+define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
+; CHECK-LABEL: fun34:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 416(%r15)
-; CHECK-NEXT:    vl %v3, 352(%r15)
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v0, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v0, %v2, %v0
-; CHECK-NEXT:    vceqh %v2, %v26, %v30
-; CHECK-NEXT:    vuphh %v3, %v2
-; CHECK-NEXT:    vx %v0, %v3, %v0
-; CHECK-NEXT:    vl %v3, 448(%r15)
-; CHECK-NEXT:    vl %v4, 384(%r15)
-; CHECK-NEXT:    vsel %v28, %v4, %v3, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v3, %v29, %v3
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vpkg %v0, %v3, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v3, 368(%r15)
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vsel %v26, %v3, %v1, %v0
-; CHECK-NEXT:    vl %v0, 336(%r15)
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v3, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vx %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
+; CHECK-NEXT:    vmrlf [[REG0:%v[0-9]+]], %v27, %v27
+; CHECK-NEXT:    vmrlf [[REG1:%v[0-9]+]], %v25, %v25
+; CHECK-NEXT:    vldeb [[REG2:%v[0-9]+]], [[REG0]]
+; CHECK-NEXT:    vldeb [[REG3:%v[0-9]+]], [[REG1]]
+; CHECK-NEXT:    vfchdb [[REG4:%v[0-9]+]], [[REG3]], [[REG2]]
+; CHECK-NEXT:    vmrhf [[REG5:%v[0-9]+]], %v27, %v27
+; CHECK-NEXT:    vmrhf [[REG6:%v[0-9]+]], %v25, %v25
+; CHECK-DAG:     vldeb [[REG7:%v[0-9]+]], [[REG5]]
+; CHECK-DAG:     vl [[REG8:%v[0-9]+]], 176(%r15)
+; CHECK-DAG:     vldeb [[REG9:%v[0-9]+]], [[REG6]]
+; CHECK-DAG:     vl [[REG10:%v[0-9]+]], 160(%r15)
+; CHECK-DAG:     vfchdb [[REG11:%v[0-9]+]], [[REG9]], [[REG7]]
+; CHECK-DAG:     vpkg [[REG12:%v[0-9]+]], [[REG11]], [[REG4]]
+; CHECK-DAG:     vuphf [[REG13:%v[0-9]+]], [[REG12]]
+; CHECK-DAG:     vmrlg [[REG14:%v[0-9]+]], [[REG12]], [[REG12]]
+; CHECK-NEXT:    vfchdb [[REG15:%v[0-9]+]], %v24, %v28
+; CHECK-NEXT:    vfchdb [[REG16:%v[0-9]+]], %v26, %v30
+; CHECK-NEXT:    vuphf [[REG17:%v[0-9]+]], [[REG14]]
+; CHECK-NEXT:    vn [[REG18:%v[0-9]+]], [[REG16]], [[REG17]]
+; CHECK-NEXT:    vn [[REG19:%v[0-9]+]], [[REG15]], [[REG13]]
+; CHECK-NEXT:    vsel %v24, %v29, [[REG10]], [[REG19]]
+; CHECK-NEXT:    vsel %v26, %v31, [[REG8]], [[REG18]]
 ; CHECK-NEXT:    br %r14
-  %cmp0 = icmp eq <16 x i16> %val1, %val2
-  %cmp1 = fcmp ogt <16 x double> %val3, %val4
-  %and = xor <16 x i1> %cmp0, %cmp1
-  %sel = select <16 x i1> %and, <16 x i32> %val5, <16 x i32> %val6
-  ret <16 x i32> %sel
+;
+; CHECK-Z14-LABEL: fun34:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb %v4, %v25, %v27
+; CHECK-Z14-NEXT:    vuphf %v5, %v4
+; CHECK-Z14-NEXT:    vmrlg %v4, %v4, %v4
+; CHECK-Z14-NEXT:    vfchdb %v2, %v24, %v28
+; CHECK-Z14-NEXT:    vfchdb %v3, %v26, %v30
+; CHECK-Z14-NEXT:    vuphf %v4, %v4
+; CHECK-Z14-NEXT:    vl %v0, 176(%r15)
+; CHECK-Z14-NEXT:    vl %v1, 160(%r15)
+; CHECK-Z14-NEXT:    vn %v3, %v3, %v4
+; CHECK-Z14-NEXT:    vn %v2, %v2, %v5
+; CHECK-Z14-NEXT:    vsel %v24, %v29, %v1, %v2
+; CHECK-Z14-NEXT:    vsel %v26, %v31, %v0, %v3
+; CHECK-Z14-NEXT:    br %r14
+  %cmp0 = fcmp ogt <4 x double> %val1, %val2
+  %cmp1 = fcmp ogt <4 x float> %val3, %val4
+  %and = and <4 x i1> %cmp0, %cmp1
+  %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6
+  ret <4 x double> %sel
 }
-

test/CodeGen/SystemZ/vec-cmpsel.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;
 ; Test that vector compare / select combinations do not produce any
 ; unnecessary pack /unpack / shift instructions.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
-
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CHECK-Z14
 
 define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4) {
 ; CHECK-LABEL: fun0:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <2 x i8> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
   ret <2 x i8> %sel
 }
 
 define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4) {
 ; CHECK-LABEL: fun1:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-NEXT:    vuphb %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <2 x i8> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
   ret <2 x i16> %sel
 }
 
-define <2 x i32> @fun2(<2 x i8> %val1, <2 x i8> %val2, <2 x i32> %val3, <2 x i32> %val4) {
+define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4) {
 ; CHECK-LABEL: fun2:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i8> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
-  ret <2 x i32> %sel
+  %cmp = icmp eq <16 x i8> %val1, %val2
+  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %sel
 }
 
-define <2 x i64> @fun3(<2 x i8> %val1, <2 x i8> %val2, <2 x i64> %val3, <2 x i64> %val4) {
+define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4) {
 ; CHECK-LABEL: fun3:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-DAG:     vuphb [[REG0:%v[0-9]+]], %v0
+; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
+; CHECK-DAG:     vuphb [[REG1]], [[REG1]]
+; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG0]]
+; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i8> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
-  ret <2 x i64> %sel
+  %cmp = icmp eq <16 x i8> %val1, %val2
+  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
+  ret <16 x i16> %sel
 }
 
-define <2 x float> @fun4(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4) {
+define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4) {
 ; CHECK-LABEL: fun4:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
+; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i8> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
-  ret <2 x float> %sel
+  %cmp = icmp eq <32 x i8> %val1, %val2
+  %sel = select <32 x i1> %cmp, <32 x i8> %val3, <32 x i8> %val4
+  ret <32 x i8> %sel
 }
 
-define <2 x double> @fun5(<2 x i8> %val1, <2 x i8> %val2, <2 x double> %val3, <2 x double> %val4) {
+define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4) {
 ; CHECK-LABEL: fun5:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i8> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
-  ret <2 x double> %sel
-}
-
-define <2 x i8> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4) {
-; CHECK-LABEL: fun6:
-; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vpkh %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <2 x i16> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
   ret <2 x i8> %sel
 }
 
-define <2 x i16> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4) {
-; CHECK-LABEL: fun7:
+define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4) {
+; CHECK-LABEL: fun6:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <2 x i16> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
   ret <2 x i16> %sel
 }
 
-define <2 x i32> @fun8(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4) {
-; CHECK-LABEL: fun8:
+define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4) {
+; CHECK-LABEL: fun7:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vuphh %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <2 x i16> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
   ret <2 x i32> %sel
 }
 
-define <2 x i64> @fun9(<2 x i16> %val1, <2 x i16> %val2, <2 x i64> %val3, <2 x i64> %val4) {
+define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i8> %val3, <8 x i8> %val4) {
+; CHECK-LABEL: fun8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vceqh %v0, %v24, %v26
+; CHECK-NEXT:    vpkh %v0, %v0, %v0
+; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-NEXT:    br %r14
+  %cmp = icmp eq <8 x i16> %val1, %val2
+  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
+  ret <8 x i8> %sel
+}
+
+define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4) {
 ; CHECK-LABEL: fun9:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i16> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
-  ret <2 x i64> %sel
+  %cmp = icmp eq <8 x i16> %val1, %val2
+  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %sel
 }
 
-define <2 x float> @fun10(<2 x i16> %val1, <2 x i16> %val2, <2 x float> %val3, <2 x float> %val4) {
+define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4) {
 ; CHECK-LABEL: fun10:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-DAG:     vuphh [[REG0:%v[0-9]+]], %v0
+; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
+; CHECK-DAG:     vuphh [[REG1]], [[REG1]]
+; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG0]]
+; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i16> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
-  ret <2 x float> %sel
+  %cmp = icmp eq <8 x i16> %val1, %val2
+  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
+  ret <8 x i32> %sel
 }
 
-define <2 x double> @fun11(<2 x i16> %val1, <2 x i16> %val2, <2 x double> %val3, <2 x double> %val4) {
+define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i8> %val3, <16 x i8> %val4) {
 ; CHECK-LABEL: fun11:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-NEXT:    vceqh %v0, %v26, %v30
+; CHECK-NEXT:    vceqh %v1, %v24, %v28
+; CHECK-NEXT:    vpkh %v0, %v1, %v0
+; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i16> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
-  ret <2 x double> %sel
+  %cmp = icmp eq <16 x i16> %val1, %val2
+  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %sel
 }
 
-define <2 x i8> @fun12(<2 x i32> %val1, <2 x i32> %val2, <2 x i8> %val3, <2 x i8> %val4) {
+define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4) {
 ; CHECK-LABEL: fun12:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI12_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
+; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i32> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
-  ret <2 x i8> %sel
+  %cmp = icmp eq <16 x i16> %val1, %val2
+  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
+  ret <16 x i16> %sel
 }
 
 define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i16> %val3, <2 x i16> %val4) {
 ; CHECK-LABEL: fun13:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkf %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0

 ; CHECK-NEXT:    vuphf %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <2 x i32> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
   ret <2 x i64> %sel
 }
 
-define <2 x float> @fun16(<2 x i32> %val1, <2 x i32> %val2, <2 x float> %val3, <2 x float> %val4) {
+define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4) {
 ; CHECK-LABEL: fun16:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i32> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
-  ret <2 x float> %sel
-}
-
-define <2 x double> @fun17(<2 x i32> %val1, <2 x i32> %val2, <2 x double> %val3, <2 x double> %val4) {
-; CHECK-LABEL: fun17:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i32> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
-  ret <2 x double> %sel
-}
-
-define <2 x i8> @fun18(<2 x i64> %val1, <2 x i64> %val2, <2 x i8> %val3, <2 x i8> %val4) {
-; CHECK-LABEL: fun18:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v26
-; CHECK-NEXT:    vrepih %v1, 1807
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i64> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
-  ret <2 x i8> %sel
-}
-
-define <2 x i16> @fun19(<2 x i64> %val1, <2 x i64> %val2, <2 x i16> %val3, <2 x i16> %val4) {
-; CHECK-LABEL: fun19:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI19_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vceqg %v0, %v24, %v26
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i64> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun20(<2 x i64> %val1, <2 x i64> %val2, <2 x i32> %val3, <2 x i32> %val4) {
-; CHECK-LABEL: fun20:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v26
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i64> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
-  ret <2 x i32> %sel
-}
-
-define <2 x i64> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4) {
-; CHECK-LABEL: fun21:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i64> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
-  ret <2 x i64> %sel
-}
-
-define <2 x float> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x float> %val3, <2 x float> %val4) {
-; CHECK-LABEL: fun22:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v26
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i64> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
-  ret <2 x float> %sel
-}
-
-define <2 x double> @fun23(<2 x i64> %val1, <2 x i64> %val2, <2 x double> %val3, <2 x double> %val4) {
-; CHECK-LABEL: fun23:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <2 x i64> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
-  ret <2 x double> %sel
-}
-
-define <4 x i8> @fun24(<4 x i8> %val1, <4 x i8> %val2, <4 x i8> %val3, <4 x i8> %val4) {
-; CHECK-LABEL: fun24:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i8> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i8> %val3, <4 x i8> %val4
-  ret <4 x i8> %sel
-}
-
-define <4 x i16> @fun25(<4 x i8> %val1, <4 x i8> %val2, <4 x i16> %val3, <4 x i16> %val4) {
-; CHECK-LABEL: fun25:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i8> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
-  ret <4 x i16> %sel
-}
-
-define <4 x i32> @fun26(<4 x i8> %val1, <4 x i8> %val2, <4 x i32> %val3, <4 x i32> %val4) {
-; CHECK-LABEL: fun26:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i8> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun27(<4 x i8> %val1, <4 x i8> %val2, <4 x i64> %val3, <4 x i64> %val4) {
-; CHECK-LABEL: fun27:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i8> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
-  ret <4 x i64> %sel
-}
-
-define <4 x float> @fun28(<4 x i8> %val1, <4 x i8> %val2, <4 x float> %val3, <4 x float> %val4) {
-; CHECK-LABEL: fun28:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i8> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
-  ret <4 x float> %sel
-}
-
-define <4 x double> @fun29(<4 x i8> %val1, <4 x i8> %val2, <4 x double> %val3, <4 x double> %val4) {
-; CHECK-LABEL: fun29:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i8> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
-  ret <4 x double> %sel
-}
-
-define <4 x i8> @fun30(<4 x i16> %val1, <4 x i16> %val2, <4 x i8> %val3, <4 x i8> %val4) {
-; CHECK-LABEL: fun30:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i16> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i8> %val3, <4 x i8> %val4
-  ret <4 x i8> %sel
-}
-
-define <4 x i16> @fun31(<4 x i16> %val1, <4 x i16> %val2, <4 x i16> %val3, <4 x i16> %val4) {
-; CHECK-LABEL: fun31:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i16> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
-  ret <4 x i16> %sel
-}
-
-define <4 x i32> @fun32(<4 x i16> %val1, <4 x i16> %val2, <4 x i32> %val3, <4 x i32> %val4) {
-; CHECK-LABEL: fun32:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i16> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun33(<4 x i16> %val1, <4 x i16> %val2, <4 x i64> %val3, <4 x i64> %val4) {
-; CHECK-LABEL: fun33:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i16> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
-  ret <4 x i64> %sel
-}
-
-define <4 x float> @fun34(<4 x i16> %val1, <4 x i16> %val2, <4 x float> %val3, <4 x float> %val4) {
-; CHECK-LABEL: fun34:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i16> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
-  ret <4 x float> %sel
-}
-
-define <4 x double> @fun35(<4 x i16> %val1, <4 x i16> %val2, <4 x double> %val3, <4 x double> %val4) {
-; CHECK-LABEL: fun35:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i16> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
-  ret <4 x double> %sel
-}
-
-define <4 x i8> @fun36(<4 x i32> %val1, <4 x i32> %val2, <4 x i8> %val3, <4 x i8> %val4) {
-; CHECK-LABEL: fun36:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI36_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i32> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i8> %val3, <4 x i8> %val4
-  ret <4 x i8> %sel
-}
-
-define <4 x i16> @fun37(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4) {
-; CHECK-LABEL: fun37:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkf %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <4 x i32> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
   ret <4 x i16> %sel
 }
 
-define <4 x i32> @fun38(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4) {
-; CHECK-LABEL: fun38:
+define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: fun17:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <4 x i32> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
   ret <4 x i32> %sel
 }
 
-define <4 x i64> @fun39(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4) {
-; CHECK-LABEL: fun39:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i32> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
-  ret <4 x i64> %sel
-}
-
-define <4 x float> @fun40(<4 x i32> %val1, <4 x i32> %val2, <4 x float> %val3, <4 x float> %val4) {
-; CHECK-LABEL: fun40:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i32> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
-  ret <4 x float> %sel
-}
-
-define <4 x double> @fun41(<4 x i32> %val1, <4 x i32> %val2, <4 x double> %val3, <4 x double> %val4) {
-; CHECK-LABEL: fun41:
+define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4) {
+; CHECK-LABEL: fun18:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
+; CHECK-DAG:     vuphf [[REG0:%v[0-9]+]], %v0
+; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
+; CHECK-DAG:     vuphf [[REG1]], [[REG1]]
+; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG0]]
+; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <4 x i32> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
-  ret <4 x double> %sel
-}
-
-define <4 x i8> @fun42(<4 x i64> %val1, <4 x i64> %val2, <4 x i8> %val3, <4 x i8> %val4) {
-; CHECK-LABEL: fun42:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI42_0
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vceqg %v0, %v26, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i64> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i8> %val3, <4 x i8> %val4
-  ret <4 x i8> %sel
-}
-
-define <4 x i16> @fun43(<4 x i64> %val1, <4 x i64> %val2, <4 x i16> %val3, <4 x i16> %val4) {
-; CHECK-LABEL: fun43:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI43_0
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vceqg %v0, %v26, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i64> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
-  ret <4 x i16> %sel
-}
-
-define <4 x i32> @fun44(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4) {
-; CHECK-LABEL: fun44:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v26, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i64> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
-  ret <4 x i32> %sel
-}
-
-define <4 x i64> @fun45(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4) {
-; CHECK-LABEL: fun45:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vceqg %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i64> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
   ret <4 x i64> %sel
 }
 
-define <4 x float> @fun46(<4 x i64> %val1, <4 x i64> %val2, <4 x float> %val3, <4 x float> %val4) {
-; CHECK-LABEL: fun46:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v26, %v30
-; CHECK-NEXT:    vceqg %v1, %v24, %v28
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i64> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
-  ret <4 x float> %sel
-}
-
-define <4 x double> @fun47(<4 x i64> %val1, <4 x i64> %val2, <4 x double> %val3, <4 x double> %val4) {
-; CHECK-LABEL: fun47:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vceqg %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <4 x i64> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
-  ret <4 x double> %sel
-}
-
-define <8 x i8> @fun48(<8 x i8> %val1, <8 x i8> %val2, <8 x i8> %val3, <8 x i8> %val4) {
-; CHECK-LABEL: fun48:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i8> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun49(<8 x i8> %val1, <8 x i8> %val2, <8 x i16> %val3, <8 x i16> %val4) {
-; CHECK-LABEL: fun49:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i8> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun50(<8 x i8> %val1, <8 x i8> %val2, <8 x i32> %val3, <8 x i32> %val4) {
-; CHECK-LABEL: fun50:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i8> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun51(<8 x i8> %val1, <8 x i8> %val2, <8 x i64> %val3, <8 x i64> %val4) {
-; CHECK-LABEL: fun51:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v29, %v1
-; CHECK-NEXT:    vpkf %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v31, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 6
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v27, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i8> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i64> %val3, <8 x i64> %val4
-  ret <8 x i64> %sel
-}
-
-define <8 x float> @fun52(<8 x i8> %val1, <8 x i8> %val2, <8 x float> %val3, <8 x float> %val4) {
-; CHECK-LABEL: fun52:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i8> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
-  ret <8 x float> %sel
-}
-
-define <8 x double> @fun53(<8 x i8> %val1, <8 x i8> %val2, <8 x double> %val3, <8 x double> %val4) {
-; CHECK-LABEL: fun53:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v29, %v1
-; CHECK-NEXT:    vpkf %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v31, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 6
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v27, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i8> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x double> %val3, <8 x double> %val4
-  ret <8 x double> %sel
-}
-
-define <8 x i8> @fun54(<8 x i16> %val1, <8 x i16> %val2, <8 x i8> %val3, <8 x i8> %val4) {
-; CHECK-LABEL: fun54:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vpkh %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i16> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun55(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4) {
-; CHECK-LABEL: fun55:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i16> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun56(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4) {
-; CHECK-LABEL: fun56:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i16> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun57(<8 x i16> %val1, <8 x i16> %val2, <8 x i64> %val3, <8 x i64> %val4) {
-; CHECK-LABEL: fun57:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v29, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v31, %v1
-; CHECK-NEXT:    vmrlg %v1, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v27, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i16> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i64> %val3, <8 x i64> %val4
-  ret <8 x i64> %sel
-}
-
-define <8 x float> @fun58(<8 x i16> %val1, <8 x i16> %val2, <8 x float> %val3, <8 x float> %val4) {
-; CHECK-LABEL: fun58:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i16> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
-  ret <8 x float> %sel
-}
-
-define <8 x double> @fun59(<8 x i16> %val1, <8 x i16> %val2, <8 x double> %val3, <8 x double> %val4) {
-; CHECK-LABEL: fun59:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v26
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v29, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v31, %v1
-; CHECK-NEXT:    vmrlg %v1, %v0, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v27, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i16> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x double> %val3, <8 x double> %val4
-  ret <8 x double> %sel
-}
-
-define <8 x i8> @fun60(<8 x i32> %val1, <8 x i32> %val2, <8 x i8> %val3, <8 x i8> %val4) {
-; CHECK-LABEL: fun60:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI60_0
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vceqf %v0, %v26, %v30
-; CHECK-NEXT:    vceqf %v1, %v24, %v28
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i32> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun61(<8 x i32> %val1, <8 x i32> %val2, <8 x i16> %val3, <8 x i16> %val4) {
-; CHECK-LABEL: fun61:
+define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: fun19:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vceqf %v0, %v26, %v30
 ; CHECK-NEXT:    vceqf %v1, %v24, %v28
 ; CHECK-NEXT:    vpkf %v0, %v1, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <8 x i32> %val1, %val2
   %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
   ret <8 x i16> %sel
 }
 
-define <8 x i32> @fun62(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4) {
-; CHECK-LABEL: fun62:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vceqf %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i32> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun63(<8 x i32> %val1, <8 x i32> %val2, <8 x i64> %val3, <8 x i64> %val4) {
-; CHECK-LABEL: fun63:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v28
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vceqf %v1, %v26, %v30
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v27, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i32> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i64> %val3, <8 x i64> %val4
-  ret <8 x i64> %sel
-}
-
-define <8 x float> @fun64(<8 x i32> %val1, <8 x i32> %val2, <8 x float> %val3, <8 x float> %val4) {
-; CHECK-LABEL: fun64:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vceqf %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i32> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
-  ret <8 x float> %sel
-}
-
-define <8 x double> @fun65(<8 x i32> %val1, <8 x i32> %val2, <8 x double> %val3, <8 x double> %val4) {
-; CHECK-LABEL: fun65:
+define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4) {
+; CHECK-LABEL: fun20:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v24, %v28
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vceqf %v1, %v26, %v30
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v27, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v1, %v0
+; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
+; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
 ; CHECK-NEXT:    br %r14
   %cmp = icmp eq <8 x i32> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x double> %val3, <8 x double> %val4
-  ret <8 x double> %sel
-}
-
-define <8 x i8> @fun66(<8 x i64> %val1, <8 x i64> %val2, <8 x i8> %val3, <8 x i8> %val4) {
-; CHECK-LABEL: fun66:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v30, %v31
-; CHECK-NEXT:    vceqg %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v26, %v27
-; CHECK-NEXT:    vceqg %v2, %v24, %v25
-; CHECK-NEXT:    larl %r1, .LCPI66_0
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vlrepg %v1, 168(%r15)
-; CHECK-NEXT:    vlrepg %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i64> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun67(<8 x i64> %val1, <8 x i64> %val2, <8 x i16> %val3, <8 x i16> %val4) {
-; CHECK-LABEL: fun67:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v30, %v31
-; CHECK-NEXT:    vceqg %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vceqg %v1, %v26, %v27
-; CHECK-NEXT:    vceqg %v2, %v24, %v25
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i64> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun68(<8 x i64> %val1, <8 x i64> %val2, <8 x i32> %val3, <8 x i32> %val4) {
-; CHECK-LABEL: fun68:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v26, %v27
-; CHECK-NEXT:    vceqg %v1, %v24, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqg %v0, %v30, %v31
-; CHECK-NEXT:    vceqg %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i64> %val1, %val2
   %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
   ret <8 x i32> %sel
 }
 
-define <8 x i64> @fun69(<8 x i64> %val1, <8 x i64> %val2, <8 x i64> %val3, <8 x i64> %val4) {
-; CHECK-LABEL: fun69:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v24, %v25
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqg %v0, %v26, %v27
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v28, %v29
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v31
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i64> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i64> %val3, <8 x i64> %val4
-  ret <8 x i64> %sel
-}
-
-define <8 x float> @fun70(<8 x i64> %val1, <8 x i64> %val2, <8 x float> %val3, <8 x float> %val4) {
-; CHECK-LABEL: fun70:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqg %v0, %v26, %v27
-; CHECK-NEXT:    vceqg %v1, %v24, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqg %v0, %v30, %v31
-; CHECK-NEXT:    vceqg %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i64> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
-  ret <8 x float> %sel
-}
-
-define <8 x double> @fun71(<8 x i64> %val1, <8 x i64> %val2, <8 x double> %val3, <8 x double> %val4) {
-; CHECK-LABEL: fun71:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v24, %v25
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqg %v0, %v26, %v27
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v28, %v29
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v31
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <8 x i64> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x double> %val3, <8 x double> %val4
-  ret <8 x double> %sel
-}
-
-define <16 x i8> @fun72(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4) {
-; CHECK-LABEL: fun72:
+define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i32> %val3, <2 x i32> %val4) {
+; CHECK-LABEL: fun21:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
+; CHECK-NEXT:    vceqg %v0, %v24, %v26
+; CHECK-NEXT:    vpkg %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i8> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun73(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4) {
-; CHECK-LABEL: fun73:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i8> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun74(<16 x i8> %val1, <16 x i8> %val2, <16 x i32> %val3, <16 x i32> %val4) {
-; CHECK-LABEL: fun74:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v29, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v31, %v1
-; CHECK-NEXT:    vmrlg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v27, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i8> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i32> %val3, <16 x i32> %val4
-  ret <16 x i32> %sel
-}
-
-define <16 x i64> @fun75(<16 x i8> %val1, <16 x i8> %val2, <16 x i64> %val3, <16 x i64> %val4) {
-; CHECK-LABEL: fun75:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v2, %v1
-; CHECK-NEXT:    vpkf %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v2, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vsldb %v1, %v0, %v0, 6
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v30, %v27, %v2, %v1
-; CHECK-NEXT:    vl %v2, 256(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v25, %v29, %v2, %v1
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vsldb %v1, %v0, %v0, 10
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v27, %v31, %v2, %v1
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsldb %v1, %v0, %v0, 12
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 14
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i8> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i64> %val3, <16 x i64> %val4
-  ret <16 x i64> %sel
-}
-
-define <16 x float> @fun76(<16 x i8> %val1, <16 x i8> %val2, <16 x float> %val3, <16 x float> %val4) {
-; CHECK-LABEL: fun76:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v29, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v31, %v1
-; CHECK-NEXT:    vmrlg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v27, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i8> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x float> %val3, <16 x float> %val4
-  ret <16 x float> %sel
-}
-
-define <16 x double> @fun77(<16 x i8> %val1, <16 x i8> %val2, <16 x double> %val3, <16 x double> %val4) {
-; CHECK-LABEL: fun77:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqb %v0, %v24, %v26
-; CHECK-NEXT:    vuphb %v1, %v0
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v2, %v1
-; CHECK-NEXT:    vpkf %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v2, %v1
-; CHECK-NEXT:    vpkg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vsel %v28, %v25, %v2, %v1
-; CHECK-NEXT:    vl %v2, 240(%r15)
-; CHECK-NEXT:    vsldb %v1, %v0, %v0, 6
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v30, %v27, %v2, %v1
-; CHECK-NEXT:    vl %v2, 256(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v0, %v0
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v25, %v29, %v2, %v1
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vsldb %v1, %v0, %v0, 10
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v27, %v31, %v2, %v1
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsldb %v1, %v0, %v0, 12
-; CHECK-NEXT:    vuphb %v1, %v1
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 14
-; CHECK-NEXT:    vuphh %v1, %v1
-; CHECK-NEXT:    vuphb %v0, %v0
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i8> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x double> %val3, <16 x double> %val4
-  ret <16 x double> %sel
-}
-
-define <16 x i8> @fun78(<16 x i16> %val1, <16 x i16> %val2, <16 x i8> %val3, <16 x i8> %val4) {
-; CHECK-LABEL: fun78:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v26, %v30
-; CHECK-NEXT:    vceqh %v1, %v24, %v28
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i16> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun79(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4) {
-; CHECK-LABEL: fun79:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vceqh %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i16> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun80(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4) {
-; CHECK-LABEL: fun80:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v28
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v27, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i16> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i32> %val3, <16 x i32> %val4
-  ret <16 x i32> %sel
-}
-
-define <16 x i64> @fun81(<16 x i16> %val1, <16 x i16> %val2, <16 x i64> %val3, <16 x i64> %val4) {
-; CHECK-LABEL: fun81:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v28
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vl %v3, 288(%r15)
-; CHECK-NEXT:    vl %v4, 160(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v25, %v4, %v3, %v2
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v26, %v27, %v3, %v2
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v2, %v0
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vsldb %v0, %v1, %v1, 12
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i16> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i64> %val3, <16 x i64> %val4
-  ret <16 x i64> %sel
-}
-
-define <16 x float> @fun82(<16 x i16> %val1, <16 x i16> %val2, <16 x float> %val3, <16 x float> %val4) {
-; CHECK-LABEL: fun82:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v28
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v26, %v27, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i16> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x float> %val3, <16 x float> %val4
-  ret <16 x float> %sel
-}
-
-define <16 x double> @fun83(<16 x i16> %val1, <16 x i16> %val2, <16 x double> %val3, <16 x double> %val4) {
-; CHECK-LABEL: fun83:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqh %v0, %v24, %v28
-; CHECK-NEXT:    vuphh %v1, %v0
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vceqh %v1, %v26, %v30
-; CHECK-NEXT:    vuphh %v2, %v1
-; CHECK-NEXT:    vl %v3, 288(%r15)
-; CHECK-NEXT:    vl %v4, 160(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v25, %v4, %v3, %v2
-; CHECK-NEXT:    vpkg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vsel %v26, %v27, %v3, %v2
-; CHECK-NEXT:    vmrlg %v2, %v0, %v0
-; CHECK-NEXT:    vuphh %v2, %v2
-; CHECK-NEXT:    vsldb %v0, %v0, %v0, 12
-; CHECK-NEXT:    vl %v3, 256(%r15)
-; CHECK-NEXT:    vuphf %v2, %v2
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 272(%r15)
-; CHECK-NEXT:    vl %v3, 176(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v2, %v0
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v29, %v3, %v2, %v0
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vsldb %v0, %v1, %v1, 12
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vuphh %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i16> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x double> %val3, <16 x double> %val4
-  ret <16 x double> %sel
-}
-
-define <16 x i8> @fun84(<16 x i32> %val1, <16 x i32> %val2, <16 x i8> %val3, <16 x i8> %val4) {
-; CHECK-LABEL: fun84:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vceqf %v1, %v28, %v29
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vceqf %v1, %v26, %v27
-; CHECK-NEXT:    vceqf %v2, %v24, %v25
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i32> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun85(<16 x i32> %val1, <16 x i32> %val2, <16 x i16> %val3, <16 x i16> %val4) {
-; CHECK-LABEL: fun85:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v0, %v26, %v27
-; CHECK-NEXT:    vceqf %v1, %v24, %v25
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vceqf %v1, %v28, %v29
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i32> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun86(<16 x i32> %val1, <16 x i32> %val2, <16 x i32> %val3, <16 x i32> %val4) {
-; CHECK-LABEL: fun86:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqf %v0, %v24, %v25
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqf %v0, %v26, %v27
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vceqf %v0, %v28, %v29
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i32> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i32> %val3, <16 x i32> %val4
-  ret <16 x i32> %sel
-}
-
-define <16 x i64> @fun87(<16 x i32> %val1, <16 x i32> %val2, <16 x i64> %val3, <16 x i64> %val4) {
-; CHECK-LABEL: fun87:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v24, %v25
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphf %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vceqf %v2, %v26, %v27
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v0, %v2
-; CHECK-NEXT:    vsel %v0, %v4, %v3, %v0
-; CHECK-NEXT:    vceqf %v3, %v28, %v29
-; CHECK-NEXT:    vl %v5, 352(%r15)
-; CHECK-NEXT:    vl %v6, 224(%r15)
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vceqf %v4, %v30, %v31
-; CHECK-NEXT:    vl %v6, 384(%r15)
-; CHECK-NEXT:    vl %v7, 256(%r15)
-; CHECK-NEXT:    vuphf %v5, %v4
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v29, %v7, %v6, %v5
-; CHECK-NEXT:    vl %v5, 304(%r15)
-; CHECK-NEXT:    vl %v6, 176(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v6, %v5, %v1
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vl %v5, 208(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v30, %v5, %v2, %v1
-; CHECK-NEXT:    vmrlg %v1, %v3, %v3
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vlr %v28, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v4, %v4
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i32> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i64> %val3, <16 x i64> %val4
-  ret <16 x i64> %sel
-}
-
-define <16 x float> @fun88(<16 x i32> %val1, <16 x i32> %val2, <16 x float> %val3, <16 x float> %val4) {
-; CHECK-LABEL: fun88:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqf %v0, %v24, %v25
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vceqf %v0, %v26, %v27
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vceqf %v0, %v28, %v29
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vceqf %v0, %v30, %v31
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i32> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x float> %val3, <16 x float> %val4
-  ret <16 x float> %sel
-}
-
-define <16 x double> @fun89(<16 x i32> %val1, <16 x i32> %val2, <16 x double> %val3, <16 x double> %val4) {
-; CHECK-LABEL: fun89:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vceqf %v1, %v24, %v25
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vuphf %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vceqf %v2, %v26, %v27
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vuphf %v0, %v2
-; CHECK-NEXT:    vsel %v0, %v4, %v3, %v0
-; CHECK-NEXT:    vceqf %v3, %v28, %v29
-; CHECK-NEXT:    vl %v5, 352(%r15)
-; CHECK-NEXT:    vl %v6, 224(%r15)
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vceqf %v4, %v30, %v31
-; CHECK-NEXT:    vl %v6, 384(%r15)
-; CHECK-NEXT:    vl %v7, 256(%r15)
-; CHECK-NEXT:    vuphf %v5, %v4
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vsel %v29, %v7, %v6, %v5
-; CHECK-NEXT:    vl %v5, 304(%r15)
-; CHECK-NEXT:    vl %v6, 176(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v26, %v6, %v5, %v1
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vl %v5, 208(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v30, %v5, %v2, %v1
-; CHECK-NEXT:    vmrlg %v1, %v3, %v3
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vlr %v28, %v0
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v4, %v4
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i32> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x double> %val3, <16 x double> %val4
-  ret <16 x double> %sel
-}
-
-define <16 x i8> @fun90(<16 x i64> %val1, <16 x i64> %val2, <16 x i8> %val3, <16 x i8> %val4) {
-; CHECK-LABEL: fun90:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vceqg %v1, %v27, %v1
-; CHECK-NEXT:    vceqg %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vceqg %v1, %v30, %v1
-; CHECK-NEXT:    vceqg %v2, %v28, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vceqg %v2, %v26, %v2
-; CHECK-NEXT:    vceqg %v3, %v24, %v3
-; CHECK-NEXT:    vpkg %v2, %v3, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i64> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun91(<16 x i64> %val1, <16 x i64> %val2, <16 x i16> %val3, <16 x i16> %val4) {
-; CHECK-LABEL: fun91:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v0
-; CHECK-NEXT:    vceqg %v1, %v28, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vceqg %v1, %v26, %v1
-; CHECK-NEXT:    vceqg %v2, %v24, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vceqg %v1, %v27, %v1
-; CHECK-NEXT:    vceqg %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i64> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun92(<16 x i64> %val1, <16 x i64> %val2, <16 x i32> %val3, <16 x i32> %val4) {
-; CHECK-LABEL: fun92:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v26, %v0
-; CHECK-NEXT:    vceqg %v1, %v24, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 352(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v0
-; CHECK-NEXT:    vceqg %v1, %v28, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 368(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 384(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i64> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i32> %val3, <16 x i32> %val4
-  ret <16 x i32> %sel
-}
-
-define <16 x i64> @fun93(<16 x i64> %val1, <16 x i64> %val2, <16 x i64> %val3, <16 x i64> %val4) {
-; CHECK-LABEL: fun93:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vl %v1, 416(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vceqg %v0, %v24, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vceqg %v0, %v26, %v0
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vl %v1, 448(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vceqg %v0, %v28, %v0
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 224(%r15)
-; CHECK-NEXT:    vl %v1, 480(%r15)
-; CHECK-NEXT:    vl %v2, 352(%r15)
-; CHECK-NEXT:    vceqg %v0, %v25, %v0
-; CHECK-NEXT:    vsel %v25, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 496(%r15)
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v29, %v0
-; CHECK-NEXT:    vl %v1, 512(%r15)
-; CHECK-NEXT:    vl %v2, 384(%r15)
-; CHECK-NEXT:    vsel %v29, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vl %v1, 528(%r15)
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i64> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i64> %val3, <16 x i64> %val4
-  ret <16 x i64> %sel
-}
-
-define <16 x float> @fun94(<16 x i64> %val1, <16 x i64> %val2, <16 x float> %val3, <16 x float> %val4) {
-; CHECK-LABEL: fun94:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vceqg %v0, %v26, %v0
-; CHECK-NEXT:    vceqg %v1, %v24, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 352(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v0
-; CHECK-NEXT:    vceqg %v1, %v28, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 368(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vceqg %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 384(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vceqg %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i64> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x float> %val3, <16 x float> %val4
-  ret <16 x float> %sel
-}
-
-define <16 x double> @fun95(<16 x i64> %val1, <16 x i64> %val2, <16 x double> %val3, <16 x double> %val4) {
-; CHECK-LABEL: fun95:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vl %v1, 416(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vceqg %v0, %v24, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vceqg %v0, %v26, %v0
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vl %v1, 448(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vceqg %v0, %v28, %v0
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vceqg %v0, %v30, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 224(%r15)
-; CHECK-NEXT:    vl %v1, 480(%r15)
-; CHECK-NEXT:    vl %v2, 352(%r15)
-; CHECK-NEXT:    vceqg %v0, %v25, %v0
-; CHECK-NEXT:    vsel %v25, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 496(%r15)
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vceqg %v0, %v27, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 256(%r15)
-; CHECK-NEXT:    vceqg %v0, %v29, %v0
-; CHECK-NEXT:    vl %v1, 512(%r15)
-; CHECK-NEXT:    vl %v2, 384(%r15)
-; CHECK-NEXT:    vsel %v29, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vceqg %v0, %v31, %v0
-; CHECK-NEXT:    vl %v1, 528(%r15)
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = icmp eq <16 x i64> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x double> %val3, <16 x double> %val4
-  ret <16 x double> %sel
+  %cmp = icmp eq <2 x i64> %val1, %val2
+  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
+  ret <2 x i32> %sel
 }
 
-define <2 x i8> @fun96(<2 x float> %val1, <2 x float> %val2, <2 x i8> %val3, <2 x i8> %val4) {
-; CHECK-LABEL: fun96:
+define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: fun22:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    larl %r1, .LCPI96_0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
+; CHECK-NEXT:    vceqg %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x float> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
-  ret <2 x i8> %sel
+  %cmp = icmp eq <2 x i64> %val1, %val2
+  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %sel
 }
 
-define <2 x i16> @fun97(<2 x float> %val1, <2 x float> %val2, <2 x i16> %val3, <2 x i16> %val4) {
-; CHECK-LABEL: fun97:
+define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: fun23:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
+; CHECK-NEXT:    vceqg %v0, %v26, %v30
+; CHECK-NEXT:    vceqg %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x float> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
-  ret <2 x i16> %sel
+  %cmp = icmp eq <4 x i64> %val1, %val2
+  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %sel
 }
 
-define <2 x i32> @fun98(<2 x float> %val1, <2 x float> %val2, <2 x i32> %val3, <2 x i32> %val4) {
-; CHECK-LABEL: fun98:
+define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4) {
+; CHECK-LABEL: fun24:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
+; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
+; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x float> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
-  ret <2 x i32> %sel
+  %cmp = icmp eq <4 x i64> %val1, %val2
+  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
+  ret <4 x i64> %sel
 }
 
-define <2 x i64> @fun99(<2 x float> %val1, <2 x float> %val2, <2 x i64> %val3, <2 x i64> %val4) {
-; CHECK-LABEL: fun99:
+define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4) {
+; CHECK-LABEL: fun25:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
 ; CHECK-NEXT:    vmrhf %v1, %v26, %v26
 ; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x float> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
-  ret <2 x i64> %sel
-}
 
-define <2 x float> @fun100(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4) {
-; CHECK-LABEL: fun100:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
+; CHECK-Z14-LABEL: fun25:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
+; CHECK-Z14-NEXT:    br %r14
+
   %cmp = fcmp ogt <2 x float> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
   ret <2 x float> %sel
 }
 
-define <2 x double> @fun101(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4) {
-; CHECK-LABEL: fun101:
+define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: fun26:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
 ; CHECK-NEXT:    vmrhf %v1, %v26, %v26
 ; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
 ; CHECK-NEXT:    vuphf %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
+
+; CHECK-Z14-LABEL: fun26:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vuphf   %v0, %v0
+; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
+; CHECK-Z14-NEXT:    br %r14
+
   %cmp = fcmp ogt <2 x float> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
   ret <2 x double> %sel
 }
 
-define <2 x i8> @fun102(<2 x double> %val1, <2 x double> %val2, <2 x i8> %val3, <2 x i8> %val4) {
-; CHECK-LABEL: fun102:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v26
-; CHECK-NEXT:    vrepih %v1, 1807
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x double> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
-  ret <2 x i8> %sel
-}
-
-define <2 x i16> @fun103(<2 x double> %val1, <2 x double> %val2, <2 x i16> %val3, <2 x i16> %val4) {
-; CHECK-LABEL: fun103:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI103_0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vfchdb %v0, %v24, %v26
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x double> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
-  ret <2 x i16> %sel
-}
-
-define <2 x i32> @fun104(<2 x double> %val1, <2 x double> %val2, <2 x i32> %val3, <2 x i32> %val4) {
-; CHECK-LABEL: fun104:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v26
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x double> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
-  ret <2 x i32> %sel
-}
-
-define <2 x i64> @fun105(<2 x double> %val1, <2 x double> %val2, <2 x i64> %val3, <2 x i64> %val4) {
-; CHECK-LABEL: fun105:
+; Test a widening select of floats.
+define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4) {
+; CHECK-LABEL: fun27:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v26
+; CHECK-NEXT:    vceqb %v0, %v24, %v26
+; CHECK-NEXT:    vuphb %v0, %v0
+; CHECK-NEXT:    vuphh %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x double> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
-  ret <2 x i64> %sel
-}
 
-define <2 x float> @fun106(<2 x double> %val1, <2 x double> %val2, <2 x float> %val3, <2 x float> %val4) {
-; CHECK-LABEL: fun106:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v26
-; CHECK-NEXT:    vpkg %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %cmp = icmp eq <2 x i8> %val1, %val2
   %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
   ret <2 x float> %sel
 }
 
-define <2 x double> @fun107(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4) {
-; CHECK-LABEL: fun107:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v26
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <2 x double> %val1, %val2
-  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
-  ret <2 x double> %sel
-}
-
-define <4 x i8> @fun108(<4 x float> %val1, <4 x float> %val2, <4 x i8> %val3, <4 x i8> %val4) {
-; CHECK-LABEL: fun108:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    larl %r1, .LCPI108_0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x float> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i8> %val3, <4 x i8> %val4
-  ret <4 x i8> %sel
-}
-
-define <4 x i16> @fun109(<4 x float> %val1, <4 x float> %val2, <4 x i16> %val3, <4 x i16> %val4) {
-; CHECK-LABEL: fun109:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vpkf %v0, %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x float> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
-  ret <4 x i16> %sel
-}
-
-define <4 x i32> @fun110(<4 x float> %val1, <4 x float> %val2, <4 x i32> %val3, <4 x i32> %val4) {
-; CHECK-LABEL: fun110:
+define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: fun28:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
 ; CHECK-NEXT:    vmrhf %v1, %v26, %v26
 ; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x float> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
-  ret <4 x i32> %sel
-}
 
-define <4 x i64> @fun111(<4 x float> %val1, <4 x float> %val2, <4 x i64> %val3, <4 x i64> %val4) {
-; CHECK-LABEL: fun111:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x float> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
-  ret <4 x i64> %sel
-}
+; CHECK-Z14-LABEL: fun28:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
+; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
+; CHECK-Z14-NEXT:    br %r14
 
-define <4 x float> @fun112(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4) {
-; CHECK-LABEL: fun112:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v26, %v26
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
-; CHECK-NEXT:    br %r14
   %cmp = fcmp ogt <4 x float> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
   ret <4 x float> %sel
 }
 
-define <4 x double> @fun113(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4) {
-; CHECK-LABEL: fun113:
+define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4) {
+; CHECK-LABEL: fun29:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vfchdb %v0, %v1, %v0
 ; CHECK-NEXT:    vmrhf %v1, %v26, %v26
 ; CHECK-NEXT:    vmrhf %v2, %v24, %v24
 ; CHECK-NEXT:    vldeb %v1, %v1
 ; CHECK-NEXT:    vldeb %v2, %v2
 ; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v24, %v28, %v25, %v1
-; CHECK-NEXT:    vsel %v26, %v30, %v27, %v0
-; CHECK-NEXT:    br %r14
+; CHECK-NEXT:    vpkg [[REG0:%v[0-9]+]], %v1, %v0
+; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
+; CHECK-DAG:     vuphf [[REG1]], [[REG1]]
+; CHECK-DAG:     vuphf [[REG2:%v[0-9]+]], [[REG0]]
+; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG2]]
+; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
+; CHECK-NEXT:    br %r14
+
+; CHECK-Z14-LABEL: fun29:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
+; CHECK-Z14-DAG:     vuphf   [[REG0:%v[0-9]+]], %v0
+; CHECK-Z14-DAG:     vmrlg   [[REG1:%v[0-9]+]], %v0, %v0
+; CHECK-Z14-DAG:     vuphf   [[REG1]], [[REG1]]
+; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v25, [[REG0]]
+; CHECK-Z14-NEXT:    vsel    %v26, %v30, %v27, [[REG1]]
+; CHECK-Z14-NEXT:    br %r14
+
   %cmp = fcmp ogt <4 x float> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
   ret <4 x double> %sel
 }
 
-define <4 x i8> @fun114(<4 x double> %val1, <4 x double> %val2, <4 x i8> %val3, <4 x i8> %val4) {
-; CHECK-LABEL: fun114:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI114_0
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v30
-; CHECK-NEXT:    vfchdb %v1, %v24, %v28
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x double> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i8> %val3, <4 x i8> %val4
-  ret <4 x i8> %sel
+define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x float> %val3, <8 x float> %val4) {
+; CHECK-Z14-LABEL: fun30:
+; CHECK-Z14:       # BB#0:
+; CHECK-Z14-DAG:     vfchsb  [[REG0:%v[0-9]+]], %v26, %v30
+; CHECK-Z14-DAG:     vfchsb  [[REG1:%v[0-9]+]], %v24, %v28
+; CHECK-Z14-DAG:     vsel    %v24, %v25, %v29, [[REG1]]
+; CHECK-Z14-DAG:     vsel    %v26, %v27, %v31, [[REG0]]
+; CHECK-Z14-NEXT:    br %r14
+  %cmp = fcmp ogt <8 x float> %val1, %val2
+  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
+  ret <8 x float> %sel
 }
 
-define <4 x i16> @fun115(<4 x double> %val1, <4 x double> %val2, <4 x i16> %val3, <4 x i16> %val4) {
-; CHECK-LABEL: fun115:
+define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x float> %val3, <2 x float> %val4) {
+; CHECK-LABEL: fun31:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    larl %r1, .LCPI115_0
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v30
-; CHECK-NEXT:    vfchdb %v1, %v24, %v28
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
+; CHECK-NEXT:    vfchdb %v0, %v24, %v26
+; CHECK-NEXT:    vpkg %v0, %v0, %v0
+; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x double> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
-  ret <4 x i16> %sel
-}
 
-define <4 x i32> @fun116(<4 x double> %val1, <4 x double> %val2, <4 x i32> %val3, <4 x i32> %val4) {
-; CHECK-LABEL: fun116:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v26, %v30
-; CHECK-NEXT:    vfchdb %v1, %v24, %v28
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x double> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
-  ret <4 x i32> %sel
+  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
+  ret <2 x float> %sel
 }
 
-define <4 x i64> @fun117(<4 x double> %val1, <4 x double> %val2, <4 x i64> %val3, <4 x i64> %val4) {
-; CHECK-LABEL: fun117:
+define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: fun32:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vfchdb %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
+; CHECK-NEXT:    vfchdb %v0, %v24, %v26
+; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <4 x double> %val1, %val2
-  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
-  ret <4 x i64> %sel
+  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %sel
 }
 
-define <4 x float> @fun118(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4) {
-; CHECK-LABEL: fun118:
+define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: fun33:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vfchdb %v0, %v26, %v30
 ; CHECK-NEXT:    vfchdb %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
 ; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
 ; CHECK-NEXT:    br %r14
   %cmp = fcmp ogt <4 x double> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
   ret <4 x float> %sel
 }
 
-define <4 x double> @fun119(<4 x double> %val1, <4 x double> %val2, <4 x double> %val3, <4 x double> %val4) {
-; CHECK-LABEL: fun119:
+define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x double> %val3, <4 x double> %val4) {
+; CHECK-LABEL: fun34:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v24, %v28
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vfchdb %v0, %v26, %v30
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
+; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v26, %v30
+; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v24, %v28
+; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
+; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
 ; CHECK-NEXT:    br %r14
   %cmp = fcmp ogt <4 x double> %val1, %val2
   %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
   ret <4 x double> %sel
 }
-
-define <8 x i8> @fun120(<8 x float> %val1, <8 x float> %val2, <8 x i8> %val3, <8 x i8> %val4) {
-; CHECK-LABEL: fun120:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    larl %r1, .LCPI120_0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x float> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun121(<8 x float> %val1, <8 x float> %val2, <8 x i16> %val3, <8 x i16> %val4) {
-; CHECK-LABEL: fun121:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x float> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun122(<8 x float> %val1, <8 x float> %val2, <8 x i32> %val3, <8 x i32> %val4) {
-; CHECK-LABEL: fun122:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x float> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun123(<8 x float> %val1, <8 x float> %val2, <8 x i64> %val3, <8 x i64> %val4) {
-; CHECK-LABEL: fun123:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v27, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x float> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i64> %val3, <8 x i64> %val4
-  ret <8 x i64> %sel
-}
-
-define <8 x float> @fun124(<8 x float> %val1, <8 x float> %val2, <8 x float> %val3, <8 x float> %val4) {
-; CHECK-LABEL: fun124:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
-; CHECK-NEXT:    vmrlf %v0, %v30, %v30
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vsel %v26, %v27, %v31, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x float> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
-  ret <8 x float> %sel
-}
-
-define <8 x double> @fun125(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4) {
-; CHECK-LABEL: fun125:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v28, %v28
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vuphf %v1, %v0
-; CHECK-NEXT:    vsel %v24, %v25, %v2, %v1
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrlg %v0, %v0, %v0
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 192(%r15)
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vuphf %v2, %v1
-; CHECK-NEXT:    vsel %v28, %v29, %v3, %v2
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v27, %v2, %v0
-; CHECK-NEXT:    vmrlg %v0, %v1, %v1
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vuphf %v0, %v0
-; CHECK-NEXT:    vsel %v30, %v31, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x float> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x double> %val3, <8 x double> %val4
-  ret <8 x double> %sel
-}
-
-define <8 x i8> @fun126(<8 x double> %val1, <8 x double> %val2, <8 x i8> %val3, <8 x i8> %val4) {
-; CHECK-LABEL: fun126:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v26, %v27
-; CHECK-NEXT:    vfchdb %v2, %v24, %v25
-; CHECK-NEXT:    larl %r1, .LCPI126_0
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 0(%r1)
-; CHECK-NEXT:    vperm %v0, %v1, %v0, %v2
-; CHECK-NEXT:    vlrepg %v1, 168(%r15)
-; CHECK-NEXT:    vlrepg %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x double> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
-  ret <8 x i8> %sel
-}
-
-define <8 x i16> @fun127(<8 x double> %val1, <8 x double> %val2, <8 x i16> %val3, <8 x i16> %val4) {
-; CHECK-LABEL: fun127:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vfchdb %v1, %v26, %v27
-; CHECK-NEXT:    vfchdb %v2, %v24, %v25
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x double> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
-  ret <8 x i16> %sel
-}
-
-define <8 x i32> @fun128(<8 x double> %val1, <8 x double> %val2, <8 x i32> %val3, <8 x i32> %val4) {
-; CHECK-LABEL: fun128:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v26, %v27
-; CHECK-NEXT:    vfchdb %v1, %v24, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x double> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
-  ret <8 x i32> %sel
-}
-
-define <8 x i64> @fun129(<8 x double> %val1, <8 x double> %val2, <8 x i64> %val3, <8 x i64> %val4) {
-; CHECK-LABEL: fun129:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v24, %v25
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v27
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v29
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x double> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x i64> %val3, <8 x i64> %val4
-  ret <8 x i64> %sel
-}
-
-define <8 x float> @fun130(<8 x double> %val1, <8 x double> %val2, <8 x float> %val3, <8 x float> %val4) {
-; CHECK-LABEL: fun130:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vfchdb %v0, %v26, %v27
-; CHECK-NEXT:    vfchdb %v1, %v24, %v25
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vfchdb %v1, %v28, %v29
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x double> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
-  ret <8 x float> %sel
-}
-
-define <8 x double> @fun131(<8 x double> %val1, <8 x double> %val2, <8 x double> %val3, <8 x double> %val4) {
-; CHECK-LABEL: fun131:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v24, %v25
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v27
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v29
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v31
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <8 x double> %val1, %val2
-  %sel = select <8 x i1> %cmp, <8 x double> %val3, <8 x double> %val4
-  ret <8 x double> %sel
-}
-
-define <16 x i8> @fun132(<16 x float> %val1, <16 x float> %val2, <16 x i8> %val3, <16 x i8> %val4) {
-; CHECK-LABEL: fun132:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vmrhf %v4, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v29, %v29
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v27, %v27
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v27, %v27
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vmrlf %v2, %v25, %v25
-; CHECK-NEXT:    vmrlf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vmrhf %v3, %v25, %v25
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vpkg %v2, %v3, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x float> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun133(<16 x float> %val1, <16 x float> %val2, <16 x i16> %val3, <16 x i16> %val4) {
-; CHECK-LABEL: fun133:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vmrhf %v3, %v24, %v24
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v25, %v25
-; CHECK-NEXT:    vmrlf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v25, %v25
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vmrhf %v3, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vmrlf %v1, %v29, %v29
-; CHECK-NEXT:    vmrlf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vmrhf %v2, %v29, %v29
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x float> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun134(<16 x float> %val1, <16 x float> %val2, <16 x i32> %val3, <16 x i32> %val4) {
-; CHECK-LABEL: fun134:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v25, %v25
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v25, %v25
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v29, %v29
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v29, %v29
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x float> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i32> %val3, <16 x i32> %val4
-  ret <16 x i32> %sel
-}
-
-define <16 x i64> @fun135(<16 x float> %val1, <16 x float> %val2, <16 x i64> %val3, <16 x i64> %val4) {
-; CHECK-LABEL: fun135:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v25, %v25
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v25, %v25
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vl %v6, 224(%r15)
-; CHECK-NEXT:    vl %v7, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vpkg %v1, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vmrhf %v5, %v28, %v28
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vmrhf %v2, %v27, %v27
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vpkg %v2, %v2, %v0
-; CHECK-NEXT:    vuphf %v0, %v2
-; CHECK-NEXT:    vsel %v0, %v4, %v3, %v0
-; CHECK-NEXT:    vmrlf %v3, %v29, %v29
-; CHECK-NEXT:    vmrlf %v4, %v28, %v28
-; CHECK-NEXT:    vlr %v28, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v29, %v29
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vfchdb %v4, %v5, %v4
-; CHECK-NEXT:    vl %v5, 352(%r15)
-; CHECK-NEXT:    vpkg %v3, %v4, %v3
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vmrlf %v4, %v31, %v31
-; CHECK-NEXT:    vmrlf %v5, %v30, %v30
-; CHECK-NEXT:    vmrhf %v6, %v30, %v30
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vfchdb %v4, %v5, %v4
-; CHECK-NEXT:    vmrhf %v5, %v31, %v31
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v5, %v6, %v5
-; CHECK-NEXT:    vl %v6, 384(%r15)
-; CHECK-NEXT:    vpkg %v4, %v5, %v4
-; CHECK-NEXT:    vuphf %v5, %v4
-; CHECK-NEXT:    vsel %v29, %v7, %v6, %v5
-; CHECK-NEXT:    vl %v5, 304(%r15)
-; CHECK-NEXT:    vl %v6, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v6, %v5, %v1
-; CHECK-NEXT:    vl %v5, 208(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v30, %v5, %v2, %v1
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v3, %v3
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v4, %v4
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x float> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i64> %val3, <16 x i64> %val4
-  ret <16 x i64> %sel
-}
-
-define <16 x float> @fun136(<16 x float> %val1, <16 x float> %val2, <16 x float> %val3, <16 x float> %val4) {
-; CHECK-LABEL: fun136:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v25, %v25
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v25, %v25
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v1, %v26, %v26
-; CHECK-NEXT:    vmrhf %v2, %v26, %v26
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v27, %v27
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v29, %v29
-; CHECK-NEXT:    vmrlf %v1, %v28, %v28
-; CHECK-NEXT:    vmrhf %v2, %v28, %v28
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v29, %v29
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vmrlf %v0, %v31, %v31
-; CHECK-NEXT:    vmrlf %v1, %v30, %v30
-; CHECK-NEXT:    vmrhf %v2, %v30, %v30
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v31, %v31
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 208(%r15)
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 272(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x float> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x float> %val3, <16 x float> %val4
-  ret <16 x float> %sel
-}
-
-define <16 x double> @fun137(<16 x float> %val1, <16 x float> %val2, <16 x double> %val3, <16 x double> %val4) {
-; CHECK-LABEL: fun137:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vmrlf %v0, %v25, %v25
-; CHECK-NEXT:    vmrlf %v1, %v24, %v24
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vfchdb %v0, %v1, %v0
-; CHECK-NEXT:    vmrhf %v1, %v25, %v25
-; CHECK-NEXT:    vmrhf %v2, %v24, %v24
-; CHECK-NEXT:    vldeb %v1, %v1
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vl %v4, 192(%r15)
-; CHECK-NEXT:    vl %v6, 224(%r15)
-; CHECK-NEXT:    vl %v7, 256(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vpkg %v1, %v1, %v0
-; CHECK-NEXT:    vuphf %v0, %v1
-; CHECK-NEXT:    vsel %v24, %v3, %v2, %v0
-; CHECK-NEXT:    vmrlf %v0, %v27, %v27
-; CHECK-NEXT:    vmrlf %v2, %v26, %v26
-; CHECK-NEXT:    vmrhf %v3, %v26, %v26
-; CHECK-NEXT:    vmrhf %v5, %v28, %v28
-; CHECK-NEXT:    vmrlg %v1, %v1, %v1
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vldeb %v0, %v0
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vfchdb %v0, %v2, %v0
-; CHECK-NEXT:    vmrhf %v2, %v27, %v27
-; CHECK-NEXT:    vldeb %v2, %v2
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vfchdb %v2, %v3, %v2
-; CHECK-NEXT:    vl %v3, 320(%r15)
-; CHECK-NEXT:    vpkg %v2, %v2, %v0
-; CHECK-NEXT:    vuphf %v0, %v2
-; CHECK-NEXT:    vsel %v0, %v4, %v3, %v0
-; CHECK-NEXT:    vmrlf %v3, %v29, %v29
-; CHECK-NEXT:    vmrlf %v4, %v28, %v28
-; CHECK-NEXT:    vlr %v28, %v0
-; CHECK-NEXT:    vldeb %v3, %v3
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vfchdb %v3, %v4, %v3
-; CHECK-NEXT:    vmrhf %v4, %v29, %v29
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vfchdb %v4, %v5, %v4
-; CHECK-NEXT:    vl %v5, 352(%r15)
-; CHECK-NEXT:    vpkg %v3, %v4, %v3
-; CHECK-NEXT:    vuphf %v4, %v3
-; CHECK-NEXT:    vsel %v25, %v6, %v5, %v4
-; CHECK-NEXT:    vmrlf %v4, %v31, %v31
-; CHECK-NEXT:    vmrlf %v5, %v30, %v30
-; CHECK-NEXT:    vmrhf %v6, %v30, %v30
-; CHECK-NEXT:    vldeb %v4, %v4
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vfchdb %v4, %v5, %v4
-; CHECK-NEXT:    vmrhf %v5, %v31, %v31
-; CHECK-NEXT:    vldeb %v5, %v5
-; CHECK-NEXT:    vldeb %v6, %v6
-; CHECK-NEXT:    vfchdb %v5, %v6, %v5
-; CHECK-NEXT:    vl %v6, 384(%r15)
-; CHECK-NEXT:    vpkg %v4, %v5, %v4
-; CHECK-NEXT:    vuphf %v5, %v4
-; CHECK-NEXT:    vsel %v29, %v7, %v6, %v5
-; CHECK-NEXT:    vl %v5, 304(%r15)
-; CHECK-NEXT:    vl %v6, 176(%r15)
-; CHECK-NEXT:    vsel %v26, %v6, %v5, %v1
-; CHECK-NEXT:    vl %v5, 208(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v2, %v2
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v30, %v5, %v2, %v1
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v3, %v3
-; CHECK-NEXT:    vl %v3, 240(%r15)
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v27, %v3, %v2, %v1
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vl %v3, 272(%r15)
-; CHECK-NEXT:    vmrlg %v1, %v4, %v4
-; CHECK-NEXT:    vuphf %v1, %v1
-; CHECK-NEXT:    vsel %v31, %v3, %v2, %v1
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x float> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x double> %val3, <16 x double> %val4
-  ret <16 x double> %sel
-}
-
-define <16 x i8> @fun138(<16 x double> %val1, <16 x double> %val2, <16 x i8> %val3, <16 x i8> %val4) {
-; CHECK-LABEL: fun138:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v27, %v1
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 208(%r15)
-; CHECK-NEXT:    vl %v2, 192(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v30, %v1
-; CHECK-NEXT:    vfchdb %v2, %v28, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vl %v2, 176(%r15)
-; CHECK-NEXT:    vl %v3, 160(%r15)
-; CHECK-NEXT:    vfchdb %v2, %v26, %v2
-; CHECK-NEXT:    vfchdb %v3, %v24, %v3
-; CHECK-NEXT:    vpkg %v2, %v3, %v2
-; CHECK-NEXT:    vpkf %v1, %v2, %v1
-; CHECK-NEXT:    vpkh %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 304(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x double> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
-  ret <16 x i8> %sel
-}
-
-define <16 x i16> @fun139(<16 x double> %val1, <16 x double> %val2, <16 x i16> %val3, <16 x i16> %val4) {
-; CHECK-LABEL: fun139:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v0
-; CHECK-NEXT:    vfchdb %v1, %v28, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 176(%r15)
-; CHECK-NEXT:    vl %v2, 160(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v26, %v1
-; CHECK-NEXT:    vfchdb %v2, %v24, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 320(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 240(%r15)
-; CHECK-NEXT:    vl %v2, 224(%r15)
-; CHECK-NEXT:    vfchdb %v1, %v27, %v1
-; CHECK-NEXT:    vfchdb %v2, %v25, %v2
-; CHECK-NEXT:    vpkg %v1, %v2, %v1
-; CHECK-NEXT:    vpkf %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 336(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x double> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
-  ret <16 x i16> %sel
-}
-
-define <16 x i32> @fun140(<16 x double> %val1, <16 x double> %val2, <16 x i32> %val3, <16 x i32> %val4) {
-; CHECK-LABEL: fun140:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v0
-; CHECK-NEXT:    vfchdb %v1, %v24, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 352(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v0
-; CHECK-NEXT:    vfchdb %v1, %v28, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 368(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 384(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x double> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i32> %val3, <16 x i32> %val4
-  ret <16 x i32> %sel
-}
-
-define <16 x i64> @fun141(<16 x double> %val1, <16 x double> %val2, <16 x i64> %val3, <16 x i64> %val4) {
-; CHECK-LABEL: fun141:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vl %v1, 416(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v24, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v0
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vl %v1, 448(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v0
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 224(%r15)
-; CHECK-NEXT:    vl %v1, 480(%r15)
-; CHECK-NEXT:    vl %v2, 352(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v25, %v0
-; CHECK-NEXT:    vsel %v25, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 496(%r15)
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v29, %v0
-; CHECK-NEXT:    vl %v1, 512(%r15)
-; CHECK-NEXT:    vl %v2, 384(%r15)
-; CHECK-NEXT:    vsel %v29, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vl %v1, 528(%r15)
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x double> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x i64> %val3, <16 x i64> %val4
-  ret <16 x i64> %sel
-}
-
-define <16 x float> @fun142(<16 x double> %val1, <16 x double> %val2, <16 x float> %val3, <16 x float> %val4) {
-; CHECK-LABEL: fun142:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 160(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v0
-; CHECK-NEXT:    vfchdb %v1, %v24, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 352(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 192(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v0
-; CHECK-NEXT:    vfchdb %v1, %v28, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 368(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 224(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vfchdb %v1, %v25, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 384(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vl %v1, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vfchdb %v1, %v29, %v1
-; CHECK-NEXT:    vpkg %v0, %v1, %v0
-; CHECK-NEXT:    vl %v1, 400(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x double> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x float> %val3, <16 x float> %val4
-  ret <16 x float> %sel
-}
-
-define <16 x double> @fun143(<16 x double> %val1, <16 x double> %val2, <16 x double> %val3, <16 x double> %val4) {
-; CHECK-LABEL: fun143:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    vl %v0, 160(%r15)
-; CHECK-NEXT:    vl %v1, 416(%r15)
-; CHECK-NEXT:    vl %v2, 288(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v24, %v0
-; CHECK-NEXT:    vsel %v24, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 176(%r15)
-; CHECK-NEXT:    vl %v1, 432(%r15)
-; CHECK-NEXT:    vl %v2, 304(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v26, %v0
-; CHECK-NEXT:    vsel %v26, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 192(%r15)
-; CHECK-NEXT:    vl %v1, 448(%r15)
-; CHECK-NEXT:    vl %v2, 320(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v28, %v0
-; CHECK-NEXT:    vsel %v28, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 208(%r15)
-; CHECK-NEXT:    vl %v1, 464(%r15)
-; CHECK-NEXT:    vl %v2, 336(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v30, %v0
-; CHECK-NEXT:    vsel %v30, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 224(%r15)
-; CHECK-NEXT:    vl %v1, 480(%r15)
-; CHECK-NEXT:    vl %v2, 352(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v25, %v0
-; CHECK-NEXT:    vsel %v25, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 240(%r15)
-; CHECK-NEXT:    vl %v1, 496(%r15)
-; CHECK-NEXT:    vl %v2, 368(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v27, %v0
-; CHECK-NEXT:    vsel %v27, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 256(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v29, %v0
-; CHECK-NEXT:    vl %v1, 512(%r15)
-; CHECK-NEXT:    vl %v2, 384(%r15)
-; CHECK-NEXT:    vsel %v29, %v2, %v1, %v0
-; CHECK-NEXT:    vl %v0, 272(%r15)
-; CHECK-NEXT:    vfchdb %v0, %v31, %v0
-; CHECK-NEXT:    vl %v1, 528(%r15)
-; CHECK-NEXT:    vl %v2, 400(%r15)
-; CHECK-NEXT:    vsel %v31, %v2, %v1, %v0
-; CHECK-NEXT:    br %r14
-  %cmp = fcmp ogt <16 x double> %val1, %val2
-  %sel = select <16 x i1> %cmp, <16 x double> %val3, <16 x double> %val4
-  ret <16 x double> %sel
-}
-

test/CodeGen/SystemZ/vec-div-01.ll

 ; Test vector division.  There is no native integer support for this,
 ; so the integer cases are really a test of the operation legalization code.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test a v16i8 division.
 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
 ; CHECK-LABEL: f1:
 ; CHECK: vlvgp [[REG:%v[0-9]+]],
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 10
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 11
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 12
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 13
-; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 14
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 0
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 2
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 3
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 4
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 5
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 6
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 8
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 9
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 10
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 11
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 12
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 13
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 14
 ; CHECK: br %r14
   %ret = sdiv <16 x i8> %val1, %val2
   ret <16 x i8> %ret
 }
 
 ; Test a v8i16 division.
 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
 ; CHECK-LABEL: f2:
 ; CHECK: vlvgp [[REG:%v[0-9]+]],
-; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 0
-; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 1
-; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 2
-; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 4
-; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 5
-; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 6
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 0
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 1
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 2
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 4
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 5
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 6
 ; CHECK: br %r14
   %ret = sdiv <8 x i16> %val1, %val2
   ret <8 x i16> %ret
 }
 
 ; Test a v4i32 division.
 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
 ; CHECK-LABEL: f3:
 ; CHECK: vlvgp [[REG:%v[0-9]+]],
-; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 0
-; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 2
+; CHECK-DAG: vlvgf [[REG]], {{%r[0-9]+}}, 0
+; CHECK-DAG: vlvgf [[REG]], {{%r[0-9]+}}, 2
 ; CHECK: br %r14
   %ret = sdiv <4 x i32> %val1, %val2
   ret <4 x i32> %ret
 }
 
 ; Test a v2i64 division.
 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
 ; CHECK-LABEL: f4:

test/CodeGen/SystemZ/vec-sub-01.ll

 ; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
 ; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
 ; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v[[A1]], 1
 ; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v[[A2]], 1
 ; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v[[A1]], 2
 ; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2
 ; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3
 ; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3
-; CHECK-DAG: ldr %f[[A1copy:[0-5]]], %f[[A1]]
-; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]]
+; CHECK-DAG: sebr %f[[A1]], %f[[A2]]
 ; CHECK-DAG: sebr %f[[B1]], %f[[B2]]
 ; CHECK-DAG: sebr %f[[C1]], %f[[C2]]
 ; CHECK-DAG: sebr %f[[D1]], %f[[D2]]
-; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1copy]], %v[[B1]]
+; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1]], %v[[B1]]
 ; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]]
 ; CHECK: vmrhg %v24, [[HIGH]], [[LOW]]
 ; CHECK: br %r14
   %ret = fsub <4 x float> %val1, %val2
   ret <4 x float> %ret
 }
 
 ; Test a v2f64 subtraction.