[MiSched|TableGen] : Tidy up and modernise. NFC.

[javed.absar]

Summary

Replacing with range-based loop and substituting 'using'.
I had to choose a lot of element-names and some choices may not be so great, so am looking for suggestions for better ones.

[MatzeB]

LGTM with nitpicks.

utils/TableGen/CodeGenSchedule.cpp

165 ↗

(On Diff #114850)

Seeing that the list is called ProcRecords I would expect a single element being called ProcRecord.

206 ↗

(On Diff #114850)

Variant instead of SVDef?

300–301 ↗

(On Diff #114850)

remove the comments

464–465 ↗

(On Diff #114850)

remove the comments

1825 ↗

(On Diff #114850)

call the variable Transition?

llvm/trunk/utils/TableGen/CodeGenSchedule.h

 #include "llvm/TableGen/SetTheory.h"
 
 namespace llvm {
 
 class CodeGenTarget;
 class CodeGenSchedModels;
 class CodeGenInstruction;
 
-typedef std::vector<Record*> RecVec;
-typedef std::vector<Record*>::const_iterator RecIter;
+using RecVec = std::vector<Record*>;
+using RecIter = std::vector<Record*>::const_iterator;
 
-typedef std::vector<unsigned> IdxVec;
-typedef std::vector<unsigned>::const_iterator IdxIter;
+using IdxVec = std::vector<unsigned>;
+using IdxIter = std::vector<unsigned>::const_iterator;
 
 void splitSchedReadWrites(const RecVec &RWDefs,
                           RecVec &WriteDefs, RecVec &ReadDefs);
 
 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
 /// sequences.  TheDef is nonnull for explicit SchedWrites, but Sequence may or
 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
 /// be nonempty.
class CodeGenSchedModels {
 
   // Map dag expressions to Instruction lists.
   SetTheory Sets;
 
   // List of unique processor models.
   std::vector<CodeGenProcModel> ProcModels;
 
   // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
-  typedef DenseMap<Record*, unsigned> ProcModelMapTy;
+  using ProcModelMapTy = DenseMap<Record*, unsigned>;
   ProcModelMapTy ProcModelMap;
 
   // Per-operand SchedReadWrite types.
   std::vector<CodeGenSchedRW> SchedWrites;
   std::vector<CodeGenSchedRW> SchedReads;
 
   // List of unique SchedClasses.
   std::vector<CodeGenSchedClass> SchedClasses;
 
   // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
   unsigned NumInstrSchedClasses;
 
   RecVec ProcResourceDefs;
   RecVec ProcResGroups;
 
   // Map each instruction to its unique SchedClass index considering the
   // combination of it's itinerary class, SchedRW list, and InstRW records.
-  typedef DenseMap<Record*, unsigned> InstClassMapTy;
+  using InstClassMapTy = DenseMap<Record*, unsigned>;
   InstClassMapTy InstrClassMap;
 
 public:
   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
 
   // iterator access to the scheduling classes.
-  typedef std::vector<CodeGenSchedClass>::iterator class_iterator;
-  typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator;
+  using class_iterator = std::vector<CodeGenSchedClass>::iterator;
+  using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
   class_iterator classes_begin() { return SchedClasses.begin(); }
   const_class_iterator classes_begin() const { return SchedClasses.begin(); }
   class_iterator classes_end() { return SchedClasses.end(); }
   const_class_iterator classes_end() const { return SchedClasses.end(); }
   iterator_range<class_iterator> classes() {
    return make_range(classes_begin(), classes_end());
   }
   iterator_range<const_class_iterator> classes() const {
CodeGenProcModel &getProcModel(Record *ModelDef) {
     assert(I != ProcModelMap.end() && "missing machine model");
     return ProcModels[I->second];
   }
   const CodeGenProcModel &getProcModel(Record *ModelDef) const {
     return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
   }
 
   // Iterate over the unique processor models.
-  typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
+  using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
   ProcIter procModelBegin() const { return ProcModels.begin(); }
   ProcIter procModelEnd() const { return ProcModels.end(); }
   ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
 
   // Return true if any processors have itineraries.
   bool hasItineraries() const;
 
   // Get a SchedWrite from its index.
const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
     return SchedClasses[Idx];
   }
 
   // Get the SchedClass index for an instruction. Instructions with no
   // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
   // for NoItinerary.
   unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
 
-  typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
+  using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
   SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
   SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
   ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
 
   unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
 
   void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
   void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;

llvm/trunk/utils/TableGen/CodeGenSchedule.cpp

void CodeGenSchedModels::collectProcModels() {
   // Use idx=0 for NoModel/NoItineraries.
   Record *NoModelDef = Records.getDef("NoSchedModel");
   Record *NoItinsDef = Records.getDef("NoItineraries");
   ProcModels.emplace_back(0, "NoSchedModel", NoModelDef, NoItinsDef);
   ProcModelMap[NoModelDef] = 0;
 
   // For each processor, find a unique machine model.
   DEBUG(dbgs() << "+++ PROCESSOR MODELs (addProcModel) +++\n");
-  for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i)
-    addProcModel(ProcRecords[i]);
+  for (Record *ProcRecord : ProcRecords)
+    addProcModel(ProcRecord);
 }
 
 /// Get a unique processor model based on the defined MachineModel and
 /// ProcessorItineraries.
 void CodeGenSchedModels::addProcModel(Record *ProcDef) {
   Record *ModelKey = getModelOrItinDef(ProcDef);
   if (!ProcModelMap.insert(std::make_pair(ModelKey, ProcModels.size())).second)
     return;

 }
 
 // Recursively find all reachable SchedReadWrite records.
 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
                         SmallPtrSet<Record*, 16> &RWSet) {
   if (!RWSet.insert(RWDef).second)
     return;
   RWDefs.push_back(RWDef);
-  // Reads don't current have sequence records, but it can be added later.
+  // Reads don't currently have sequence records, but it can be added later.
   if (RWDef->isSubClassOf("WriteSequence")) {
     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
-    for (RecIter I = Seq.begin(), E = Seq.end(); I != E; ++I)
-      scanSchedRW(*I, RWDefs, RWSet);
+    for (Record *WSRec : Seq)
+      scanSchedRW(WSRec, RWDefs, RWSet);
   }
   else if (RWDef->isSubClassOf("SchedVariant")) {
     // Visit each variant (guarded by a different predicate).
     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
-    for (RecIter VI = Vars.begin(), VE = Vars.end(); VI != VE; ++VI) {
+    for (Record *Variant : Vars) {
       // Visit each RW in the sequence selected by the current variant.
-      RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
-      for (RecIter I = Selected.begin(), E = Selected.end(); I != E; ++I)
-        scanSchedRW(*I, RWDefs, RWSet);
+      RecVec Selected = Variant->getValueAsListOfDefs("Selected");
+      for (Record *SelDef : Selected)
+        scanSchedRW(SelDef, RWDefs, RWSet);
     }
   }
 }
 
 // Collect and sort all SchedReadWrites reachable via tablegen records.
 // More may be inferred later when inferring new SchedClasses from variants.
 void CodeGenSchedModels::collectSchedRW() {
   // Reserve idx=0 for invalid writes/reads.
   SchedWrites.resize(1);
   SchedReads.resize(1);
 
   SmallPtrSet<Record*, 16> RWSet;
 
   // Find all SchedReadWrites referenced by instruction defs.
   RecVec SWDefs, SRDefs;
   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
     Record *SchedDef = Inst->TheDef;
     if (SchedDef->isValueUnset("SchedRW"))
       continue;
     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
-    for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) {
-      if ((*RWI)->isSubClassOf("SchedWrite"))
-        scanSchedRW(*RWI, SWDefs, RWSet);
+    for (Record *RW : RWs) {
+      if (RW->isSubClassOf("SchedWrite"))
+        scanSchedRW(RW, SWDefs, RWSet);
       else {
-        assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
-        scanSchedRW(*RWI, SRDefs, RWSet);
+        assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
+        scanSchedRW(RW, SRDefs, RWSet);
       }
     }
   }
   // Find all ReadWrites referenced by InstRW.
   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
-  for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI) {
+  for (Record *InstRWDef : InstRWDefs) {
     // For all OperandReadWrites.
-    RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
-    for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
-         RWI != RWE; ++RWI) {
-      if ((*RWI)->isSubClassOf("SchedWrite"))
-        scanSchedRW(*RWI, SWDefs, RWSet);
+    RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");
+    for (Record *RWDef : RWDefs) {
+      if (RWDef->isSubClassOf("SchedWrite"))
+        scanSchedRW(RWDef, SWDefs, RWSet);
       else {
-        assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
-        scanSchedRW(*RWI, SRDefs, RWSet);
+        assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
+        scanSchedRW(RWDef, SRDefs, RWSet);
       }
     }
   }
   // Find all ReadWrites referenced by ItinRW.
   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
-  for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {
+  for (Record *ItinRWDef : ItinRWDefs) {
     // For all OperandReadWrites.
-    RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites");
-    for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
-         RWI != RWE; ++RWI) {
-      if ((*RWI)->isSubClassOf("SchedWrite"))
-        scanSchedRW(*RWI, SWDefs, RWSet);
+    RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");
+    for (Record *RWDef : RWDefs) {
+      if (RWDef->isSubClassOf("SchedWrite"))
+        scanSchedRW(RWDef, SWDefs, RWSet);
       else {
-        assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
-        scanSchedRW(*RWI, SRDefs, RWSet);
+        assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
+        scanSchedRW(RWDef, SRDefs, RWSet);
       }
     }
   }
   // Find all ReadWrites referenced by SchedAlias. AliasDefs needs to be sorted
   // for the loop below that initializes Alias vectors.
   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");
   std::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord());
-  for (RecIter AI = AliasDefs.begin(), AE = AliasDefs.end(); AI != AE; ++AI) {
-    Record *MatchDef = (*AI)->getValueAsDef("MatchRW");
-    Record *AliasDef = (*AI)->getValueAsDef("AliasRW");
+  for (Record *ADef : AliasDefs) {
+    Record *MatchDef = ADef->getValueAsDef("MatchRW");
+    Record *AliasDef = ADef->getValueAsDef("AliasRW");
     if (MatchDef->isSubClassOf("SchedWrite")) {
       if (!AliasDef->isSubClassOf("SchedWrite"))
-        PrintFatalError((*AI)->getLoc(), "SchedWrite Alias must be SchedWrite");
+        PrintFatalError(ADef->getLoc(), "SchedWrite Alias must be SchedWrite");
       scanSchedRW(AliasDef, SWDefs, RWSet);
     }
     else {
       assert(MatchDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
       if (!AliasDef->isSubClassOf("SchedRead"))
-        PrintFatalError((*AI)->getLoc(), "SchedRead Alias must be SchedRead");
+        PrintFatalError(ADef->getLoc(), "SchedRead Alias must be SchedRead");
       scanSchedRW(AliasDef, SRDefs, RWSet);
     }
   }
   // Sort and add the SchedReadWrites directly referenced by instructions or
   // itinerary resources. Index reads and writes in separate domains.
   std::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
-  for (RecIter SWI = SWDefs.begin(), SWE = SWDefs.end(); SWI != SWE; ++SWI) {
-    assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
-    SchedWrites.emplace_back(SchedWrites.size(), *SWI);
+  for (Record *SWDef : SWDefs) {
+    assert(!getSchedRWIdx(SWDef, /*IsRead=*/false) && "duplicate SchedWrite");
+    SchedWrites.emplace_back(SchedWrites.size(), SWDef);
   }
   std::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
-  for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) {
-    assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite");
-    SchedReads.emplace_back(SchedReads.size(), *SRI);
+  for (Record *SRDef : SRDefs) {
+    assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite");
+    SchedReads.emplace_back(SchedReads.size(), SRDef);
   }
   // Initialize WriteSequence vectors.
-  for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
-         WE = SchedWrites.end(); WI != WE; ++WI) {
-    if (!WI->IsSequence)
+  for (CodeGenSchedRW &CGRW : SchedWrites) {
+    if (!CGRW.IsSequence)
       continue;
-    findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
+    findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
             /*IsRead=*/false);
   }
   // Initialize Aliases vectors.
-  for (RecIter AI = AliasDefs.begin(), AE = AliasDefs.end(); AI != AE; ++AI) {
-    Record *AliasDef = (*AI)->getValueAsDef("AliasRW");
+  for (Record *ADef : AliasDefs) {
+    Record *AliasDef = ADef->getValueAsDef("AliasRW");
     getSchedRW(AliasDef).IsAlias = true;
-    Record *MatchDef = (*AI)->getValueAsDef("MatchRW");
+    Record *MatchDef = ADef->getValueAsDef("MatchRW");
     CodeGenSchedRW &RW = getSchedRW(MatchDef);
     if (RW.IsAlias)
-      PrintFatalError((*AI)->getLoc(), "Cannot Alias an Alias");
-    RW.Aliases.push_back(*AI);
+      PrintFatalError(ADef->getLoc(), "Cannot Alias an Alias");
+    RW.Aliases.push_back(ADef);
   }
   DEBUG(
     dbgs() << "\n+++ SCHED READS and WRITES (collectSchedRW) +++\n";
     for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) {
       dbgs() << WIdx << ": ";
       SchedWrites[WIdx].dump();
       dbgs() << '\n';
     }
     for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; ++RIdx) {
       dbgs() << RIdx << ": ";
       SchedReads[RIdx].dump();
       dbgs() << '\n';
     }
     RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");
-    for (RecIter RI = RWDefs.begin(), RE = RWDefs.end();
-         RI != RE; ++RI) {
-      if (!getSchedRWIdx(*RI, (*RI)->isSubClassOf("SchedRead"))) {
-        const std::string &Name = (*RI)->getName();
+    for (Record *RWDef : RWDefs) {
+      if (!getSchedRWIdx(RWDef, RWDef->isSubClassOf("SchedRead"))) {
+        const std::string &Name = RWDef->getName();
         if (Name != "NoWrite" && Name != "ReadDefault")
-          dbgs() << "Unused SchedReadWrite " << (*RI)->getName() << '\n';
+          dbgs() << "Unused SchedReadWrite " << RWDef->getName() << '\n';
       }
     });
 }
 
 /// Compute a SchedWrite name from a sequence of writes.
 std::string CodeGenSchedModels::genRWName(ArrayRef<unsigned> Seq, bool IsRead) {
   std::string Name("(");
   for (auto I = Seq.begin(), E = Seq.end(); I != E; ++I) {
for (std::vector<CodeGenSchedRW>::const_iterator I = RWVec.begin() + After,
          E = RWVec.end(); I != E; ++I) {
     if (I->TheDef == Def)
       return I - RWVec.begin();
   }
   return 0;
 }
 
 bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
-  for (unsigned i = 0, e = SchedReads.size(); i < e; ++i) {
-    Record *ReadDef = SchedReads[i].TheDef;
+  for (const CodeGenSchedRW &Read : SchedReads) {
+    Record *ReadDef = Read.TheDef;
     if (!ReadDef || !ReadDef->isSubClassOf("ProcReadAdvance"))
       continue;
 
     RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");
     if (is_contained(ValidWrites, WriteDef)) {
       return true;
     }
   }
   return false;
 }
 
 namespace llvm {
 
 void splitSchedReadWrites(const RecVec &RWDefs,
                           RecVec &WriteDefs, RecVec &ReadDefs) {
-  for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
-    if ((*RWI)->isSubClassOf("SchedWrite"))
-      WriteDefs.push_back(*RWI);
+  for (Record *RWDef : RWDefs) {
+    if (RWDef->isSubClassOf("SchedWrite"))
+      WriteDefs.push_back(RWDef);
     else {
-      assert((*RWI)->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
-      ReadDefs.push_back(*RWI);
+      assert(RWDef->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
+      ReadDefs.push_back(RWDef);
     }
   }
 }
 
 } // end namespace llvm
 
 // Split the SchedReadWrites defs and call findRWs for each list.
 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
                                  IdxVec &Writes, IdxVec &Reads) const {
     RecVec WriteDefs;
     RecVec ReadDefs;
     splitSchedReadWrites(RWDefs, WriteDefs, ReadDefs);
     findRWs(WriteDefs, Writes, false);
     findRWs(ReadDefs, Reads, true);
 }
 
 // Call getSchedRWIdx for all elements in a sequence of SchedRW defs.
 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,
                                  bool IsRead) const {
-  for (RecIter RI = RWDefs.begin(), RE = RWDefs.end(); RI != RE; ++RI) {
-    unsigned Idx = getSchedRWIdx(*RI, IsRead);
+  for (Record *RWDef : RWDefs) {
+    unsigned Idx = getSchedRWIdx(RWDef, IsRead);
     assert(Idx && "failed to collect SchedReadWrite");
     RWs.push_back(Idx);
   }
 }
 
 void CodeGenSchedModels::expandRWSequence(unsigned RWIdx, IdxVec &RWSeq,
                                           bool IsRead) const {
   const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
   if (!SchedRW.IsSequence) {
     RWSeq.push_back(RWIdx);
     return;
   }
   int Repeat =
     SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
   for (int i = 0; i < Repeat; ++i) {
-    for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end();
-         I != E; ++I) {
-      expandRWSequence(*I, RWSeq, IsRead);
+    for (unsigned I : SchedRW.Sequence) {
+      expandRWSequence(I, RWSeq, IsRead);
     }
   }
 }
 
 // Expand a SchedWrite as a sequence following any aliases that coincide with
 // the given processor model.
 void CodeGenSchedModels::expandRWSeqForProc(
   unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
void CodeGenSchedModels::expandRWSeqForProc(
   }
   if (!SchedWrite.IsSequence) {
     RWSeq.push_back(RWIdx);
     return;
   }
   int Repeat =
     SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1;
   for (int i = 0; i < Repeat; ++i) {
-    for (IdxIter I = SchedWrite.Sequence.begin(), E = SchedWrite.Sequence.end();
-         I != E; ++I) {
-      expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
+    for (unsigned I : SchedWrite.Sequence) {
+      expandRWSeqForProc(I, RWSeq, IsRead, ProcModel);
     }
   }
 }
 
 // Find the existing SchedWrite that models this sequence of writes.
 unsigned CodeGenSchedModels::findRWForSequence(ArrayRef<unsigned> Seq,
                                                bool IsRead) {
   std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
 
     unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
     InstrClassMap[Inst->TheDef] = SCIdx;
   }
   // Create classes for InstRW defs.
   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
   std::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
   DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n");
-  for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI)
-    createInstRWClass(*OI);
+  for (Record *RWDef : InstRWDefs)
+    createInstRWClass(RWDef);
 
   NumInstrSchedClasses = SchedClasses.size();
 
   bool EnableDump = false;
   DEBUG(EnableDump = true);
   if (!EnableDump)
     return;
 
if (!SC.Writes.empty()) {
       dbgs() << "SchedRW machine model for " << InstName;
       for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI)
         dbgs() << " " << SchedWrites[*WI].Name;
       for (IdxIter RI = SC.Reads.begin(), RE = SC.Reads.end(); RI != RE; ++RI)
         dbgs() << " " << SchedReads[*RI].Name;
       dbgs() << '\n';
     }
     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
-    for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
-         RWI != RWE; ++RWI) {
+    for (Record *RWDef : RWDefs) {
       const CodeGenProcModel &ProcModel =
-        getProcModel((*RWI)->getValueAsDef("SchedModel"));
+        getProcModel(RWDef->getValueAsDef("SchedModel"));
       ProcIndices.push_back(ProcModel.Index);
       dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
       IdxVec Writes;
       IdxVec Reads;
-      findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),
+      findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
               Writes, Reads);
-      for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
-        dbgs() << " " << SchedWrites[*WI].Name;
-      for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
-        dbgs() << " " << SchedReads[*RI].Name;
+      for (unsigned WIdx : Writes)
+        dbgs() << " " << SchedWrites[WIdx].Name;
+      for (unsigned RIdx : Reads)
+        dbgs() << " " << SchedReads[RIdx].Name;
       dbgs() << '\n';
     }
     // If ProcIndices contains zero, the class applies to all processors.
     if (!std::count(ProcIndices.begin(), ProcIndices.end(), 0)) {
       for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
              PE = ProcModels.end(); PI != PE; ++PI) {
         if (!std::count(ProcIndices.begin(), ProcIndices.end(), PI->Index))
           dbgs() << "No machine model for " << Inst->TheDef->getName()
for (; CIdx != CEnd; ++CIdx) {
     ArrayRef<Record*> InstDefs = ClassInstrs[CIdx].second;
     // If the all instrs in the current class are accounted for, then leave
     // them mapped to their old class.
     if (OldSCIdx) {
       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
       if (!RWDefs.empty()) {
         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
         unsigned OrigNumInstrs = 0;
-        for (RecIter I = OrigInstDefs->begin(), E = OrigInstDefs->end();
-             I != E; ++I) {
-          if (InstrClassMap[*I] == OldSCIdx)
+        for (Record *OIDef : make_range(OrigInstDefs->begin(), OrigInstDefs->end())) {
+          if (InstrClassMap[OIDef] == OldSCIdx)
             ++OrigNumInstrs;
         }
         if (OrigNumInstrs == InstDefs.size()) {
           assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
                  "expected a generic SchedClass");
           DEBUG(dbgs() << "InstRW: Reuse SC " << OldSCIdx << ":"
                 << SchedClasses[OldSCIdx].Name << " on "
                 << InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
for (ArrayRef<Record*>::const_iterator
       InstrClassMap[*II] = SCIdx;
     }
     SC.InstRWs.push_back(InstRWDef);
   }
 }
 
 // True if collectProcItins found anything.
 bool CodeGenSchedModels::hasItineraries() const {
-  for (CodeGenSchedModels::ProcIter PI = procModelBegin(), PE = procModelEnd();
-       PI != PE; ++PI) {
-    if (PI->hasItineraries())
+  for (const CodeGenProcModel &PM : make_range(procModelBegin(),procModelEnd())) {
+    if (PM.hasItineraries())
       return true;
   }
   return false;
 }
 
 // Gather the processor itineraries.
 void CodeGenSchedModels::collectProcItins() {
   DEBUG(dbgs() << "\n+++ PROBLEM ITINERARIES (collectProcItins) +++\n");
Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
                                              const CodeGenProcModel &PM) const {
   if (ProcResKind->isSubClassOf("ProcResourceUnits"))
     return ProcResKind;
 
   Record *ProcUnitDef = nullptr;
   assert(!ProcResourceDefs.empty());
   assert(!ProcResGroups.empty());
 
-  for (RecIter RI = ProcResourceDefs.begin(), RE = ProcResourceDefs.end();
-       RI != RE; ++RI) {
-
-    if ((*RI)->getValueAsDef("Kind") == ProcResKind
-        && (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
+  for (Record *ProcResDef : ProcResourceDefs) {
+    if (ProcResDef->getValueAsDef("Kind") == ProcResKind
+        && ProcResDef->getValueAsDef("SchedModel") == PM.ModelDef) {
       if (ProcUnitDef) {
-        PrintFatalError((*RI)->getLoc(),
+        PrintFatalError(ProcResDef->getLoc(),
                         "Multiple ProcessorResourceUnits associated with "
                         + ProcResKind->getName());
       }
-      ProcUnitDef = *RI;
+      ProcUnitDef = ProcResDef;
     }
   }
-  for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end();
-       RI != RE; ++RI) {
-
-    if (*RI == ProcResKind
-        && (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
+  for (Record *ProcResGroup : ProcResGroups) {
+    if (ProcResGroup == ProcResKind
+        && ProcResGroup->getValueAsDef("SchedModel") == PM.ModelDef) {
       if (ProcUnitDef) {
-        PrintFatalError((*RI)->getLoc(),
+        PrintFatalError((ProcResGroup)->getLoc(),
                         "Multiple ProcessorResourceUnits associated with "
                         + ProcResKind->getName());
       }
-      ProcUnitDef = *RI;
+      ProcUnitDef = ProcResGroup;
     }
   }
   if (!ProcUnitDef) {
     PrintFatalError(ProcResKind->getLoc(),
                     "No ProcessorResources associated with "
                     + ProcResKind->getName());
   }
   return ProcUnitDef;
for (unsigned i = 0, N = Reads.size(); i < N; ++i) {
     if (i < N-1) {
       dbgs() << '\n';
       dbgs().indent(10);
     }
   }
   dbgs() << "\n  ProcIdx: "; dumpIdxVec(ProcIndices); dbgs() << '\n';
   if (!Transitions.empty()) {
     dbgs() << "\n Transitions for Proc ";
-    for (std::vector<CodeGenSchedTransition>::const_iterator
-           TI = Transitions.begin(), TE = Transitions.end(); TI != TE; ++TI) {
-      dumpIdxVec(TI->ProcIndices);
+    for (const CodeGenSchedTransition &Transition : Transitions) {
+      dumpIdxVec(Transition.ProcIndices);
     }
   }
 }
 
 void PredTransitions::dump() const {
   dbgs() << "Expanded Variants:\n";
   for (std::vector<PredTransition>::const_iterator
          TI = TransVec.begin(), TE = TransVec.end(); TI != TE; ++TI) {