[X86][LLVM][TD] Arranging Atom family in an inheritance ratio

[m_zuckerman]

Summary

X86.td file contains number of features that can be arrange in more general pattern . We can combine features that include in number of atom into single processor and create a inheritance ratio between them all.

[craig.topper]

lib/Target/X86/X86.td

428–443

This looks to be adding RDRAND to SLM. Whether that's correct or not, that's a functional change which should not be part of this patch.

437

Should SSSE3 be part of AtomValues instead? The rest of these are uarch details, but that one is a real feature and should be with the other features.

[m_zuckerman]

lib/Target/X86/X86.td

428–443

hi.
First, this feature is part of SLM.
Secondly , why don't you want it as part of the patch ?

437

Higher features hint for lower features. In this case feature SSSE3 is part of the SSE42 so i didn't want to create a duplication.

[craig.topper]

lib/Target/X86/X86.td

428–443

I agree that it's part of SLM and that it should be fixed. But this patch should be treated as a refactor that doesn't change behavior. Especially since your description makes no mention of this change. And clang needs to be updated too. So submit a separate pre or post patch for the SLM rdrand change.

[m_zuckerman]

I returned the RDRAND into the Goldmont and I will fix it later in another patch.

[craig.topper]

lib/Target/X86/X86.td

415

Why is CallRegIndirect in BonnellProc and AtomPlusFeatures? Should it be in AtomFeatures instead? Or should each CPU list is separately?

417

I don't think the "Slow" features should be part of AtomPlusFeatures. While its great for sharing between Silvermont and Goldmont. It makes AtomPlusFeatures hard to inherit from for the processor after Goldmont if it changes any of those things.

lib/Target/X86/X86.td

def : ProcessorModel<"core2", SandyBridgeModel, [
   FeatureSlowUAMem16,
   FeatureMMX,
   FeatureSSSE3,
   FeatureFXSR,
   FeatureCMPXCHG16B,
   FeatureSlowBTMem,
   FeatureLAHFSAHF
 ]>;
+
 def : ProcessorModel<"penryn", SandyBridgeModel, [
   FeatureX87,
   FeatureSlowUAMem16,
   FeatureMMX,
   FeatureSSE41,
   FeatureFXSR,
   FeatureCMPXCHG16B,
   FeatureSlowBTMem,
   FeatureLAHFSAHF
 ]>;
 
-// Atom CPUs.
-class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
-  ProcIntelAtom,
+class ProcessorFeatures<list<SubtargetFeature> Inherited,
+                        list<SubtargetFeature> NewFeatures> {
+  list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
+}
+
+class ProcModel<string Name, SchedMachineModel Model,
+                list<SubtargetFeature> ProcFeatures,
+                list<SubtargetFeature> OtherFeatures> :
+  ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
+
+def AtomFeatures : ProcessorFeatures<[], [
   FeatureX87,
-  FeatureSlowUAMem16,
   FeatureMMX,
-  FeatureSSSE3,
   FeatureFXSR,
   FeatureCMPXCHG16B,
   FeatureMOVBE,
-  FeatureSlowBTMem,
-  FeatureLEAForSP,
-  FeatureSlowDivide32,
-  FeatureSlowDivide64,
-  FeatureCallRegIndirect,
-  FeatureLEAUsesAG,
-  FeaturePadShortFunctions,
   FeatureLAHFSAHF
 ]>;
-def : BonnellProc<"bonnell">;
-def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 
-class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
-  ProcIntelSLM,
-  FeatureX87,
-  FeatureMMX,
+def AtomPlusFeatures : ProcessorFeatures<AtomFeatures.Value, [
   FeatureSSE42,
-  FeatureFXSR,
-  FeatureCMPXCHG16B,
-  FeatureMOVBE,
   FeaturePOPCNT,
   FeaturePCLMUL,
   FeatureAES,
-  FeatureSlowDivide64,
   FeatureCallRegIndirect,
   FeaturePRFCHW,
   FeatureSlowLEA,
   FeatureSlowIncDec,
+  FeatureSlowBTMem
+]>;
+
+// Atom CPUs.
+class BonnellProc<string Name> : ProcModel<Name, AtomModel,
+             AtomFeatures.Value, [
+  ProcIntelAtom,
+  FeatureSlowUAMem16,
+  FeatureSSSE3,
   FeatureSlowBTMem,
-  FeatureSlowPMULLD,
-  FeatureLAHFSAHF
+  FeatureLEAForSP,
+  FeatureSlowDivide32,
+  FeatureSlowDivide64,
+  FeatureCallRegIndirect,
+  FeatureLEAUsesAG,
+  FeaturePadShortFunctions
+]>;
+def : BonnellProc<"bonnell">;
+def : BonnellProc<"atom">; // Pin the generic name to the baseline.
+
+class SilvermontProc<string Name> : ProcModel<Name, SLMModel,
+                                              AtomPlusFeatures.Value,[
+  ProcIntelSLM,
+  FeatureSlowDivide64,
+  FeatureSlowPMULLD
 ]>;
 def : SilvermontProc<"silvermont">;
 def : SilvermontProc<"slm">; // Legacy alias.
 
-class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
+class GoldmontProc<string Name> : ProcModel<Name, SLMModel,
+                                            AtomPlusFeatures.Value,[
   ProcIntelGLM,
-  FeatureX87,
-  FeatureMMX,
-  FeatureSSE42,
-  FeatureFXSR,
-  FeatureCMPXCHG16B,
-  FeatureMOVBE,
-  FeaturePOPCNT,
-  FeaturePCLMUL,
-  FeatureAES,
-  FeaturePRFCHW,
-  FeatureCallRegIndirect,
-  FeatureSlowLEA,
-  FeatureSlowIncDec,
-  FeatureSlowBTMem,
-  FeatureLAHFSAHF,
   FeatureMPX,
   FeatureSHA,
   FeatureRDRAND,
   FeatureRDSEED,
   FeatureXSAVE,
   FeatureXSAVEOPT,
   FeatureXSAVEC,
   FeatureXSAVES,
class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
   FeatureSlowBTMem,
   FeaturePOPCNT,
   FeatureAES,
   FeaturePCLMUL,
   FeatureLAHFSAHF
 ]>;
 def : WestmereProc<"westmere">;
 
-class ProcessorFeatures<list<SubtargetFeature> Inherited,
-                        list<SubtargetFeature> NewFeatures> {
-  list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
-}
 
-class ProcModel<string Name, SchedMachineModel Model,
-                list<SubtargetFeature> ProcFeatures,
-                list<SubtargetFeature> OtherFeatures> :
-  ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 
 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 // rather than a superset.
 def SNBFeatures : ProcessorFeatures<[], [
   FeatureX87,
   FeatureMMX,
   FeatureAVX,
   FeatureFXSR,