RenameIndependentSubregs: Fix iterator problem

[arsenm]

Summary

Fixes bug 33597.

Use of substituteRegister in the tied operand case messes
up the register use iterator, causing some uses to be left
unprocessed.

[MatzeB]

Thanks, LGTM!

[arsenm]

r306333

lib/CodeGen/RenameIndependentSubregs.cpp

for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
     }
 
     unsigned VReg = Intervals[ID]->reg;
     MO.setReg(VReg);
     if (MO.isTied()) {
       /// Undef use operands are not tracked in the equivalence class but need
       /// to be update if they are tied.
       MO.getParent()->substituteRegister(Reg, VReg, 0, TRI);
+
+      // substituteRegister breaks the iterator, so restart.
+      I = MRI->reg_nodbg_begin(Reg);
     }
   }
   // TODO: We could attempt to recompute new register classes while visiting
   // the operands: Some of the split register may be fine with less constraint
   // classes than the original vreg.
 }
 
 void RenameIndependentSubregs::distribute(const IntEqClasses &Classes,

test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir

bb.3:
     %14 = COPY %1.sub1
     %16 = COPY killed %1.sub0
     undef %15.sub0 = COPY killed %16
     %15.sub1 = COPY killed %14
     FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, implicit %exec, implicit %flat_scr
     S_ENDPGM
 
 ...
+---
+# Make sure others uses after the mac are properly handled and not
+# left unreplaced due to iterator issues from substituteRegister.
+
+# GCN-LABEL: name: vreg_does_not_dominate
+
+# GCN: undef %8.sub1 = V_MAC_F32_e32 undef %2, undef %1, undef %8.sub1, implicit %exec
+# GCN: undef %7.sub0 = V_MOV_B32_e32 0, implicit %exec
+# GCN: undef %9.sub2 = COPY %7.sub0
+
+# GCN: undef %6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit %exec
+# GCN: undef %7.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit %exec
+# GCN: %8.sub1 = V_ADD_F32_e32 %8.sub1, %8.sub1, implicit %exec
+
+# GCN: BUFFER_STORE_DWORD_OFFEN %6.sub3, %0,
+# GCN: BUFFER_STORE_DWORD_OFFEN %9.sub2, %0,
+# GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,
+# GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0,
+name:            vreg_does_not_dominate
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '' }
+  - { id: 3, class: vgpr_32, preferred-register: '' }
+  - { id: 4, class: vgpr_32, preferred-register: '' }
+  - { id: 5, class: sreg_64, preferred-register: '' }
+  - { id: 6, class: vreg_128, preferred-register: '' }
+liveins:
+  - { reg: '%vgpr0', virtual-reg: '%0' }
+  - { reg: '%sgpr30_sgpr31', virtual-reg: '%5' }
+body:             |
+  bb.0:
+    successors: %bb.2, %bb.1
+    liveins: %vgpr0, %sgpr30_sgpr31, %sgpr5
+
+    %5 = COPY %sgpr30_sgpr31
+    %0 = COPY %vgpr0
+    undef %6.sub1 = V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit %exec
+    %6.sub0 = V_MOV_B32_e32 0, implicit %exec
+    %6.sub2 = COPY %6.sub0
+    S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
+    S_BRANCH %bb.1
+
+  bb.1:
+    successors: %bb.2
+
+    %6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit %exec
+    %6.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit %exec
+    %6.sub1 = V_ADD_F32_e32 %6.sub1, %6.sub1, implicit %exec
+    %6.sub2 = COPY %6.sub0
+
+  bb.2:
+    BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 12, 0, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 8, 0, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 4, 0, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
+    %sgpr30_sgpr31 = COPY %5
+    %sgpr5 = COPY %sgpr5
+    S_SETPC_B64_return %sgpr30_sgpr31, implicit %sgpr5
+
+...