Keep NDEBUG out of header

[jaykang10]

Summary

Keep NDEBUG out of header in order to build llvm with cmake option -DCMAKE_CXX_FLAGS:STRING="-DLLVM_ENABLE_DUMP" -DCMAKE_BUILD_TYPE=RelWithDebInfo.

[mehdi_amini]

include/llvm/MC/MCSchedule.h

29

I don't understand this change.
We don't want to increase the runtime memory consumption when not needed. This should still be compiled out in release build.

[jaykang10]

include/llvm/MC/MCSchedule.h

29

Sorry Mehdi. I know what you mean. In order to remove the "#ifndef NDEBUG" on dumpuses, we also need to remove it here. This patch's goal is to build llvm with cmake option -DCMAKE_CXX_FLAGS:STRING="-DLLVM_ENABLE_DUMP" -DCMAKE_BUILD_TYPE=RelWithDebInfo. First time, I suggested to add "|| defined(LLVM_ENABLE_DUMP)" with "#ifndef NDEBUG" to achieve the goal but I understand what Matthias want. I am not sure how I can satisfy you guys. If possible, can you suggest idea please? I will be very happy with it.

[MatzeB]

include/llvm/MC/MCSchedule.h

29

This is a case where the dumping code seems to be dependent on !NDEBUG code. You could solve this by tweaking the SchedBoundary::dumpScheduledState() implementation instead. (Like for example not calling getResourceName() with NDEBUG enabled).

[jaykang10]

include/llvm/MC/MCSchedule.h

29

I appreciate you guys comments. This issue is related to http://bugs.llvm.org/show_bug.cgi?id=32283. I think Chris will manage it overall. If possible, I would like to close this review.

include/llvm/CodeGen/MachineRegisterInfo.h

public:
   MachineInstr *getUniqueVRegDef(unsigned Reg) const;
 
   /// clearKillFlags - Iterate over all the uses of the given register and
   /// clear the kill flag from the MachineOperand. This function is used by
   /// optimization passes which extend register lifetimes and need only
   /// preserve conservative kill flag information.
   void clearKillFlags(unsigned Reg) const;
 
-#ifndef NDEBUG
   void dumpUses(unsigned RegNo) const;
-#endif
 
   /// Returns true if PhysReg is unallocatable and constant throughout the
   /// function. Writing to a constant register has no effect.
   bool isConstantPhysReg(unsigned PhysReg) const;
 
   /// Get an iterator over the pressure sets affected by the given physical or
   /// virtual register. If RegUnit is physical, it must be a register unit (from
   /// MCRegUnitIterator).

include/llvm/CodeGen/MachineScheduler.h

public:
 
   void removeReady(SUnit *SU);
 
   /// Call this before applying any other heuristics to the Available queue.
   /// Updates the Available/Pending Q's if necessary and returns the single
   /// available instruction, or NULL if there are multiple candidates.
   SUnit *pickOnlyChoice();
 
-#ifndef NDEBUG
   void dumpScheduledState();
-#endif
 };
 
 /// Base class for GenericScheduler. This class maintains information about
 /// scheduling candidates based on TargetSchedModel making it easy to implement
 /// heuristics for either preRA or postRA scheduling.
 class GenericSchedulerBase : public MachineSchedStrategy {
 public:
   /// Represent the type of SchedCandidate found within a single queue.

include/llvm/CodeGen/TargetSchedule.h

unsigned getNumProcResourceKinds() const {
     return SchedModel.getNumProcResourceKinds();
   }
 
   /// \brief Get a processor resource by ID for convenience.
   const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
     return SchedModel.getProcResource(PIdx);
   }
 
-#ifndef NDEBUG
   const char *getResourceName(unsigned PIdx) const {
     if (!PIdx)
       return "MOps";
     return SchedModel.getProcResource(PIdx)->Name;
   }
-#endif
 
   typedef const MCWriteProcResEntry *ProcResIter;
 
   // \brief Get an iterator into the processor resources consumed by this
   // scheduling class.
   ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
     // The subtarget holds a single resource table for all processors.
     return STI->getWriteProcResBegin(SC);

include/llvm/MC/MCSchedule.h

 #include <cassert>
 
 namespace llvm {
 
 struct InstrItinerary;
 
 /// Define a kind of processor resource that will be modeled by the scheduler.
 struct MCProcResourceDesc {
-#ifndef NDEBUG
   const char *Name;
-#endif
   unsigned NumUnits; // Number of resource of this kind
   unsigned SuperIdx; // Index of the resources kind that contains this kind.
 
   // Number of resources that may be buffered.
   //
   // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
   // cycle after dispatch. This should be used for out-of-order cpus when
   // instructions that use this resource can be buffered in a reservaton

 /// Summarize the scheduling resources required for an instruction of a
 /// particular scheduling class.
 ///
 /// Defined as an aggregate struct for creating tables with initializer lists.
 struct MCSchedClassDesc {
   static const unsigned short InvalidNumMicroOps = UINT16_MAX;
   static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
 
-#ifndef NDEBUG
   const char* Name;
-#endif
   unsigned short NumMicroOps;
   bool     BeginGroup;
   bool     EndGroup;
   unsigned WriteProcResIdx; // First index into WriteProcResTable.
   unsigned NumWriteProcResEntries;
   unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
   unsigned NumWriteLatencyEntries;
   unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.

utils/TableGen/SubtargetEmitter.cpp

 
 //
 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
 //
 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
   OS << "#ifdef DBGFIELD\n"
      << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
      << "#endif\n"
-     << "#ifndef NDEBUG\n"
-     << "#define DBGFIELD(x) x,\n"
-     << "#else\n"
-     << "#define DBGFIELD(x)\n"
-     << "#endif\n";
+     << "#define DBGFIELD(x) x,\n";
 
   if (SchedModels.hasItineraries()) {
     std::vector<std::vector<InstrItinerary>> ProcItinLists;
     // Emit the stage data
     EmitStageAndOperandCycleData(OS, ProcItinLists);
     EmitItineraries(OS, ProcItinLists);
   }
   OS << "\n// ===============================================================\n"