AArch64_BE function argument passing for ARM ABI

[cpirker]

Summary

Hi all,

This patch implements the function argument passing for ARM ABI for AArch64 big endian.
Please review.

Thanks,
Christian

[t.p.northover]

Hi Christian,

Most of this looks good. Just a couple of minor quibbles:

lib/Target/AArch64/AArch64ISelLowering.cpp

1641–1642

Is this extra alignment step needed? I can't think of any types with a bitsize not a multiple of 8.

test/CodeGen/AArch64/func-argpassing.ll

23

Accidentally removed whitespace.

test/CodeGen/AArch64/mul-lohi.ll

11

It's best to use "CHECK-BE-LABEL:" for function names. It makes debugging any failures in future easier.

[cpirker]

lib/Target/AArch64/AArch64ISelLowering.cpp

1641–1642

You are right, we simply copied line 1629.

[cpirker]

Hi Tim,

I updated the test files:

test/CodeGen/AArch64/func-argpassing.ll
test/CodeGen/AArch64/mul-lohi.ll

Thanks,
Christian

[cpirker]

I committed this patch as r204814.

[cpirker]

Hi Tim,

I added you as reviewer.
Can you please "Accepted Revision" so that I can "Close Revision"?
As you can see in the comment above, the patch is already committed (rL204814).

Thanks,
Christian

lib/Target/AArch64/AArch64ISelLowering.cpp

       int Size = Flags.getByValSize();
       unsigned NumRegs = (Size + 7) / 8;
 
+      uint32_t BEAlign = 0;
+      if (Size < 8 && !getSubtarget()->isLittle())
+        BEAlign = 8-Size;
       unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
-                                                 VA.getLocMemOffset(),
+                                                 VA.getLocMemOffset() + BEAlign,
                                                  false);
       SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
       InVals.push_back(FrameIdxN);

       // loaded before this eventual operation. Otherwise they'll be clobbered.
       Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
     } else {
-      SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
+      uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize()*8 :
+                                          VA.getLocVT().getSizeInBits();
+      OpSize = (OpSize + 7) / 8;
+      uint32_t BEAlign = 0;
+      if (OpSize < 8 && !getSubtarget()->isLittle())
+        BEAlign = 8-OpSize;
+      SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + BEAlign);
 
       DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
       DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());

test/CodeGen/AArch64/adc.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
 
 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
 ; CHECK-LABEL: test_simple:
 
   %valadd = add i128 %a, %b
-; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2
-; CHECK-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
+; CHECK-LE: adds [[ADDLO:x[0-9]+]], x0, x2
+; CHECK-LE-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
+; CHECK-BE: adds [[ADDLO:x[0-9]+]], x1, x3
+; CHECK-BE-NEXT: adcs [[ADDHI:x[0-9]+]], x0, x2
 
   %valsub = sub i128 %valadd, %c
-; CHECK: subs x0, [[ADDLO]], x4
-; CHECK: sbcs x1, [[ADDHI]], x5
+; CHECK-LE: subs x0, [[ADDLO]], x4
+; CHECK-LE: sbcs x1, [[ADDHI]], x5
+; CHECK-BE: subs x1, [[ADDLO]], x5
+; CHECK-BE: sbcs x0, [[ADDHI]], x4
 
   ret i128 %valsub
 ; CHECK: ret

 ; CHECK-LABEL: test_imm:
 
   %val = add i128 %a, 12
-; CHECK: adds x0, x0, #12
-; CHECK: adcs x1, x1, {{x[0-9]|xzr}}
+; CHECK-LE: adds x0, x0, #12
+; CHECK-LE: adcs x1, x1, {{x[0-9]|xzr}}
+; CHECK-BE: adds x1, x1, #12
+; CHECK-BE: adcs x0, x0, {{x[0-9]|xzr}}
 
   ret i128 %val
 ; CHECK: ret

   %rhs = shl i128 %b, 45
 
   %val = add i128 %a, %rhs
-; CHECK: adds x0, x0, x2, lsl #45
-; CHECK: adcs x1, x1, {{x[0-9]}}
+; CHECK-LE: adds x0, x0, x2, lsl #45
+; CHECK-LE: adcs x1, x1, {{x[0-9]}}
+; CHECK-BE: adds x1, x1, x3, lsl #45
+; CHECK-BE: adcs x0, x0, {{x[0-9]}}
 
   ret i128 %val
 ; CHECK: ret

   %rhs = shl i128 %ext, 3
 
   %val = add i128 %a, %rhs
-; CHECK: adds x0, x0, w2, sxth #3
-; CHECK: adcs x1, x1, {{x[0-9]}}
+; CHECK-LE: adds x0, x0, w2, sxth #3
+; CHECK-LE: adcs x1, x1, {{x[0-9]}}
+; CHECK-BE: adds x1, x1, w2, sxth #3
+; CHECK-BE: adcs x0, x0, {{x[0-9]}}
 
   ret i128 %val
 ; CHECK: ret

test/CodeGen/AArch64/func-argpassing.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
 
 %myStruct = type { i64 , i8, i32 }
 

 
     %retval = load volatile i32* %stacked
     ret i32 %retval
-; CHECK: ldr w0, [sp, #16]
+; CHECK-LE: ldr w0, [sp, #16]
+; CHECK-BE: ldr w0, [sp, #20]
 }
 
 define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,

 ; CHECK: check_i128_stackalign
     store i128 %stack2, i128* @var128
     ; Nothing local on stack in current codegen, so first stack is 16 away
-; CHECK: add     x[[REG:[0-9]+]], sp, #16
-; CHECK: ldr {{x[0-9]+}}, [x[[REG]], #8]
+; CHECK-LE: add     x[[REG:[0-9]+]], sp, #16
+; CHECK-LE: ldr {{x[0-9]+}}, [x[[REG]], #8]
+; CHECK-BE: ldr {{x[0-9]+}}, [sp, #24]
+
     ; Important point is that we address sp+24 for second dword
 ; CHECK: ldr     {{x[0-9]+}}, [sp, #16]
     ret void

test/CodeGen/AArch64/func-calls.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-BE --check-prefix=CHECK-NOFP %s
 
 %myStruct = type { i64 , i8, i32 }
 

 
   call void @check_i128_regalign(i32 0, i128 42)
 ; CHECK-NOT: mov x1
-; CHECK: movz x2, #42
-; CHECK: mov x3, xzr
+; CHECK-LE: movz x2, #42
+; CHECK-LE: mov x3, xzr
+; CHECK-BE: movz x3, #42
+; CHECK-BE: mov x2, xzr
 ; CHECK: bl check_i128_regalign
 
   ret void

test/CodeGen/AArch64/mul-lohi.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck --check-prefix=CHECK-BE %s
 
 define i128 @test_128bitmul(i128 %lhs, i128 %rhs) {
-; CHECK: test_128bitmul:
+; CHECK-LABEL: test_128bitmul:
 ; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
 ; CHECK: madd x1, x1, x2, [[PART1]]
 ; CHECK: mul x0, x0, x2
 
+; CHECK-BE-LABEL: test_128bitmul:
+; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
+; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
+; CHECK-BE: madd x0, x0, x3, [[PART1]]
+; CHECK-BE: mul x1, x1, x3
+
   %prod = mul i128 %lhs, %rhs
   ret i128 %prod
 }

test/CodeGen/AArch64/pic-eh-stubs.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64_be-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
 
 ; Make sure exception-handling PIC code can be linked correctly. An alternative
 ; to the sequence described below would have .gcc_except_table itself writable