Handle boundry condition missed by r297682

[zzheng]

Summary

There's a corner case when imm is -2147483648, that's -2^31 and 0x80000000 in two's compliment.

SignExt this value then take it's negative, it's still 0x80000000 and interpreted as -2^31 by i32 type.

So we have infinite loop here where this function consume and produce this number forever.

[zzheng]

Updated diff with full context

[efriedma]

(Missing context in diff; please generate diffs with "-U1000000".)

lib/Target/ARM/ARMISelLowering.cpp

9792

"-(1<<31)" is undefined behavior, strictly speaking. There are a few different ways you could write it, but the simplest is "INT32_MIN".

test/CodeGen/Thumb/long.ll

148

This comment is a bit misleading... we can, and do perform that transform.

[zzheng]

sorry... this should be fixed by https://reviews.llvm.org/rL297820, I'll abandon this one.

[efriedma]

r297820 got reverted in r297842.

lib/Target/ARM/ARMISelLowering.cpp

 }
 
 static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
                                       const ARMSubtarget *Subtarget) {
   if (Subtarget->isThumb1Only()) {
     SDValue RHS = N->getOperand(1);
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
       int64_t imm = C->getSExtValue();
-      if (imm < 0) {
+      if (imm < 0 && imm > -(1<<31)) {
         SDLoc DL(N);
         RHS = DAG.getConstant(-imm, DL, MVT::i32);
         unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
                                                            : ARMISD::ADDC;
         return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS);
       }
     }
   }

test/CodeGen/Thumb/long.ll

entry:
         %or = or i64 %shl, 4294967295
         %sub = sub nsw i64 %x, %or
         ret i64 %sub
 ; CHECK-LABEL: f9d:
 ; CHECK: adds r0, r0, #1
 ; CHECK: sbcs r1, r2
 }
 
+; i32 type represents from -2^31 to 2^31-1. Cannot transform this into
+; add i64 %y, 2147483648 because Thumb addc/subc don't support MVT::i32 type.
+define i64 @f9e(i64 %x, i64 %y) {
+entry:
+        %tmp1 = sub i64 %y, -2147483648
+        ret i64 %tmp1
+; CHECK-LABEL: f9e:
+; CHECK: movs r0, #1
+; CHECK: lsls r0, r0, #31
+; CHECK: movs r1, #0
+; CHECK: adds r0, r2, r0
+; CHECK: adcs r1, r3
+}
+
+define i64 @f9f(i64 %x, i64 %y) {
+entry:
+        %tmp1 = add i64 %y, -2147483648
+        ret i64 %tmp1
+; CHECK-LABEL: f9f:
+; CHECK: movs r0, #1
+; CHECK: lsls r0, r0, #31
+; CHECK: movs r1, #0
+; CHECK: adds r0, r2, r0
+; CHECK: sbcs r3, r1
+; CHECK: movs r1, r3
+}
+
 define i64 @f(i32 %a, i32 %b) {
 entry:
         %tmp = sext i32 %a to i64               ; <i64> [#uses=1]
         %tmp1 = sext i32 %b to i64              ; <i64> [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
         ret i64 %tmp2
 ; CHECK-LABEL: f:
 ; CHECK-V6: bl __aeabi_lmul