[NDS32 45/46] Support parsing/encode/decode for Load/Store Instructions

[shiva0217]

Summary

Support parsing/encode/decode for Load/Store Instructions

[shiva0217]

Add parameter name in function declaration.

lib/Target/NDS32/AsmParser/NDS32AsmParser.cpp

#include "NDS32GenAsmMatcher.inc"
   OperandMatchResultTy parseImm(OperandVector &Operands);
 
   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
 
   OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
 
   bool parseRelocOperand(OperandVector &);
 
+  bool parseMemory(OperandVector &);
+
   bool parseOperand(OperandVector &, StringRef Mnemonic);
 
   int matchCPURegisterName(StringRef Symbol);
   int matchMRegisterName(StringRef Symbol);
   int tryParseRegister();
 
 public:
   enum NDS32MatchResultTy {
public:
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCExpr *Expr = getImm();
     addExpr(Inst, Expr);
   }
 
   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    addRegOperands (Inst, N);
   }
 
   void addAddrRegShiftOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 3 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+    Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
   }
 
   void addAddrImm15sWordOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrImm15sHalfOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrImm15sByteOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrImm3uWordOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrImm3uHalfOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrImm3uByteOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrFPImm7uWordOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addAddrSPImm7uWordOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(NDS32::SP));
+    Inst.addOperand(MCOperand::createImm(Val));
   }
 
   void addRegListOperands(MCInst &Inst, unsigned N) const {
   }
 
   bool isReg() const override {
     return isGPRAsmReg();
   }
public:
   }
   bool isImm15u() const {
     return isConstantImm() ? isUIntN(15, getConstantImm()) : isImm();
   }
   bool isImm20u() const {
     return isConstantImm() ? isUIntN(20, getConstantImm()) : isImm();
   }
   bool isMemNoOffset() const {
-    return false;
+    if (!isMem()) return false;
+    // No offset of any kind.
+    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr;
   }
   // [Reg + Reg << sv], sv could be 0, 1, 2, 3
   bool isAddrRegShift() const {
-    return false;
+    if (!isMem()) return false;
+    if (Memory.OffsetImm != nullptr) return false;
+    if (Memory.ShiftImm > 3) return false;
+    return true;
   }
   // [Reg + imm15s << 2]
   bool isAddrImm15sWord() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    if (Memory.isMinusOffset) Val = -Val;
+    return isIntN(15 + 2, Val) && (Val % 4 == 0);
   }
   // [Reg + imm15s << 1]
   bool isAddrImm15sHalf() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    if (Memory.isMinusOffset) Val = -Val;
+    return isIntN(15 + 1, Val) && (Val % 2 == 0);
   }
   // [Reg + imm15s]
   bool isAddrImm15sByte() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    if (Memory.isMinusOffset) Val = -Val;
+    return isIntN(15, Val);
   }
   // [Reg + imm3u << 2]
   bool isAddrImm3uWord() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return isUIntN(3 + 2, Val) && (Val % 4 == 0);
   }
   // [Reg + imm3u << 1]
   bool isAddrImm3uHalf() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return isUIntN(3 + 1, Val) && (Val % 2 == 0);
   }
   // [Reg + imm3u]
   bool isAddrImm3uByte() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return isUIntN(3, Val);
   }
   // [FP + imm7u << 2]
   bool isAddrFPImm7uWord() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return isUIntN(7 + 2, Val) && (Val % 4 == 0);
   }
   // [SP + imm7u << 2]
   bool isAddrSPImm7uWord() const {
-    return false;
+    if (!isMem()) return false;
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return isUIntN(7 + 2, Val) && (Val % 4 == 0);
   }
   // imm15s << 2
   bool isOffsetImm15sWord() const {
-    return false;
+    return isConstantImm() && isIntN(15 + 2, getConstantImm()) &&
+           (getConstantImm() % 4 == 0);
   }
   // imm15s << 1
   bool isOffsetImm15sHalf() const {
-    return false;
+    return isConstantImm() && isIntN(15 + 1, getConstantImm()) &&
+           (getConstantImm() % 2 == 0);
   }
   // imm15s
   bool isOffsetImm15sByte() const {
-    return false;
+    return isConstantImm() && isIntN(15, getConstantImm());
   }
   bool isMemRegOffset() const {
-    return false;
+    return isReg();
   }
   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
   }
 
   void addOffsetImm15sWordOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getConstantImm()));
   }
 
   void addOffsetImm15sHalfOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getConstantImm()));
   }
 
   void addOffsetImm15sByteOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getConstantImm()));
   }
 
   StringRef getToken() const {
     assert(Kind == k_Token && "Invalid access!");
     return StringRef(Tok.Data, Tok.Length);
   }
 
   unsigned getReg() const override {
CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, NDS32AsmParser &Parser) {
     Op->EndLoc = E;
     return Op;
   }
 
   static std::unique_ptr<NDS32Operand>
   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
             unsigned OffsetRegNum, unsigned ShiftImm, bool isMinusOffset,
             SMLoc S, SMLoc E, NDS32AsmParser &Parser) {
+    auto Op = make_unique<NDS32Operand>(k_Memory, Parser);
+    Op->Memory.BaseRegNum = BaseRegNum;
+    Op->Memory.OffsetImm = OffsetImm;
+    Op->Memory.OffsetRegNum = OffsetRegNum;
+    Op->Memory.ShiftImm = ShiftImm;
+    Op->Memory.isMinusOffset = isMinusOffset;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
   }
 
   static std::unique_ptr<NDS32Operand>
   CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc,
                 NDS32AsmParser &Parser) {
   }
 
   bool isGPRAsmReg() const {
bool NDS32AsmParser::parseRelocOperand(OperandVector &Operands) {
   assert(Kind != NDS32MCExpr::MEK_None);
 
   IdVal = NDS32MCExpr::create(Kind, IdVal, getContext());
   Operands.push_back(NDS32Operand::CreateImm(IdVal, S, E, *this));
 
   return false;
 }
 
+// Parse an NDS32 memory expression, return false if successful else return
+// true or an error.  The first token must be a '[' when called.
+bool NDS32AsmParser::parseMemory(OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  SMLoc S, E;
+  bool isMinusOffset = false;
+  int BaseRegNum = -1;
+
+  DEBUG(dbgs() << "ParseMemory\n");
+
+  assert(Parser.getTok().is(AsmToken::LBrac) &&
+         "Token is not a Left Bracket");
+  S = Parser.getTok().getLoc();
+  Parser.Lex(); // Eat left bracket token.
+
+  if (Parser.getTok().is(AsmToken::Dollar)) {
+    Parser.Lex(); // Eat the Dollar.
+    DEBUG(dbgs() << "Eat $ \n");
+
+    const AsmToken &BaseRegTok = Parser.getTok();
+    BaseRegNum = tryParseRegister();
+    if (BaseRegNum == -1)
+      return Error(BaseRegTok.getLoc(), "register expected");
+
+    DEBUG(dbgs() << "BaseRegNum = " << BaseRegNum << "\n");
+  }
+
+  // The next token must either be a plus or a closing bracket.
+  const AsmToken &Tok = Parser.getTok();
+  if (!Tok.is(AsmToken::Plus) &&
+      !Tok.is(AsmToken::RBrac))
+    return Error(Tok.getLoc(), "malformed memory operand");
+
+  // parsing [Reg]
+  if (Tok.is(AsmToken::RBrac)) {
+    E = Tok.getEndLoc();
+    Parser.Lex(); // Eat right bracket token.
+
+    Operands.push_back(NDS32Operand::CreateMem(BaseRegNum, nullptr, 0, 0,
+                                               isMinusOffset, S, E, *this));
+    return false;
+  }
+
+  assert(Tok.is(AsmToken::Plus) && "Lost Plus in memory operand?!");
+
+  if (Tok.is(AsmToken::Plus)) {
+    DEBUG(dbgs() << "Eat + \n");
+    Parser.Lex(); // Eat the Plus.
+  }
+
+  if (Tok.is(AsmToken::LParen)) {
+    DEBUG(dbgs() << "Eat ( \n");
+    Parser.Lex(); // Eat the LParen.
+  }
+
+  if (Tok.is(AsmToken::Minus)) {
+    DEBUG(dbgs() << "Eat - \n");
+    Parser.Lex(); // Eat the Minus.
+    isMinusOffset = true;
+  }
+
+  // parsing [Reg + Imm]
+  if (Parser.getTok().is(AsmToken::Integer)) {
+    E = Parser.getTok().getLoc();
+
+    const MCExpr *Offset;
+    if (getParser().parseExpression(Offset))
+     return true;
+
+    // The expression has to be a constant. Memory references with relocations
+    // don't come through here, as they use the <label> forms of the relevant
+    // instructions.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
+    if (!CE)
+      return Error (E, "constant expression expected");
+
+    DEBUG(dbgs() << "Offset = " << CE->getValue() << "\n");
+
+    if (Tok.is(AsmToken::RParen)) {
+      Parser.Lex(); // Eat the RParen.
+    }
+
+    if (Parser.getTok().isNot(AsmToken::RBrac))
+      return Error(Parser.getTok().getLoc(), "']' expected");
+    Parser.Lex(); // Eat right bracket token.
+    E = Parser.getTok().getEndLoc();
+
+    // Don't worry about range checking the value here. That's handled by
+    // the is*() predicates.
+    Operands.push_back(NDS32Operand::CreateMem(BaseRegNum, CE, 0, 0,
+                       isMinusOffset, S, E, *this));
+    return false;
+  }
+
+  // parsing [Reg + Reg << sv]
+  if (Tok.is(AsmToken::Dollar)) {
+    Parser.Lex(); // Eat the Dollar.
+    DEBUG(dbgs() << "Eat $ \n");
+  }
+
+  E = Parser.getTok().getLoc();
+  int OffsetRegNum = tryParseRegister();
+  if (OffsetRegNum == -1)
+    return Error(E, "register expected");
+
+  DEBUG(dbgs() << "OffsetRegNum = " << OffsetRegNum << "\n");
+
+  unsigned ShiftImm = 0;
+  if (Tok.is(AsmToken::LessLess)) {
+    Parser.Lex(); // Eat the LessLess.
+    DEBUG(dbgs() << "Eat << \n");
+    E = Parser.getTok().getLoc();
+
+    const MCExpr *sv;  // sv immediate value
+    if (getParser().parseExpression(sv))
+      return true;
+
+    // The expression has to be a constant.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(sv);
+    if (!CE)
+      return Error (E, "constant expression expected");
+
+    ShiftImm = CE->getValue();
+    DEBUG(dbgs() << "ShiftImm = " << ShiftImm << "\n");
+  }
+
+  // Now we should have the closing ']'
+  if (Parser.getTok().isNot(AsmToken::RBrac))
+    return Error(Parser.getTok().getLoc(), "']' expected");
+  Parser.Lex(); // Eat right bracket token.
+
+  E = Parser.getTok().getEndLoc();
+
+  Operands.push_back(NDS32Operand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
+                                             ShiftImm, isMinusOffset,
+                                             S, E, *this));
+  return false;
+}
+
 bool NDS32AsmParser::
 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                  SMLoc NameLoc, OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   DEBUG(dbgs() << "ParseInstruction\n");
 
   // Check if we have valid mnemonic
   if (!mnemonicIsValid(Name, 0)) {
bool NDS32AsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   case AsmToken::Dollar: {
     // Parse the register.
     if (parseAnyRegister(Operands) != MatchOperand_NoMatch)
       return false;
   }
   case AsmToken::Identifier:
     DEBUG(dbgs() << "parse Identifier\n");
     return parseRelocOperand(Operands);
+  case AsmToken::LBrac:
+    return parseMemory(Operands);
   case AsmToken::Minus:
   case AsmToken::Plus:
   case AsmToken::Integer:
   case AsmToken::String: {
     OperandMatchResultTy ResTy = parseImm(Operands);
     return ResTy != MatchOperand_Success;
   }
   } // switch(getLexer().getKind())

lib/Target/NDS32/Disassembler/NDS32Disassembler.cpp

static DecodeStatus DecodeBranchTargetImm8s(MCInst &Inst,
                                             unsigned Offset,
                                             uint64_t Address,
                                             const void *Decoder) {
   int32_t BranchOffset = (SignExtend32<8>(Offset) * 2);
   Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
+static bool Check(DecodeStatus &Out, DecodeStatus In) {
+  switch (In) {
+    case MCDisassembler::Success:
+      // Out stays the same.
+      return true;
+    case MCDisassembler::SoftFail:
+      Out = In;
+      return true;
+    case MCDisassembler::Fail:
+      Out = In;
+      return false;
+  }
+  llvm_unreachable("Invalid DecodeStatus!");
+}
+
 // Decode [Reg + Imm] addressing mode
 static DecodeStatus DecodeAddrRegImm(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder,
                                      unsigned Ra,
                                      int32_t Imm) {
-  return MCDisassembler::Success;
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Ra, Address, Decoder)))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createImm(Imm));
+
+  return S;
 }
 
 static DecodeStatus DecodeAddrWord(MCInst &Inst,
                                    unsigned Insn,
                                    uint64_t Address,
                                    const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Value = fieldFromInstruction(Insn, 0, 15) * 4;
+  int32_t Imm = SignExtend32<17>(Value);
+  unsigned Ra = fieldFromInstruction(Insn, 15, 5);
+
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, Ra, Imm);
 }
 
 static DecodeStatus DecodeAddrHalf(MCInst &Inst,
                                    unsigned Insn,
                                    uint64_t Address,
                                    const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Value = fieldFromInstruction(Insn, 0, 15) * 2;
+  int32_t Imm = SignExtend32<16>(Value);
+  unsigned Ra = fieldFromInstruction(Insn, 15, 5);
+
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, Ra, Imm);
 }
 
 static DecodeStatus DecodeAddrByte(MCInst &Inst,
                                    unsigned Insn,
                                    uint64_t Address,
                                    const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Value = fieldFromInstruction(Insn, 0, 15);
+  int32_t Imm = SignExtend32<15>(Value);
+  unsigned Ra = fieldFromInstruction(Insn, 15, 5);
+
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, Ra, Imm);
 }
 
 static DecodeStatus DecodeAddrImm3uWord(MCInst &Inst,
                                         unsigned Insn,
                                         uint64_t Address,
                                         const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Imm = fieldFromInstruction(Insn, 0, 3) * 4;
+  unsigned Ra = fieldFromInstruction(Insn, 3, 3);
+
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, Ra, Imm);
 }
 
 static DecodeStatus DecodeAddrImm3uHalf(MCInst &Inst,
                                         unsigned Insn,
                                         uint64_t Address,
                                         const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Imm = fieldFromInstruction(Insn, 0, 3) * 2;
+  unsigned Ra = fieldFromInstruction(Insn, 3, 3);
+
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, Ra, Imm);
 }
 
 static DecodeStatus DecodeAddrImm3uByte(MCInst &Inst,
                                         unsigned Insn,
                                         uint64_t Address,
                                         const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Imm = fieldFromInstruction(Insn, 0, 3);
+  unsigned Ra = fieldFromInstruction(Insn, 3, 3);
+
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, Ra, Imm);
 }
 
 // Decode [$fp + Imm7u << 2] addressing mode
 static DecodeStatus DecodeAddrFPImm7uWord(MCInst &Inst,
                                           unsigned Insn,
                                           uint64_t Address,
                                           const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Imm = fieldFromInstruction(Insn, 0, 7) * 4;
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, 28, Imm);
 }
 
 // Decode sp base imply [+ Imm7u << 2] addressing mode
 static DecodeStatus DecodeAddrSPImm7uWord(MCInst &Inst,
                                           unsigned Insn,
                                           uint64_t Address,
                                           const void *Decoder) {
-  return MCDisassembler::Success;
+  int32_t Imm = fieldFromInstruction(Insn, 0, 7) * 4;
+  return DecodeAddrRegImm(Inst, Insn, Address, Decoder, 31, Imm);
 }
 
 static DecodeStatus DecodeAddrRegShift(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,
                                        const void *Decoder) {
-  return MCDisassembler::Success;
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned Ra = fieldFromInstruction(Insn, 5, 5);
+  unsigned Rb = fieldFromInstruction(Insn, 2, 5);
+  unsigned sv = fieldFromInstruction(Insn, 0, 2);
+
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Ra, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rb, Address, Decoder)))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createImm(sv));
+
+  return S;
 }
 
 static DecodeStatus DecodeAddrOffsetWord(MCInst &Inst,
                                          unsigned Insn,
                                          uint64_t Address,
                                          const void *Decoder) {
+  int32_t Value = fieldFromInstruction(Insn, 0, 15) * 4;
+  int32_t Imm = SignExtend32<17>(Value);
+
+  Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeAddrOffsetHalf(MCInst &Inst,
                                          unsigned Insn,
                                          uint64_t Address,
                                          const void *Decoder) {
+  int32_t Value = fieldFromInstruction(Insn, 0, 15) * 2;
+  int32_t Imm = SignExtend32<16>(Value);
+
+  Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeAddrOffsetByte(MCInst &Inst,
                                          unsigned Insn,
                                          uint64_t Address,
                                          const void *Decoder) {
+  int32_t Value = fieldFromInstruction(Insn, 0, 15);
+  int32_t Imm = SignExtend32<15>(Value);
+
+  Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeImm5s(MCInst &Inst,
                                 unsigned Insn,
                                 uint64_t Address,
                                 const void *Decoder) {
   int32_t Value = fieldFromInstruction(Insn, 0, 5);

lib/Target/NDS32/MCTargetDesc/NDS32MCCodeEmitter.cpp

getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
 
   return 0;
 }
 
 unsigned NDS32MCCodeEmitter::
 getOffsetImm7uWordEncoding(const MCInst &MI, unsigned OpNo,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isImm() &&
+         "getOffsetImm7uWordEncoding expects only an immediate");
+  // The immediate is encoded as 'immediate << 2'.
+  unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
+  assert((Res & 3) == 0);
+  return Res >> 2;
 }
 
 unsigned NDS32MCCodeEmitter::
 getAddrFPImm7uWordEncoding(const MCInst &MI, unsigned OpNo,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const {
-  return 0;
+  // FP don't need encoding to the instruction because
+  // swi37/lwi37 already imply the usage.
+  const MCOperand &MO = MI.getOperand(OpNo + 1);
+  // The immediate is encoded as 'immediate << 2'.
+  unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
+  assert((Res & 3) == 0);
+  return Res >> 2;
 }
 
 unsigned NDS32MCCodeEmitter::
 getAddrSPImm7uWordEncoding(const MCInst &MI, unsigned OpNo,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const {
-  return 0;
+  // SP don't need encoding to the instruction because
+  // swi37.sp/lwi37.sp already imply the usage.
+  const MCOperand &MO = MI.getOperand(OpNo + 1);
+  // The immediate is encoded as 'immediate << 2'.
+  unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
+  assert((Res & 3) == 0);
+  return Res >> 2;
 }
 
 unsigned
 NDS32MCCodeEmitter::getAddrRegEncoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isReg() &&
+         "getAddrRegEncoding expects only a register");
+  return getMachineOpValue(MI, MO,  Fixups, STI);
 }
 
 unsigned
 NDS32MCCodeEmitter::getAddrRegShiftEncoding(const MCInst &MI, unsigned OpNo,
                                             SmallVectorImpl<MCFixup> &Fixups,
                                             const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  const MCOperand &MO2 = MI.getOperand(OpNo + 2);
+
+  // addr{11-7}; // Ra
+  // addr{6-2};  // Rb
+  // addr{1-0};  // sv
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 7 |
+         getMachineOpValue(MI, MO1, Fixups, STI) << 2 |
+         getMachineOpValue(MI, MO2, Fixups, STI);
 }
 
 // Encoding [Reg + imm3u << 2]
 unsigned
 NDS32MCCodeEmitter::getAddrImm3uWordEncoding(const MCInst &MI, unsigned OpNo,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 3 |
+         getMachineOpValue(MI, MO1, Fixups, STI) >> 2;
 }
 
 // Encoding [Reg + imm3u << 1]
 unsigned
 NDS32MCCodeEmitter::getAddrImm3uHalfEncoding(const MCInst &MI, unsigned OpNo,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 3 |
+         getMachineOpValue(MI, MO1, Fixups, STI) >> 1;
 }
 
 // Encoding [Reg + imm3u]
 unsigned
 NDS32MCCodeEmitter::getAddrImm3uByteEncoding(const MCInst &MI, unsigned OpNo,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 3 |
+         getMachineOpValue(MI, MO1, Fixups, STI);
 }
 
 // Encoding [Reg + imm15s << 2]
 unsigned
 NDS32MCCodeEmitter::getAddrWordEncoding(const MCInst &MI, unsigned OpNo,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 15 |
+         getMachineOpValue(MI, MO1, Fixups, STI) >> 2;
 }
 
 // Encoding [Reg + imm15s << 1]
 unsigned
 NDS32MCCodeEmitter::getAddrHalfEncoding(const MCInst &MI, unsigned OpNo,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 15 |
+         getMachineOpValue(MI, MO1, Fixups, STI) >> 1;
 }
 
 // Encoding [Reg + imm15s]
 unsigned
 NDS32MCCodeEmitter::getAddrByteEncoding(const MCInst &MI, unsigned OpNo,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  const MCOperand &MO1 = MI.getOperand(OpNo + 1);
+  return getMachineOpValue(MI, MO,  Fixups, STI) << 15 |
+         getMachineOpValue(MI, MO1, Fixups, STI);
 }
 
 unsigned
 NDS32MCCodeEmitter::getAddrRegOffsetEncoding(const MCInst &MI, unsigned OpNo,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isReg() &&
+         "getAddrRegOffsetEncoding expects only a register");
+  return getMachineOpValue(MI, MO,  Fixups, STI);
 }
 
 unsigned NDS32MCCodeEmitter::
 getAddrOffsetWordEncoding(const MCInst &MI, unsigned OpNo,
                           SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isImm() &&
+         "getAddrOffsetWordEncoding expects only an immediate");
+  return getMachineOpValue(MI, MO,  Fixups, STI) >> 2;
 }
 
 unsigned NDS32MCCodeEmitter::
 getAddrOffsetHalfEncoding(const MCInst &MI, unsigned OpNo,
                           SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isImm() &&
+         "getAddrOffsetHalfEncoding expects only an immediate");
+  return getMachineOpValue(MI, MO,  Fixups, STI) >> 1;
 }
 
 unsigned NDS32MCCodeEmitter::
 getAddrOffsetByteEncoding(const MCInst &MI, unsigned OpNo,
                           SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const {
-  return 0;
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isImm() &&
+         "getAddrOffsetByteEncoding expects only an immediate");
+  return getMachineOpValue(MI, MO,  Fixups, STI);
 }
 
 /// getBranchTargetImm8sEncoding - Return binary encoding of the branch
 /// target operand. If the machine operand requires relocation,
 /// record the relocation and return zero.
 unsigned NDS32MCCodeEmitter::
 getBranchTargetImm8sEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,

lib/Target/NDS32/NDS32Predicate.td

 def AddrImm15sWordAsmOperand : AsmOperandClass { let Name = "AddrImm15sWord"; }
 def addr_imm15s_word : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm15sWord", []> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s << 2).
 
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrWordEncoding";
+  let DecoderMethod = "DecodeAddrWord";
+  let ParserMatchClass = AddrImm15sWordAsmOperand;
 }
 
 // addr_imm15s_half := [reg + imm15s << 1]
 def AddrImm15sHalfAsmOperand : AsmOperandClass { let Name = "AddrImm15sHalf"; }
 def addr_imm15s_half : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm15sHalf", []> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s << 1).
 
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrHalfEncoding";
+  let DecoderMethod = "DecodeAddrHalf";
+  let ParserMatchClass = AddrImm15sHalfAsmOperand;
 }
 
 // addr_imm15s_byte := [reg + imm15s]
 def AddrImm15sByteAsmOperand : AsmOperandClass { let Name = "AddrImm15sByte"; }
 def addr_imm15s_byte : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm15sByte", []> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s).
 
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrByteEncoding";
+  let DecoderMethod = "DecodeAddrByte";
+  let ParserMatchClass = AddrImm15sByteAsmOperand;
 }
 
 // ldst_reg_shift := [reg + reg << sv]
 // sv: shift value could be 0, 1, 2, 3
 def MemAddrRegShiftAsmOperand : AsmOperandClass { let Name = "AddrRegShift"; }
 def ldst_reg_shift : MemOperand,
                   ComplexPattern<i32, 3, "SelectLdStRegShift", []> {
   let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$shift);
   let PrintMethod = "printAddrRegShift";
+  let EncoderMethod = "getAddrRegShiftEncoding";
+  let DecoderMethod = "DecodeAddrRegShift";
+  let ParserMatchClass = MemAddrRegShiftAsmOperand;
 }
 
 
 // addr_reg := [reg]
 // use single reg as memory access address
 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
 def addr_reg : MemOperand,
                ComplexPattern<i32, 1, "SelectAddrReg", []> {
   let MIOperandInfo = (ops GPR:$base);
   let PrintMethod = "printAddrRegOperand";
+  let EncoderMethod = "getAddrRegEncoding";
+  let DecoderMethod = "DecodeGPRRegisterClass";
+  let ParserMatchClass = MemNoOffsetAsmOperand;
 }
 
 // offset operand as Reg for ([Reg], [Reg]) POST_INC addressing mode
 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
 def offset_reg : MemOperand,
                 ComplexPattern<i32, 2, "SelectAddrOffsetReg",
                 [], [SDNPWantRoot]> {
   let MIOperandInfo = (ops GPR, GPR);
   let PrintMethod = "printAddrRegOffsetOperand";
+  let EncoderMethod = "getAddrRegOffsetEncoding";
+  let DecoderMethod = "DecodeGPRRegisterClass";
+  let ParserMatchClass = MemRegOffsetAsmOperand;
 }
 
 // addressing mode operand for [Reg], (imm15s << 2) POST_INC addressing mode
 def OffsetImm15sWordAsmOperand : AsmOperandClass { let Name = "OffsetImm15sWord"; }
 def offset_imm15s_word : MemOperand,
                 ComplexPattern<i32, 2, "SelectAddrImm15sWordPostInc",
                 [], [SDNPWantRoot]> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s << 2).
   let MIOperandInfo = (ops GPR, i32imm);
   let PrintMethod = "printAddrImmOffsetOperand";
+  let EncoderMethod = "getAddrOffsetWordEncoding";
+  let DecoderMethod = "DecodeAddrOffsetWord";
+  let ParserMatchClass = OffsetImm15sWordAsmOperand;
 }
 
 // addressing mode operand for [Reg], (imm15s << 1) POST_INC addressing mode
 def OffsetImm15sHalfAsmOperand : AsmOperandClass { let Name = "OffsetImm15sHalf"; }
 def offset_imm15s_half : MemOperand,
                 ComplexPattern<i32, 2, "SelectAddrImm15sHalfPostInc",
                 [], [SDNPWantRoot]> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s << 1).
   let MIOperandInfo = (ops GPR, i32imm);
   let PrintMethod = "printAddrImmOffsetOperand";
+  let EncoderMethod = "getAddrOffsetHalfEncoding";
+  let DecoderMethod = "DecodeAddrOffsetHalf";
+  let ParserMatchClass = OffsetImm15sHalfAsmOperand;
 }
 
 // addressing mode operand for [Reg], (imm15s) POST_INC addressing mode
 def OffsetImm15sByteAsmOperand : AsmOperandClass { let Name = "OffsetImm15sByte"; }
 def offset_imm15s_byte : MemOperand,
                 ComplexPattern<i32, 2, "SelectAddrImm15sBytePostInc",
                 [], [SDNPWantRoot]> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s).
   let MIOperandInfo = (ops GPR, i32imm);
   let PrintMethod = "printAddrImmOffsetOperand";
+  let EncoderMethod = "getAddrOffsetByteEncoding";
+  let DecoderMethod = "DecodeAddrOffsetByte";
+  let ParserMatchClass = OffsetImm15sByteAsmOperand;
 }
 
 // A list of registers. Used by load/store multiple.
 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
 def reglist : Operand<i32> {
   let MIOperandInfo = (ops GPR:$base, variable_ops);
   let PrintMethod = "printRegisterList";
   let ParserMatchClass = RegListAsmOperand;

 def AddrImm3uWordAsmOperand : AsmOperandClass { let Name = "AddrImm3uWord"; }
 def addr_imm3u_word : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm3uWord", []> {
   // 3-bit unsigned immediate operand. Note that for byte size load/store
   // immediate access range would be + (imm3u << 2).
 
   let MIOperandInfo = (ops lGPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrImm3uWordEncoding";
+  let DecoderMethod = "DecodeAddrImm3uWord";
+  let ParserMatchClass = AddrImm3uWordAsmOperand;
 }
 
 def AddrImm3uHalfAsmOperand : AsmOperandClass { let Name = "AddrImm3uHalf"; }
 def addr_imm3u_half : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm3uHalf", []> {
   // 3-bit unsigned immediate operand. Note that for byte size load/store
   // immediate access range would be + (imm3u << 1).
 
   let MIOperandInfo = (ops lGPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrImm3uHalfEncoding";
+  let DecoderMethod = "DecodeAddrImm3uHalf";
+  let ParserMatchClass = AddrImm3uHalfAsmOperand;
 }
 
 def AddrImm3uByteAsmOperand : AsmOperandClass { let Name = "AddrImm3uByte"; }
 def addr_imm3u_byte : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm3uByte", []> {
   // 3-bit unsigned immediate operand. Note that for byte size load/store
   // immediate access range would be + (imm3u).
 
   let MIOperandInfo = (ops lGPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrImm3uByteEncoding";
+  let DecoderMethod = "DecodeAddrImm3uByte";
+  let ParserMatchClass = AddrImm3uByteAsmOperand;
 }
 
 // addr_sp_base_offset_imm7u_word := [+ imm7u << 2]
 def AddrSPImm7uWordAsmOperand : AsmOperandClass { let Name = "AddrSPImm7uWord"; }
 def addr_sp_base_offset_imm7u_word : MemOperand {
   let MIOperandInfo = (ops SPReg:$base, i32imm:$offsimm);
   let PrintMethod = "printSPImplyAddrImmOperand";
+  let EncoderMethod = "getAddrSPImm7uWordEncoding";
+  let DecoderMethod = "DecodeAddrSPImm7uWord";
+  let ParserMatchClass = AddrSPImm7uWordAsmOperand;
 }
 
 // addr_fp_base_offset_imm7u_word := [$fp + imm7u << 2]
 def AddrFPImm7uWordAsmOperand : AsmOperandClass { let Name = "AddrFPImm7uWord"; }
 def addr_fp_base_offset_imm7u_word : MemOperand {
   let MIOperandInfo = (ops FPReg:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
+  let EncoderMethod = "getAddrFPImm7uWordEncoding";
+  let DecoderMethod = "DecodeAddrFPImm7uWord";
+  let ParserMatchClass = AddrFPImm7uWordAsmOperand;
 }

test/MC/NDS32/load-store-insns.s

+! RUN: llvm-mc -triple nds32 -filetype=obj -o %t %s
+! RUN:    llvm-objdump -d -r -triple nds32 %t | FileCheck %s
+foo:
+
+!------------------------------------------------------------------------------
+! Load instructions
+!------------------------------------------------------------------------------
+  lwi $r0, [$r1 + 4]
+  lw $r0, [$r1 + $r2]
+  lhi $r0, [$r1 + 4]
+  lh $r0, [$r1 + $r2]
+  lbi $r0, [$r1 + 4]
+  lb $r0, [$r1 + $r2]
+
+! CHECK: 04 00 80 01     lwi     $r0, [$r1 + (4)]
+! CHECK: 38 00 88 02     lw      $r0, [$r4 + $r2]
+! CHECK: 02 00 80 02     lhi     $r0, [$r1 + (4)]
+! CHECK: 38 00 88 01     lh      $r0, [$r4 + $r2]
+! CHECK: 00 00 80 04     lbi     $r0, [$r1 + (4)]
+! CHECK: 38 00 88 00     lb      $r0, [$r4 + $r2]
+
+!------------------------------------------------------------------------------
+! Post-indexed Load instructions
+!------------------------------------------------------------------------------
+  lwi.bi $r0, [$r1], 4
+  lw.bi $r0, [$r1], $r2
+  lhi.bi $r0, [$r1], 4
+  lh.bi $r0, [$r1], $r2
+  lbi.bi $r0, [$r1], 4
+  lb.bi $r0, [$r1], $r2
+
+! CHECK: 0c 00 80 01     lwi.bi  $r0, [$r1], 4
+! CHECK: 38 00 88 06     lw.bi   $r0, [$r1], $r2
+! CHECK: 0a 00 80 02     lhi.bi  $r0, [$r1], 4
+! CHECK: 38 00 88 05     lh.bi   $r0, [$r1], $r2
+! CHECK: 08 00 80 04     lbi.bi  $r0, [$r1], 4
+! CHECK: 38 00 88 04     lb.bi   $r0, [$r1], $r2
+
+!------------------------------------------------------------------------------
+! 16-Bit Load instructions
+!------------------------------------------------------------------------------
+  lwi333 $r0, [$r1 + 4]
+  lhi333 $r1, [$r2 + 2]
+  lbi333 $r2, [$r3 + 5]
+  lwi37.sp $r4, [+ 16]
+  lwi37 $r5, [$fp + 20]
+
+! CHECK: a0 09   lwi333  $r0, [$r1 + (4)]
+! CHECK: a4 51   lhi333  $r1, [$r2 + (2)]
+! CHECK: a6 9d   lbi333  $r2, [$r3 + (5)]
+! CHECK: f4 04   lwi37.sp        $r4, [+ (16)]
+! CHECK: bd 05   lwi37   $r5, [$fp + (20)]
+
+!------------------------------------------------------------------------------
+! Store instructions
+!------------------------------------------------------------------------------
+  swi $r0, [$r1 + 4]
+  sw $r0, [$r1 + $r2]
+  shi $r0, [$r1 + 4]
+  sh $r0, [$r1 + $r2]
+  sbi $r0, [$r1 + 4]
+  sb $r0, [$r1 + $r2]
+
+! CHECK: 14 00 80 01     swi     $r0, [$r1 + (4)]
+! CHECK: 38 00 88 0a     sw      $r0, [$r4 + $r2]
+! CHECK: 12 00 80 02     shi     $r0, [$r1 + (4)]
+! CHECK: 38 00 88 09     sh      $r0, [$r4 + $r2]
+! CHECK: 10 00 80 04     sbi     $r0, [$r1 + (4)]
+! CHECK: 38 00 88 08     sb      $r0, [$r4 + $r2]
+
+!------------------------------------------------------------------------------
+! Post-indexed Store instructions
+!------------------------------------------------------------------------------
+  swi.bi $r0, [$r1], 4
+  sw.bi $r0, [$r1], $r2
+  shi.bi $r0, [$r1], 4
+  sh.bi $r0, [$r1], $r2
+  sbi.bi $r0, [$r1], 4
+  sb.bi $r0, [$r1], $r2
+
+! CHECK: 1c 00 80 01     swi.bi  $r0, [$r1], 4
+! CHECK: 38 00 88 0e     sw.bi   $r0, [$r1], $r2
+! CHECK: 1a 00 80 02     shi.bi  $r0, [$r1], 4
+! CHECK: 38 00 88 0d     sh.bi   $r0, [$r1], $r2
+! CHECK: 18 00 80 04     sbi.bi  $r0, [$r1], 4
+! CHECK: 38 00 88 0c     sb.bi   $r0, [$r1], $r2
+
+!------------------------------------------------------------------------------
+! 16-Bit Store instructions
+!------------------------------------------------------------------------------
+  swi333 $r6, [$r1 + 8]
+  shi333 $r7, [$r2 + 4]
+  sbi333 $r2, [$r3 + 3]
+  swi37.sp $r3, [+ 24]
+  swi37 $r2, [$fp + 20]
+
+! CHECK: a9 8a   swi333  $r6, [$r1 + (8)]
+! CHECK: ad d2   shi333  $r7, [$r2 + (4)]
+! CHECK: ae 9b   sbi333  $r2, [$r3 + (3)]
+! CHECK: f3 86   swi37.sp        $r3, [+ (24)]
+! CHECK: ba 85   swi37   $r2, [$fp + (20)]