[NDS32 33/46] Support Generation of Jump Table

[shiva0217]

Summary

Support Generation of Jump Table

lib/Target/NDS32/NDS32ISelLowering.h

public:
     SDValue LowerDIVREM(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 
+    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
+
     /// getTargetNodeName - This method returns the name of a target specific
     /// DAG node.
     const char *getTargetNodeName(unsigned Opcode) const override;
 
     TargetLowering::ConstraintType
     getConstraintType(StringRef Constraint) const override;
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
private:
     // Create a TargetExternalSymbol node.
     SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
                           unsigned Flag) const;
 
     // Create a TargetBlockAddress node.
     SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
                           unsigned Flag) const;
 
+    // Create a TargetJumpTable node.
+    SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
+                          unsigned Flag) const;
+
     typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
 
     /// copyByValArg - Copy argument registers which were used to pass a byval
     /// argument to the stack. Create a stack frame object for the byval
     /// argument.
     void copyByValRegs(SDValue Chain, const SDLoc &DL,
                        std::vector<SDValue> &OutChains, SelectionDAG &DAG,
                        const ISD::ArgFlagsTy &Flags,

lib/Target/NDS32/NDS32ISelLowering.cpp

SDValue NDS32TargetLowering::LowerOperation(SDValue Op,
   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
   case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
   case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
   case ISD::UDIVREM:          return LowerDIVREM(Op, DAG);
   case ISD::SDIVREM:          return LowerDIVREM(Op, DAG);
   case ISD::VASTART:          return LowerVASTART(Op, DAG);
   case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
+  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
   default:
     llvm_unreachable("unimplemented operand");
   }
 }
 
 SDValue NDS32TargetLowering::LowerDIVREM(SDValue Op, SelectionDAG &DAG) const {
   SDLoc dl(Op);
   EVT VT      = Op.getValueType();

 }
 
 SDValue NDS32TargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
                                            SelectionDAG &DAG,
                                            unsigned Flag) const {
   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
 }
 
+SDValue NDS32TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
+                                           SelectionDAG &DAG,
+                                           unsigned Flag) const {
+  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
+}
+
 SDValue NDS32TargetLowering::LowerVASTART(SDValue Op,
                                            SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   NDS32MachineFunctionInfo *FuncInfo = MF.getInfo<NDS32MachineFunctionInfo>();
   auto PtrVT = getPointerTy(DAG.getDataLayout());
 
   // Frame index of first vararg argument
   SDValue FrameIndex =
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
                        DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
                        MachinePointerInfo());
   }
 
   unsigned Reg = MF.addLiveIn(NDS32::LP, getRegClassFor(MVT::i32));
   return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
 }
 
+SDValue NDS32TargetLowering::
+LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
+{
+  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
+  EVT Ty = Op.getValueType();
+
+  return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
+}
+
 
 //===----------------------------------------------------------------------===//
 //                       NDS32 Addressing Mode Support
 //===----------------------------------------------------------------------===//
 
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.

lib/Target/NDS32/NDS32InstrInfo.td

 //===----------------------------------------------------------------------===//
 // Pattern Transformation
 //===----------------------------------------------------------------------===//
 
 // hi/lo relocs
 def : Pat<(NDS32hi20 tglobaladdr:$in), (SETHI tglobaladdr:$in)>;
 def : Pat<(NDS32hi20 tblockaddress:$in), (SETHI tblockaddress:$in)>;
 def : Pat<(NDS32hi20 texternalsym:$in), (SETHI texternalsym:$in)>;
+def : Pat<(NDS32hi20 tjumptable:$in), (SETHI tjumptable:$in)>;
 
 def : Pat<(or GPR:$hi, (NDS32lo12 tglobaladdr:$lo)),
           (ORI GPR:$hi, tglobaladdr:$lo)>;
 def : Pat<(or GPR:$hi, (NDS32lo12 tblockaddress:$lo)),
           (ORI GPR:$hi, tblockaddress:$lo)>;
 def : Pat<(or GPR:$hi, (NDS32lo12 texternalsym:$lo)),
           (ORI GPR:$hi, texternalsym:$lo)>;
+def : Pat<(or GPR:$hi, (NDS32lo12 tjumptable:$lo)),
+          (ORI GPR:$hi, tjumptable:$lo)>;
 
 // Arbitrary immediates
 def : Pat<(i32 imm:$imm),
           (ORI (SETHI (HI20 imm:$imm)), (LO12 imm:$imm))>;
 
 // division patterns
 def : Pat<(NDS32sdivrem i32:$Ra, i32:$Rb),
           (SDIVREM i32:$Ra, i32:$Rb)>;

test/CodeGen/NDS32/jumptable.ll

+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "nds32le---elf"
+
+; Function Attrs: norecurse nounwind readnone
+define i32 @jumptable(i32 %a, i32 %b) local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: jumptable:
+; CHECK: lw      $r0, [$r2 + $r0 << 2]
+; CHECK: jr5     $r0
+  switch i32 %a, label %sw.epilog [
+    i32 1, label %sw.bb
+    i32 2, label %return
+    i32 3, label %sw.bb2
+    i32 4, label %sw.bb4
+  ]
+
+sw.bb:                                            ; preds = %entry
+  %mul = mul nsw i32 %b, %b
+  br label %return
+
+sw.bb2:                                           ; preds = %entry
+  %mul3 = mul nsw i32 %b, 3
+  br label %return
+
+sw.bb4:                                           ; preds = %entry
+  %mul5 = mul nsw i32 %b, %b
+  %mul6 = mul nsw i32 %mul5, %b
+  br label %return
+
+sw.epilog:                                        ; preds = %entry
+  br label %return
+
+return:                                           ; preds = %entry, %sw.epilog, %sw.bb4, %sw.bb2, %sw.bb
+  %retval.0 = phi i32 [ 0, %sw.epilog ], [ %mul6, %sw.bb4 ], [ %mul3, %sw.bb2 ], [ %mul, %sw.bb ], [ %b, %entry ]
+  ret i32 %retval.0
+}
+
+; CHECK: .LJTI0_0:
+; CHECK-NEXT: .long   .LBB0_2
+; CHECK-NEXT: .long   .LBB0_6
+; CHECK-NEXT: .long   .LBB0_3
+; CHECK-NEXT: .long   .LBB0_4