This is an archive of the discontinued LLVM Phabricator instance.

[X86][Tablegen] Fixing register defs and uses for the ENTER instruction.
Needs ReviewPublic

Authored by cray on Jan 30 2017, 12:44 PM.

Reviewers

craig.topper

Repository

rL LLVM

Build Status

Buildable 3412
Build 3412: arc lint + arc unit

lib/Target/X86/X86InstrInfo.td
1080	Why mayLoad? Shouldn't it be mayStore?

lib/Target/X86/X86InstrInfo.td
1080	Nice catch! I will fix this.

Path

Size

lib/

Target/

X86/

	X86InstrInfo.td
	X86InstrInfo.td (revision 293512)

11 lines

Context not available.


	// Constructing a stack frame.	// Constructing a stack frame.
	def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),	let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
		craig.topperUnsubmitted Not Done Reply Inline Actions Why mayLoad? Shouldn't it be mayStore? craig.topper: Why mayLoad? Shouldn't it be mayStore?
		crayAuthorUnsubmitted Not Done Reply Inline Actions Nice catch! I will fix this. cray: Nice catch! I will fix this.
	"enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;	def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
		"enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>,
		Requires<[Not64BitMode]>;

		let Defs = [RBP, RSP], Uses = [RBP, RSP], mayLoad = 1, hasSideEffects=0 in
		def ENTER64 : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
		"enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>,
		Requires<[In64BitMode]>;

	let SchedRW = [WriteALU] in {	let SchedRW = [WriteALU] in {
	let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in	let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
	def LEAVE : I<0xC9, RawFrm,	def LEAVE : I<0xC9, RawFrm,
Context not available.