[MSP430] Add SRet support to MSP430 target

[awygle]

Summary

This patch adds support for struct return values to the MSP430 target backend. It also reverses the order of argument and return registers in the calling convention to bring it into closer alignment with the published EABI from TI.

[pftbest]

test/CodeGen/MSP430/cc_args.ll

55

Third argument should be back-filled into r13 register, as per section 3.3.4 of EABI.

[awygle]

Updated patch to correctly backfill registers when "holes" are created by 64-bit arguments (EABI section 3.3.4) and to split 32-bit arguments when only one free register remains (EABI section 3.3.3)

[awygle]

ping

[pftbest]

This change looks good, but I don't have any rights to accept it, sorry. We'll have to wait for aKor to review it, you can try to ask him on irc if you see him.

[asl]

lib/Target/MSP430/MSP430ISelLowering.cpp

247–248

I'm a bit confused by logic here. Is there any reason why we shouldn't simply count from 0 here? Could also switch to range-for while here?

248–256

Minor nit: I'd prefer += 1 here.

328

Minor nit: I'd prefer -= 1 here

332

Please follow LLVM's coding style : no newline before "else if" / "else"

573

No braces

[awygle]

Updated the diff to address the comments made by @asl .

[pftbest]

Sorry for being pedantic, but your new diff adds a lot of trailing spaces to the code.

[awygle]

Updated diff to hopefully address @pftbest's concerns about whitespace - I wasn't totally sure what you were pointing to but there's now no trailing whitespace in any of the code files that are modified by this patch.

[pftbest]

Whitespace is gone, thank you.
Also I did some testing: compiled llvm with expensive checks on and address sanitizer, found no issues.
Compiled a non-trivial program and ran it on CC430 MCU, it worked fine.
So this patch LGTM

[asl]

Looks like one comment in ParseFunctionArgs was not addressed.

[pftbest]

As I see it, CurrentArgIndex is overloaded with two (or more) tasks, so the code is confusing. Maybe it would be better if CurrentArgIndex was just a counter, and the other conditions can be handled by introducing boolean flags, for example.

[awygle]

Updated patch to stop being so clever with initialization in ParseFunctionArgs

[awygle]

The problem with ParseFunctionArgs was that it was being too clever with initializing CurrentArgIndex. It used to initialize to UINT16_MAX because that was "one less than" the first Arg's OrigArgIndex, but now that we have srets we can get NoArgIndex which happens to be UINT16_MAX. I originally tried to preserve the structure of the loop but now it just explicitly initializes instead of being clever.

[pftbest]

This new revision is not good. It crashes on CodeGen/MSP430/vararg.ll test.

[pftbest]

Sorry, not the vararg test, but this 3 tests:
CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
CodeGen/MSP430/2009-12-22-InlineAsm.ll
CodeGen/MSP430/cc_ret.ll

[asl]

lib/Target/MSP430/MSP430ISelLowering.cpp

248–256

Is there any guard preventing calling this function when we're having zero args?

[awygle]

Somehow managed to run check-all against an old version. Added obviously-required check for an empty vector. All tests now pass (and don't segfault).

[pftbest]

I can confirm that now it's passing the tests

[awygle]

Are there any further corrections that need to be made before this can be merged?

[asl]

LGTM with small change aboce

lib/Target/MSP430/MSP430ISelLowering.cpp

249

Simple early return here.

[awygle]

Great. Thank you. I've made the requested change.

[pftbest]

@asl can you please commit this change?

[pftbest]

Looks like D29916 broke this patch. Also CanLowerReturn should be marked with override to prevent compile warnings.

[awygle]

Updated to work with latest SVN.

[pftbest]

Looks good, Thank you.

lib/Target/MSP430/MSP430CallingConv.td

 //==- MSP430CallingConv.td - Calling Conventions for MSP430 -*- tablegen -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 // This describes the calling conventions for MSP430 architecture.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // MSP430 Return Value Calling Convention
 //===----------------------------------------------------------------------===//
 def RetCC_MSP430 : CallingConv<[
-  // i8 are returned in registers R15B, R14B, R13B, R12B
-  CCIfType<[i8], CCAssignToReg<[R15B, R14B, R13B, R12B]>>,
+  // i8 are returned in registers R12B, R13B, R14B, R15B
+  CCIfType<[i8], CCAssignToReg<[R12B, R13B, R14B, R15B]>>,
 
-  // i16 are returned in registers R15, R14, R13, R12
-  CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
+  // i16 are returned in registers R12, R13, R14, R15
+  CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // MSP430 Argument Calling Conventions
 //===----------------------------------------------------------------------===//
 def CC_MSP430_AssignStack : CallingConv<[
   // Pass by value if the byval attribute is given
   CCIfByVal<CCPassByVal<2, 2>>,

lib/Target/MSP430/MSP430ISelLowering.h

private:
     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                          const SmallVectorImpl<ISD::InputArg> &Ins,
                          const SDLoc &dl, SelectionDAG &DAG,
                          SmallVectorImpl<SDValue> &InVals) const override;
     SDValue
       LowerCall(TargetLowering::CallLoweringInfo &CLI,
                 SmallVectorImpl<SDValue> &InVals) const override;
 
+    bool CanLowerReturn(CallingConv::ID CallConv,
+                        MachineFunction &MF,
+                        bool IsVarArg,
+                        const SmallVectorImpl<ISD::OutputArg> &Outs,
+                        LLVMContext &Context) const;
+
     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         const SmallVectorImpl<SDValue> &OutVals,
                         const SDLoc &dl, SelectionDAG &DAG) const override;
 
     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                     SDValue &Base,
                                     SDValue &Offset,
                                     ISD::MemIndexedMode &AM,
                                     SelectionDAG &DAG) const override;
   };
 } // namespace llvm
 
 #endif

lib/Target/MSP430/MSP430ISelLowering.cpp

 //===----------------------------------------------------------------------===//
 
 #include "MSP430GenCallingConv.inc"
 
 /// For each argument in a function store the number of pieces it is composed
 /// of.
 template<typename ArgT>
 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
                               SmallVectorImpl<unsigned> &Out) {
-  unsigned CurrentArgIndex = ~0U;
-  for (unsigned i = 0, e = Args.size(); i != e; i++) {
-    if (CurrentArgIndex == Args[i].OrigArgIndex) {
-      Out.back()++;
+  unsigned CurrentArgIndex;
+  if (!Args.empty()) {
+    CurrentArgIndex = Args[0].OrigArgIndex;
+    Out.push_back(0);
+  }
+
+  for (auto &Arg : Args) {
+    if (CurrentArgIndex == Arg.OrigArgIndex) {
+      Out.back() += 1;
     } else {
       Out.push_back(1);
-      CurrentArgIndex++;
+      CurrentArgIndex = Arg.OrigArgIndex;
     }
   }
 }
 
 static void AnalyzeVarArgs(CCState &State,
                            const SmallVectorImpl<ISD::OutputArg> &Outs) {
   State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
 }
 
 static void AnalyzeVarArgs(CCState &State,
                            const SmallVectorImpl<ISD::InputArg> &Ins) {
   State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
 }
 
 /// Analyze incoming and outgoing function arguments. We need custom C++ code
 /// to handle special constraints in the ABI like reversing the order of the
 /// pieces of splitted arguments. In addition, all pieces of a certain argument
 /// have to be passed either using registers or the stack but never mixing both.
 template<typename ArgT>
 static void AnalyzeArguments(CCState &State,
                              SmallVectorImpl<CCValAssign> &ArgLocs,
                              const SmallVectorImpl<ArgT> &Args) {
   static const MCPhysReg RegList[] = {
-    MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
+    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
   };
   static const unsigned NbRegs = array_lengthof(RegList);
 
   if (State.isVarArg()) {
     AnalyzeVarArgs(State, Args);
     return;
   }
 
   SmallVector<unsigned, 4> ArgsParts;
   ParseFunctionArgs(Args, ArgsParts);
 
   unsigned RegsLeft = NbRegs;
-  bool UseStack = false;
+  bool UsedStack = false;
   unsigned ValNo = 0;
 
   for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
     MVT ArgVT = Args[ValNo].VT;
     ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
     MVT LocVT = ArgVT;
     CCValAssign::LocInfo LocInfo = CCValAssign::Full;
 
for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
     // Handle byval arguments
     if (ArgFlags.isByVal()) {
       State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
       continue;
     }
 
     unsigned Parts = ArgsParts[i];
 
-    if (!UseStack && Parts <= RegsLeft) {
-      unsigned FirstVal = ValNo;
+    if (!UsedStack && Parts == 2 && RegsLeft == 1) {
+      // Special case for 32-bit register split, see EABI section 3.3.3
+      unsigned Reg = State.AllocateReg(RegList);
+      State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
+      RegsLeft -= 1;
+
+      UsedStack = true;
+      CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
+    } else if (Parts <= RegsLeft) {
       for (unsigned j = 0; j < Parts; j++) {
         unsigned Reg = State.AllocateReg(RegList);
         State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
         RegsLeft--;
       }
-
-      // Reverse the order of the pieces to agree with the "big endian" format
-      // required in the calling convention ABI.
-      SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
-      std::reverse(B, B + Parts);
     } else {
-      UseStack = true;
+      UsedStack = true;
       for (unsigned j = 0; j < Parts; j++)
         CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
     }
   }
 }
 
 static void AnalyzeRetResult(CCState &State,
                              const SmallVectorImpl<ISD::InputArg> &Ins) {
   State.AnalyzeCallResult(Ins, RetCC_MSP430);
 }
 
 static void AnalyzeRetResult(CCState &State,
                              const SmallVectorImpl<ISD::OutputArg> &Outs) {
   State.AnalyzeReturn(Outs, RetCC_MSP430);
 }
 
 template<typename ArgT>
 static void AnalyzeReturnValues(CCState &State,
                                 SmallVectorImpl<CCValAssign> &RVLocs,
                                 const SmallVectorImpl<ArgT> &Args) {
   AnalyzeRetResult(State, Args);
-
-  // Reverse splitted return values to get the "big endian" format required
-  // to agree with the calling convention ABI.
-  std::reverse(RVLocs.begin(), RVLocs.end());
 }
 
 SDValue MSP430TargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
   switch (CallConv) {
#endif
             VA.getLocVT(), dl, Chain, FIN,
             MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
       }
 
       InVals.push_back(InVal);
     }
   }
 
+  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+    if (Ins[i].Flags.isSRet()) {
+      unsigned Reg = FuncInfo->getSRetReturnReg();
+      if (!Reg) {
+        Reg = MF.getRegInfo().createVirtualRegister(
+            getRegClassFor(MVT::i16));
+        FuncInfo->setSRetReturnReg(Reg);
+      }
+      SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
+      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
+    }
+  }
+
   return Chain;
 }
 
+bool
+MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
+                                     MachineFunction &MF,
+                                     bool IsVarArg,
+                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
+                                     LLVMContext &Context) const {
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
+  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
+}
+
 SDValue
 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                   bool isVarArg,
                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
                                   const SmallVectorImpl<SDValue> &OutVals,
                                   const SDLoc &dl, SelectionDAG &DAG) const {
 
+  MachineFunction &MF = DAG.getMachineFunction();
+
   // CCValAssign - represent the assignment of the return value to a location
   SmallVector<CCValAssign, 16> RVLocs;
 
   // ISRs cannot return any value.
   if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
     report_fatal_error("ISRs cannot return any value");
 
   // CCState - Info about the registers and stack slot.
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
                              OutVals[i], Flag);
 
     // Guarantee that all emitted copies are stuck together,
     // avoiding something bad.
     Flag = Chain.getValue(1);
     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
   }
 
+  if (MF.getFunction()->hasStructRetAttr()) {
+    MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
+    unsigned Reg = FuncInfo->getSRetReturnReg();
+
+    if (!Reg)
+      llvm_unreachable("sret virtual register not created in entry block");
+
+    SDValue Val =
+      DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
+    unsigned R12 = MSP430::R12;
+
+    Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
+    Flag = Chain.getValue(1);
+    RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
+  }
+
   unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
                   MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
 
   RetOps[0] = Chain;  // Update chain.
 
   // Add the flag if we have it.
   if (Flag.getNode())
     RetOps.push_back(Flag);

lib/Target/MSP430/MSP430MachineFunctionInfo.h

class MSP430MachineFunctionInfo : public MachineFunctionInfo {
   unsigned CalleeSavedFrameSize;
 
   /// ReturnAddrIndex - FrameIndex for return slot.
   int ReturnAddrIndex;
 
   /// VarArgsFrameIndex - FrameIndex for start of varargs area.
   int VarArgsFrameIndex;
 
+  /// SRetReturnReg - Some subtargets require that sret lowering includes
+  /// returning the value of the returned struct in a register. This field
+  /// holds the virtual register into which the sret argument is passed.
+  unsigned SRetReturnReg;
+
 public:
   MSP430MachineFunctionInfo() : CalleeSavedFrameSize(0) {}
 
   explicit MSP430MachineFunctionInfo(MachineFunction &MF)
-    : CalleeSavedFrameSize(0), ReturnAddrIndex(0) {}
+    : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {}
 
   unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; }
   void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; }
 
+  unsigned getSRetReturnReg() const { return SRetReturnReg; }
+  void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
+
   int getRAIndex() const { return ReturnAddrIndex; }
   void setRAIndex(int Index) { ReturnAddrIndex = Index; }
 
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex;}
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 };
 
 } // End llvm namespace
 
 #endif

test/CodeGen/MSP430/AddrMode-bis-rx.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define i16 @am1(i16 %x, i16* %a) nounwind {
   %1 = load i16, i16* %a
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am1:
-; CHECK:    bis.w 0(r14), r15
+; CHECK:    bis.w 0(r13), r12
 
 @foo = external global i16
 
 define i16 @am2(i16 %x) nounwind {
   %1 = load i16, i16* @foo
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am2:
-; CHECK:    bis.w &foo, r15
+; CHECK:    bis.w &foo, r12
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
 define i8 @am3(i8 %x, i16 %n) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
   %2 = load i8, i8* %1
   %3 = or i8 %2,%x
   ret i8 %3
 }
 ; CHECK-LABEL: am3:
-; CHECK:    bis.b bar(r14), r15
+; CHECK:    bis.b bar(r13), r12
 
 define i16 @am4(i16 %x) nounwind {
   %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am4:
-; CHECK:    bis.w &32, r15
+; CHECK:    bis.w &32, r12
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
   %1 = getelementptr i16, i16* %a, i16 2
   %2 = load i16, i16* %1
   %3 = or i16 %2,%x
   ret i16 %3
 }
 ; CHECK-LABEL: am5:
-; CHECK:    bis.w 4(r14), r15
+; CHECK:    bis.w 4(r13), r12
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
 
 define i16 @am6(i16 %x) nounwind {
   %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   %2 = or i16 %1,%x
   ret i16 %2
 }
 ; CHECK-LABEL: am6:
-; CHECK:    bis.w &baz+2, r15
+; CHECK:    bis.w &baz+2, r12
 
 %T = type { i16, [2 x i8] }
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
 
 define i8 @am7(i8 %x, i16 %n) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   %3= load i8, i8* %2
   %4 = or i8 %3,%x
   ret i8 %4
 }
 ; CHECK-LABEL: am7:
-; CHECK:    bis.b duh+2(r14), r15
+; CHECK:    bis.b duh+2(r13), r12
 

test/CodeGen/MSP430/AddrMode-bis-xr.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define void @am1(i16* %a, i16 %x) nounwind {
   %1 = load i16, i16* %a
   %2 = or i16 %x, %1
   store i16 %2, i16* %a
   ret void
 }
 ; CHECK-LABEL: am1:
-; CHECK:    bis.w r14, 0(r15)
+; CHECK:    bis.w r13, 0(r12)
 
 @foo = external global i16
 
 define void @am2(i16 %x) nounwind {
   %1 = load i16, i16* @foo
   %2 = or i16 %x, %1
   store i16 %2, i16* @foo
   ret void
 }
 ; CHECK-LABEL: am2:
-; CHECK:    bis.w r15, &foo
+; CHECK:    bis.w r12, &foo
 
 @bar = external global [2 x i8]
 
 define void @am3(i16 %i, i8 %x) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %i
   %2 = load i8, i8* %1
   %3 = or i8 %x, %2
   store i8 %3, i8* %1
   ret void
 }
 ; CHECK-LABEL: am3:
-; CHECK:    bis.b r14, bar(r15)
+; CHECK:    bis.b r13, bar(r12)
 
 define void @am4(i16 %x) nounwind {
   %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
   %2 = or i16 %x, %1
   store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
   ret void
 }
 ; CHECK-LABEL: am4:
-; CHECK:    bis.w r15, &32
+; CHECK:    bis.w r12, &32
 
 define void @am5(i16* %a, i16 %x) readonly {
   %1 = getelementptr inbounds i16, i16* %a, i16 2
   %2 = load i16, i16* %1
   %3 = or i16 %x, %2
   store i16 %3, i16* %1
   ret void
 }
 ; CHECK-LABEL: am5:
-; CHECK:    bis.w r14, 4(r15)
+; CHECK:    bis.w r13, 4(r12)
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer
 
 define void @am6(i16 %x) nounwind {
   %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   %2 = or i16 %x, %1
   store i16 %2, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   ret void
 }
 ; CHECK-LABEL: am6:
-; CHECK:    bis.w r15, &baz+2
+; CHECK:    bis.w r12, &baz+2
 
 %T = type { i16, [2 x i8] }
 @duh = external global %T
 
 define void @am7(i16 %n, i8 %x) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   %3 = load i8, i8* %2
   %4 = or i8 %x, %3
   store i8 %4, i8* %2
   ret void
 }
 ; CHECK-LABEL: am7:
-; CHECK:    bis.b r14, duh+2(r15)
+; CHECK:    bis.b r13, duh+2(r12)
 

test/CodeGen/MSP430/AddrMode-mov-rx.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define i16 @am1(i16* %a) nounwind {
   %1 = load i16, i16* %a
   ret i16 %1
 }
 ; CHECK-LABEL: am1:
-; CHECK:    mov.w 0(r15), r15
+; CHECK:    mov.w 0(r12), r12
 
 @foo = external global i16
 
 define i16 @am2() nounwind {
   %1 = load i16, i16* @foo
   ret i16 %1
 }
 ; CHECK-LABEL: am2:
-; CHECK:    mov.w &foo, r15
+; CHECK:    mov.w &foo, r12
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
 define i8 @am3(i16 %n) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
   %2 = load i8, i8* %1
   ret i8 %2
 }
 ; CHECK-LABEL: am3:
-; CHECK:    mov.b bar(r15), r15
+; CHECK:    mov.b bar(r12), r12
 
 define i16 @am4() nounwind {
   %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
   ret i16 %1
 }
 ; CHECK-LABEL: am4:
-; CHECK:    mov.w &32, r15
+; CHECK:    mov.w &32, r12
 
 define i16 @am5(i16* %a) nounwind {
   %1 = getelementptr i16, i16* %a, i16 2
   %2 = load i16, i16* %1
   ret i16 %2
 }
 ; CHECK-LABEL: am5:
-; CHECK:    mov.w 4(r15), r15
+; CHECK:    mov.w 4(r12), r12
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
 
 define i16 @am6() nounwind {
   %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   ret i16 %1
 }
 ; CHECK-LABEL: am6:
-; CHECK:    mov.w &baz+2, r15
+; CHECK:    mov.w &baz+2, r12
 
 %T = type { i16, [2 x i8] }
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
 
 define i8 @am7(i16 %n) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   %3= load i8, i8* %2
   ret i8 %3
 }
 ; CHECK-LABEL: am7:
-; CHECK:    mov.b duh+2(r15), r15
+; CHECK:    mov.b duh+2(r12), r12
 

test/CodeGen/MSP430/AddrMode-mov-xr.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define void @am1(i16* %a, i16 %b) nounwind {
   store i16 %b, i16* %a
   ret void
 }
 ; CHECK-LABEL: am1:
-; CHECK:    mov.w r14, 0(r15)
+; CHECK:    mov.w r13, 0(r12)
 
 @foo = external global i16
 
 define void @am2(i16 %a) nounwind {
   store i16 %a, i16* @foo
   ret void
 }
 ; CHECK-LABEL: am2:
-; CHECK:    mov.w r15, &foo
+; CHECK:    mov.w r12, &foo
 
 @bar = external global [2 x i8]
 
 define void @am3(i16 %i, i8 %a) nounwind {
   %1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %i
   store i8 %a, i8* %1
   ret void
 }
 ; CHECK-LABEL: am3:
-; CHECK:    mov.b r14, bar(r15)
+; CHECK:    mov.b r13, bar(r12)
 
 define void @am4(i16 %a) nounwind {
   store volatile i16 %a, i16* inttoptr(i16 32 to i16*)
   ret void
 }
 ; CHECK-LABEL: am4:
-; CHECK:    mov.w r15, &32
+; CHECK:    mov.w r12, &32
 
 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
   %1 = getelementptr inbounds i16, i16* %p, i16 2
   store i16 %a, i16* %1
   ret void
 }
 ; CHECK-LABEL: am5:
-; CHECK:    mov.w r14, 4(r15)
+; CHECK:    mov.w r13, 4(r12)
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
 
 define void @am6(i16 %a) nounwind {
   store i16 %a, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
   ret void
 }
 ; CHECK-LABEL: am6:
-; CHECK:    mov.w r15, &baz+2
+; CHECK:    mov.w r12, &baz+2
 
 %T = type { i16, [2 x i8] }
 @duh = external global %T
 
 define void @am7(i16 %n, i8 %a) nounwind {
   %1 = getelementptr %T, %T* @duh, i32 0, i32 1
   %2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
   store i8 %a, i8* %2
   ret void
 }
 ; CHECK-LABEL: am7:
-; CHECK:    mov.b r14, duh+2(r15)
+; CHECK:    mov.b r13, duh+2(r12)
 

test/CodeGen/MSP430/Inst16mr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define void @mov(i16 %a) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w  r15, &foo
+; CHECK: mov.w  r12, &foo
   store i16 %a, i16* @foo
   ret void
 }
 
 define void @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  r15, &foo
+; CHECK: add.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = add i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 
 define void @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  r15, &foo
+; CHECK: and.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = and i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 
 define void @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  r15, &foo
+; CHECK: bis.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = or i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 
 define void @bic(i16 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w   r15, &foo
+; CHECK: bic.w   r12, &foo
         %1 = xor i16 %m, -1
         %2 = load i16, i16* @foo
         %3 = and i16 %2, %1
         store i16 %3, i16* @foo
         ret void
 }
 
 define void @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  r15, &foo
+; CHECK: xor.w  r12, &foo
   %1 = load i16, i16* @foo
   %2 = xor i16 %a, %1
   store i16 %2, i16* @foo
   ret void
 }
 

test/CodeGen/MSP430/Inst16ri.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w  #1, r15
+; CHECK: mov.w  #1, r12
   ret i16 1
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  #1, r15
+; CHECK: add.w  #1, r12
   %1 = add i16 %a, 1
   ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  #1, r15
+; CHECK: and.w  #1, r12
   %1 = and i16 %a, 1
   ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  #1, r15
+; CHECK: bis.w  #1, r12
   %1 = or i16 %a, 1
   ret i16 %1
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  #1, r15
+; CHECK: xor.w  #1, r12
   %1 = xor i16 %a, 1
   ret i16 %1
 }

test/CodeGen/MSP430/Inst16rm.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define i16 @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  &foo, r15
+; CHECK: add.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = add i16 %a, %1
   ret i16 %2
 }
 
 define i16 @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  &foo, r15
+; CHECK: and.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = and i16 %a, %1
   ret i16 %2
 }
 
 define i16 @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  &foo, r15
+; CHECK: bis.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = or i16 %a, %1
   ret i16 %2
 }
 
 define i16  @bic(i16 %a) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w  &foo, r15
+; CHECK: bic.w  &foo, r12
         %1 = load i16, i16* @foo
         %2 = xor i16 %1, -1
         %3 = and i16 %a, %2
         ret i16 %3
 }
 
 define i16 @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  &foo, r15
+; CHECK: xor.w  &foo, r12
   %1 = load i16, i16* @foo
   %2 = xor i16 %a, %1
   ret i16 %2
 }
 

test/CodeGen/MSP430/Inst16rr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w  r14, r15
+; CHECK: mov.w  r13, r12
   ret i16 %b
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w  r14, r15
+; CHECK: add.w  r13, r12
   %1 = add i16 %a, %b
   ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  r14, r15
+; CHECK: and.w  r13, r12
   %1 = and i16 %a, %b
   ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  r14, r15
+; CHECK: bis.w  r13, r12
   %1 = or i16 %a, %b
   ret i16 %1
 }
 
 define i16 @bic(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w  r14, r15
+; CHECK: bic.w  r13, r12
         %1 = xor i16 %b, -1
         %2 = and i16 %a, %1
         ret i16 %2
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  r14, r15
+; CHECK: xor.w  r13, r12
   %1 = xor i16 %a, %b
   ret i16 %1
 }

test/CodeGen/MSP430/Inst8mr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define void @mov(i8 %a) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.b  r15, &foo
+; CHECK: mov.b  r12, &foo
   store i8 %a, i8* @foo
   ret void
 }
 
 define void @and(i8 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.b  r15, &foo
+; CHECK: and.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = and i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 
 define void @add(i8 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b  r15, &foo
+; CHECK: add.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = add i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 
 define void @bis(i8 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.b  r15, &foo
+; CHECK: bis.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = or i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 
 define void @bic(i8 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.b   r15, &foo
+; CHECK: bic.b   r12, &foo
         %1 = xor i8 %m, -1
         %2 = load i8, i8* @foo
         %3 = and i8 %2, %1
         store i8 %3, i8* @foo
         ret void
 }
 
 define void @xor(i8 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.b  r15, &foo
+; CHECK: xor.b  r12, &foo
   %1 = load i8, i8* @foo
   %2 = xor i8 %a, %1
   store i8 %2, i8* @foo
   ret void
 }
 

test/CodeGen/MSP430/Inst8ri.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.b  #1, r15
+; CHECK: mov.b  #1, r12
   ret i8 1
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b  #1, r15
+; CHECK: add.b  #1, r12
   %1 = add i8 %a, 1
   ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.b  #1, r15
+; CHECK: and.b  #1, r12
   %1 = and i8 %a, 1
   ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.b  #1, r15
+; CHECK: bis.b  #1, r12
   %1 = or i8 %a, 1
   ret i8 %1
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.b  #1, r15
+; CHECK: xor.b  #1, r12
   %1 = xor i8 %a, 1
   ret i8 %1
 }

test/CodeGen/MSP430/Inst8rm.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define i8 @add(i8 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b  &foo, r15
+; CHECK: add.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = add i8 %a, %1
   ret i8 %2
 }
 
 define i8 @and(i8 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.b  &foo, r15
+; CHECK: and.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = and i8 %a, %1
   ret i8 %2
 }
 
 define i8 @bis(i8 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.b  &foo, r15
+; CHECK: bis.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = or i8 %a, %1
   ret i8 %2
 }
 
 define i8  @bic(i8 %a) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.b  &foo, r15
+; CHECK: bic.b  &foo, r12
         %1 = load i8, i8* @foo
         %2 = xor i8 %1, -1
         %3 = and i8 %a, %2
         ret i8 %3
 }
 
 define i8 @xor(i8 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.b  &foo, r15
+; CHECK: xor.b  &foo, r12
   %1 = load i8, i8* @foo
   %2 = xor i8 %a, %1
   ret i8 %2
 }
 

test/CodeGen/MSP430/Inst8rr.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.{{[bw]}} r14, r15
+; CHECK: mov.{{[bw]}} r13, r12
   ret i8 %b
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.b
   %1 = add i8 %a, %b
   ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w  r14, r15
+; CHECK: and.w  r13, r12
   %1 = and i8 %a, %b
   ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w  r14, r15
+; CHECK: bis.w  r13, r12
   %1 = or i8 %a, %b
   ret i8 %1
 }
 
 define i8 @bic(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.b  r14, r15
+; CHECK: bic.b  r13, r12
         %1 = xor i8 %b, -1
         %2 = and i8 %a, %1
         ret i8 %2
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w  r14, r15
+; CHECK: xor.w  r13, r12
   %1 = xor i8 %a, %b
   ret i8 %1
 }
 

test/CodeGen/MSP430/bit.ll

 ; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
 @foo8 = external global i8
 @bar8 = external global i8
 
 define i8 @bitbrr(i8 %a, i8 %b) nounwind {
   %t1 = and i8 %a, %b
   %t2 = icmp ne i8 %t1, 0
   %t3 = zext i1 %t2 to i8
   ret i8 %t3
 }
 ; CHECK-LABEL: bitbrr:
-; CHECK: bit.b  r14, r15
+; CHECK: bit.b  r13, r12
 
 define i8 @bitbri(i8 %a) nounwind {
   %t1 = and i8 %a, 15
   %t2 = icmp ne i8 %t1, 0
   %t3 = zext i1 %t2 to i8
   ret i8 %t3
 }
 ; CHECK-LABEL: bitbri:
-; CHECK: bit.b  #15, r15
+; CHECK: bit.b  #15, r12
 
 define i8 @bitbir(i8 %a) nounwind {
   %t1 = and i8 15, %a
   %t2 = icmp ne i8 %t1, 0
   %t3 = zext i1 %t2 to i8
   ret i8 %t3
 }
 ; CHECK-LABEL: bitbir:
-; CHECK: bit.b  #15, r15
+; CHECK: bit.b  #15, r12
 
 define i8 @bitbmi() nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = and i8 %t1, 15
   %t3 = icmp ne i8 %t2, 0
   %t4 = zext i1 %t3 to i8
   ret i8 %t4
 }

 define i8 @bitbrm(i8 %a) nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = and i8 %a, %t1
   %t3 = icmp ne i8 %t2, 0
   %t4 = zext i1 %t3 to i8
   ret i8 %t4
 }
 ; CHECK-LABEL: bitbrm:
-; CHECK: bit.b  &foo8, r15
+; CHECK: bit.b  &foo8, r12
 
 define i8 @bitbmr(i8 %a) nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = and i8 %t1, %a
   %t3 = icmp ne i8 %t2, 0
   %t4 = zext i1 %t3 to i8
   ret i8 %t4
 }
 ; CHECK-LABEL: bitbmr:
-; CHECK: bit.b  r15, &foo8
+; CHECK: bit.b  r12, &foo8
 
 define i8 @bitbmm() nounwind {
   %t1 = load i8, i8* @foo8
   %t2 = load i8, i8* @bar8
   %t3 = and i8 %t1, %t2
   %t4 = icmp ne i8 %t3, 0
   %t5 = zext i1 %t4 to i8
   ret i8 %t5
 }
 ; CHECK-LABEL: bitbmm:
 ; CHECK: bit.b  &bar8, &foo8
 
 @foo16 = external global i16
 @bar16 = external global i16
 
 define i16 @bitwrr(i16 %a, i16 %b) nounwind {
   %t1 = and i16 %a, %b
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: bitwrr:
-; CHECK: bit.w  r14, r15
+; CHECK: bit.w  r13, r12
 
 define i16 @bitwri(i16 %a) nounwind {
   %t1 = and i16 %a, 4080
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: bitwri:
-; CHECK: bit.w  #4080, r15
+; CHECK: bit.w  #4080, r12
 
 define i16 @bitwir(i16 %a) nounwind {
   %t1 = and i16 4080, %a
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: bitwir:
-; CHECK: bit.w  #4080, r15
+; CHECK: bit.w  #4080, r12
 
 define i16 @bitwmi() nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = and i16 %t1, 4080
   %t3 = icmp ne i16 %t2, 0
   %t4 = zext i1 %t3 to i16
   ret i16 %t4
 }

 define i16 @bitwrm(i16 %a) nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = and i16 %a, %t1
   %t3 = icmp ne i16 %t2, 0
   %t4 = zext i1 %t3 to i16
   ret i16 %t4
 }
 ; CHECK-LABEL: bitwrm:
-; CHECK: bit.w  &foo16, r15
+; CHECK: bit.w  &foo16, r12
 
 define i16 @bitwmr(i16 %a) nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = and i16 %t1, %a
   %t3 = icmp ne i16 %t2, 0
   %t4 = zext i1 %t3 to i16
   ret i16 %t4
 }
 ; CHECK-LABEL: bitwmr:
-; CHECK: bit.w  r15, &foo16
+; CHECK: bit.w  r12, &foo16
 
 define i16 @bitwmm() nounwind {
   %t1 = load i16, i16* @foo16
   %t2 = load i16, i16* @bar16
   %t3 = and i16 %t1, %t2
   %t4 = icmp ne i16 %t3, 0
   %t5 = zext i1 %t4 to i16
   ret i16 %t5
 }
 ; CHECK-LABEL: bitwmm:
 ; CHECK: bit.w  &bar16, &foo16
 

test/CodeGen/MSP430/byval.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 target triple = "msp430---elf"
 
 %struct.Foo = type { i16, i16, i16 }
 @foo = global %struct.Foo { i16 1, i16 2, i16 3 }, align 2
 
 define i16 @callee(%struct.Foo* byval %f) nounwind {
 entry:
 ; CHECK-LABEL: callee:
-; CHECK: mov.w 2(r1), r15
+; CHECK: mov.w 2(r1), r12
   %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
   %1 = load i16, i16* %0, align 2
   ret i16 %1
 }
 
 define void @caller() nounwind {
 entry:
 ; CHECK-LABEL: caller:
 ; CHECK: mov.w &foo+4, 4(r1)
 ; CHECK-NEXT: mov.w &foo+2, 2(r1)
 ; CHECK-NEXT: mov.w &foo, 0(r1)
   %call = call i16 @callee(%struct.Foo* byval @foo)
   ret void
 }

test/CodeGen/MSP430/cc_args.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
 target triple = "msp430---elf"
 
 define void @test() #0 {
 entry:
 ; CHECK: test:
 
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
 ; CHECK: call #f_i16
   call void @f_i16(i16 1)
 
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
+; CHECK: mov.w #772, r12
+; CHECK: mov.w #258, r13
 ; CHECK: call #f_i32
   call void @f_i32(i32 16909060)
 
 ; CHECK: mov.w #1800, r12
 ; CHECK: mov.w #1286, r13
 ; CHECK: mov.w #772, r14
 ; CHECK: mov.w #258, r15
 ; CHECK: call #f_i64
   call void @f_i64(i64 72623859790382856)
 
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
-; CHECK: mov.w #1800, r12
-; CHECK: mov.w #1286, r13
+; CHECK: mov.w #772, r12
+; CHECK: mov.w #258, r13
+; CHECK: mov.w #1800, r14
+; CHECK: mov.w #1286, r15
 ; CHECK: call #f_i32_i32
   call void @f_i32_i32(i32 16909060, i32 84281096)
 
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
 ; CHECK: mov.w #772, r13
 ; CHECK: mov.w #258, r14
-; CHECK: mov.w #2, r12
+; CHECK: mov.w #2, r15
 ; CHECK: call #f_i16_i32_i16
   call void @f_i16_i32_i16(i16 1, i32 16909060, i16 2)
 
-; CHECK: mov.w #2, 8(r1)
+; CHECK: mov.w #1286, 0(r1)
+; CHECK: mov.w #1, r12
+; CHECK: mov.w #772, r13
+; CHECK: mov.w #258, r14
+; CHECK: mov.w #1800, r15
+; CHECK: call #f_i16_i32_i32
+  call void @f_i16_i32_i32(i16 1, i32 16909060, i32 84281096)
+  
 ; CHECK: mov.w #258, 6(r1)
 ; CHECK: mov.w #772, 4(r1)
 ; CHECK: mov.w #1286, 2(r1)
 ; CHECK: mov.w #1800, 0(r1)
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
+; CHECK: mov.w #2, r13
 ; CHECK: call #f_i16_i64_i16
   call void @f_i16_i64_i16(i16 1, i64 72623859790382856, i16 2)
 
   ret void
 }
 
 @g_i16 = common global i16 0, align 2
 @g_i32 = common global i32 0, align 2
 @g_i64 = common global i64 0, align 2
 
 define void @f_i16(i16 %a) #0 {
 ; CHECK: f_i16:
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
   ret void
 }
 
 define void @f_i32(i32 %a) #0 {
 ; CHECK: f_i32:
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
+; CHECK: mov.w r13, &g_i32+2
+; CHECK: mov.w r12, &g_i32
   store volatile i32 %a, i32* @g_i32, align 2
   ret void
 }
 
 define void @f_i64(i64 %a) #0 {
 ; CHECK: f_i64:
 ; CHECK: mov.w r15, &g_i64+6
 ; CHECK: mov.w r14, &g_i64+4
 ; CHECK: mov.w r13, &g_i64+2
 ; CHECK: mov.w r12, &g_i64
   store volatile i64 %a, i64* @g_i64, align 2
   ret void
 }
 
 define void @f_i32_i32(i32 %a, i32 %b) #0 {
 ; CHECK: f_i32_i32:
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
-  store volatile i32 %a, i32* @g_i32, align 2
 ; CHECK: mov.w r13, &g_i32+2
 ; CHECK: mov.w r12, &g_i32
+  store volatile i32 %a, i32* @g_i32, align 2
+; CHECK: mov.w r15, &g_i32+2
+; CHECK: mov.w r14, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
   ret void
 }
 
+define void @f_i16_i32_i32(i16 %a, i32 %b, i32 %c) #0 {
+; CHECK: f_i16_i32_i32:
+; CHECK: mov.w r12, &g_i16
+  store volatile i16 %a, i16* @g_i16, align 2
+; CHECK: mov.w r14, &g_i32+2
+; CHECK: mov.w r13, &g_i32
+  store volatile i32 %b, i32* @g_i32, align 2
+; CHECK: mov.w r15, &g_i32
+; CHECK: mov.w 4(r4), &g_i32+2
+  store volatile i32 %c, i32* @g_i32, align 2
+  ret void
+}
+
 define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
 ; CHECK: f_i16_i32_i16:
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
 ; CHECK: mov.w r14, &g_i32+2
 ; CHECK: mov.w r13, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov.w r15, &g_i16
   store volatile i16 %c, i16* @g_i16, align 2
   ret void
 }
 
 define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
 ; CHECK: f_i16_i64_i16:
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
 ;CHECK: mov.w 10(r4), &g_i64+6
 ;CHECK: mov.w 8(r4), &g_i64+4
 ;CHECK: mov.w 6(r4), &g_i64+2
 ;CHECK: mov.w 4(r4), &g_i64
   store volatile i64 %b, i64* @g_i64, align 2
-;CHECK: mov.w 12(r4), &g_i16
+;CHECK: mov.w r13, &g_i16
   store volatile i16 %c, i16* @g_i16, align 2
   ret void
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/MSP430/cc_ret.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
 target triple = "msp430---elf"
 
 define void @test() #0 {
 entry:
 ; CHECK: test:
 
 ; CHECK: call #f_i16
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov.w r12, &g_i16
   %0 = call i16 @f_i16()
   store volatile i16 %0, i16* @g_i16
 
 ; CHECK: call #f_i32
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
+; CHECK: mov.w r13, &g_i32+2
+; CHECK: mov.w r12, &g_i32
   %1 = call i32 @f_i32()
   store volatile i32 %1, i32* @g_i32
 
 ; CHECK: call #f_i64
 ; CHECK: mov.w r15, &g_i64+6
 ; CHECK: mov.w r14, &g_i64+4
 ; CHECK: mov.w r13, &g_i64+2
 ; CHECK: mov.w r12, &g_i64
   %2 = call i64 @f_i64()
   store volatile i64 %2, i64* @g_i64
 
   ret void
 }
 
 @g_i16 = common global i16 0, align 2
 @g_i32 = common global i32 0, align 2
 @g_i64 = common global i64 0, align 2
 
 define i16 @f_i16() #0 {
 ; CHECK: f_i16:
-; CHECK: mov.w #1, r15
+; CHECK: mov.w #1, r12
 ; CHECK: ret
   ret i16 1
 }
 
 define i32 @f_i32() #0 {
 ; CHECK: f_i32:
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
+; CHECK: mov.w #772, r12
+; CHECK: mov.w #258, r13
 ; CHECK: ret
   ret i32 16909060
 }
 
 define i64 @f_i64() #0 {
 ; CHECK: f_i64:
 ; CHECK: mov.w #1800, r12
 ; CHECK: mov.w #1286, r13
 ; CHECK: mov.w #772, r14
 ; CHECK: mov.w #258, r15
 ; CHECK: ret
   ret i64 72623859790382856
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/MSP430/indirectbr2.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i16 @foo(i16 %i) nounwind {
 entry:
   %tmp1 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
   %gotovar.4.0 = load i8*, i8** %tmp1, align 4        ; <i8*> [#uses=1]
-; CHECK: br .LC.0.2070(r12)
+; CHECK: br .LC.0.2070(r13)
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 L5:                                               ; preds = %bb2
   br label %L4
 
 L4:                                               ; preds = %L5, %bb2
   %res.0 = phi i16 [ 385, %L5 ], [ 35, %entry ]     ; <i16> [#uses=1]
   br label %L3

test/CodeGen/MSP430/jumptable.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 target triple = "msp430---elf"
 
 ; Function Attrs: nounwind
 define i16 @test(i16 %i) #0 {
 entry:
 ; CHECK-LABEL: test:
   %retval = alloca i16, align 2
   %i.addr = alloca i16, align 2
   store i16 %i, i16* %i.addr, align 2
   %0 = load i16, i16* %i.addr, align 2
-; CHECK: mov.w #2, r14
+; CHECK: mov.w #2, r13
 ; CHECK: call #__mulhi3hw_noint
-; CHECK: br .LJTI0_0(r15)
+; CHECK: br .LJTI0_0(r12)
   switch i16 %0, label %sw.default [
     i16 0, label %sw.bb
     i16 1, label %sw.bb1
     i16 2, label %sw.bb2
     i16 3, label %sw.bb3
   ]
 
 sw.bb:                                            ; preds = %entry

test/CodeGen/MSP430/memset.ll

 ; RUN: llc < %s | FileCheck %s
 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 target triple = "msp430---elf"
 
 @buf = external global i8*
 
 ; Function Attrs: nounwind
 define void @test() nounwind {
 entry:
 ; CHECK-LABEL: test:
   %0 = load i8*, i8** @buf, align 2
-; CHECK: mov.w &buf, r15
-; CHECK-NEXT: mov.w #5, r14
-; CHECK-NEXT: mov.w #128, r13
+; CHECK: mov.w &buf, r12
+; CHECK-NEXT: mov.w #5, r13
+; CHECK-NEXT: mov.w #128, r14
 ; CHECK-NEXT: call #memset
   call void @llvm.memset.p0i8.i16(i8* %0, i8 5, i16 128, i32 1, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind
 declare void @llvm.memset.p0i8.i16(i8* nocapture, i8, i16, i32, i1) nounwind
 

test/CodeGen/MSP430/setcc.ll

 ; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
 define i16 @sccweqand(i16 %a, i16 %b) nounwind {
   %t1 = and i16 %a, %b
   %t2 = icmp eq i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: sccweqand:
-; CHECK:  bit.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  rra.w   r15
-; CHECK:  and.w #1, r15
+; CHECK:  bit.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  rra.w   r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwneand(i16 %a, i16 %b) nounwind {
   %t1 = and i16 %a, %b
   %t2 = icmp ne i16 %t1, 0
   %t3 = zext i1 %t2 to i16
   ret i16 %t3
 }
 ; CHECK-LABEL: sccwneand:
-; CHECK:  bit.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  and.w #1, r15
+; CHECK:  bit.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwne(i16 %a, i16 %b) nounwind {
   %t1 = icmp ne i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwne:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w r2, r12
-; CHECK:  rra.w r12
-; CHECK:  mov.w #1, r15
-; CHECK:  bic.w r12, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w r2, r13
+; CHECK:  rra.w r13
+; CHECK:  mov.w #1, r12
+; CHECK:  bic.w r13, r12
 
 define i16 @sccweq(i16 %a, i16 %b) nounwind {
   %t1 = icmp eq i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccweq:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  rra.w r15
-; CHECK:  and.w #1, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  rra.w r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwugt(i16 %a, i16 %b) nounwind {
   %t1 = icmp ugt i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwugt:
-; CHECK:  cmp.w r15, r14
-; CHECK:  mov.w #1, r15
-; CHECK:  bic.w r2, r15
+; CHECK:  cmp.w r12, r13
+; CHECK:  mov.w #1, r12
+; CHECK:  bic.w r2, r12
 
 define i16 @sccwuge(i16 %a, i16 %b) nounwind {
   %t1 = icmp uge i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwuge:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w r2, r15
-; CHECK:  and.w #1, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w r2, r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwult(i16 %a, i16 %b) nounwind {
   %t1 = icmp ult i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwult:
-; CHECK:  cmp.w r14, r15
-; CHECK:  mov.w #1, r15
-; CHECK:  bic.w r2, r15
+; CHECK:  cmp.w r13, r12
+; CHECK:  mov.w #1, r12
+; CHECK:  bic.w r2, r12
 
 define i16 @sccwule(i16 %a, i16 %b) nounwind {
   %t1 = icmp ule i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 ; CHECK-LABEL:sccwule:
-; CHECK:  cmp.w r15, r14
-; CHECK:  mov.w r2, r15
-; CHECK:  and.w #1, r15
+; CHECK:  cmp.w r12, r13
+; CHECK:  mov.w r2, r12
+; CHECK:  and.w #1, r12
 
 define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
   %t1 = icmp sgt i16 %a, %b
   %t2 = zext i1 %t1 to i16
   ret i16 %t2
 }
 
 define i16 @sccwsge(i16 %a, i16 %b) nounwind {

test/CodeGen/MSP430/vararg.ll

; CHECK-NEXT: mov.w [[REG]], 0(r1)
   call void @llvm.va_end(i8* %vl1)
   ret void
 }
 
 define i16 @va_arg(i8* %vl) nounwind {
 entry:
 ; CHECK-LABEL: va_arg:
   %vl.addr = alloca i8*, align 2
-; CHECK: mov.w r15, 0(r1)
+; CHECK: mov.w r12, 0(r1)
   store i8* %vl, i8** %vl.addr, align 2
-; CHECK: mov.w r15, [[REG:r[0-9]+]]
+; CHECK: mov.w r12, [[REG:r[0-9]+]]
 ; CHECK-NEXT: add.w #2, [[REG]]
 ; CHECK-NEXT: mov.w [[REG]], 0(r1)
   %0 = va_arg i8** %vl.addr, i16
-; CHECK-NEXT: mov.w 0(r15), r15
+; CHECK-NEXT: mov.w 0(r12), r12
   ret i16 %0
 }
 
 define void @va_copy(i8* %vl) nounwind {
 entry:
 ; CHECK-LABEL: va_copy:
   %vl.addr = alloca i8*, align 2
   %vl2 = alloca i8*, align 2
-; CHECK: mov.w r15, 2(r1)
+; CHECK: mov.w r12, 2(r1)
   store i8* %vl, i8** %vl.addr, align 2
   %0 = bitcast i8** %vl2 to i8*
   %1 = bitcast i8** %vl.addr to i8*
-; CHECK-NEXT: mov.w r15, 0(r1)
+; CHECK-NEXT: mov.w r12, 0(r1)
   call void @llvm.va_copy(i8* %0, i8* %1)
   ret void
 }