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Differential D27644

Bail out for reduceVMULWidth for illegal types
AbandonedPublic

Authored by wmi on Dec 9 2016, 5:02 PM.

Details

Reviewers
RKSimon
mkuper
Summary

This is a temp workaround for PR31323. I will come up a following patch to address illegal types better.

Diff Detail

Repository
rL LLVM

Event Timeline

wmi updated this revision to Diff 80978.Dec 9 2016, 5:02 PM
wmi retitled this revision from to Bail out for reduceVMULWidth for illegal types.
wmi updated this object.
wmi added reviewers: mkuper, RKSimon.
wmi set the repository for this revision to rL LLVM.
wmi added a subscriber: llvm-commits.
mkuper edited edge metadata.Dec 9 2016, 5:05 PM

Hasn't Simon already committed an equivalent workaround in r289232?

wmi abandoned this revision.Dec 9 2016, 5:09 PM

Revision Contents

PathSize
lib/
Target/
X86/
6 lines
test/
CodeGen/
X86/
24 lines

Diff 80978

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 29,321 Lines • ▼ Show 20 Linesstatic SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
SDLoc DL(N); SDLoc DL(N);
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1); SDValue N1 = N->getOperand(1);
EVT VT = N->getOperand(0).getValueType(); EVT VT = N->getOperand(0).getValueType();
unsigned RegSize = 128; unsigned RegSize = 128;
MVT OpsVT = MVT::getVectorVT(MVT::i16, RegSize / 16); MVT OpsVT = MVT::getVectorVT(MVT::i16, RegSize / 16);
EVT ReducedVT = EVT ReducedVT =
EVT::getVectorVT(*DAG.getContext(), MVT::i16, VT.getVectorNumElements()); EVT::getVectorVT(*DAG.getContext(), MVT::i16, VT.getVectorNumElements());
// FIXME: Type like 3 x i8 cannot be properly handled. Bail out here to
// workaround the bug. It should be fixed soon in a following patch.
if (RegSize % ReducedVT.getSizeInBits() != 0)
return SDValue();
// Shrink the operands of mul. // Shrink the operands of mul.
SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0); SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0);
SDValue NewN1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N1); SDValue NewN1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N1);
if (VT.getVectorNumElements() >= OpsVT.getVectorNumElements()) { if (VT.getVectorNumElements() >= OpsVT.getVectorNumElements()) {
// Generate the lower part of mul: pmullw. For MULU8/MULS8, only the // Generate the lower part of mul: pmullw. For MULU8/MULS8, only the
// lower part is needed. // lower part is needed.
SDValue MulLo = DAG.getNode(ISD::MUL, DL, ReducedVT, NewN0, NewN1); SDValue MulLo = DAG.getNode(ISD::MUL, DL, ReducedVT, NewN0, NewN1);
▲ Show 20 Lines • Show All 4,763 Lines • Show Last 20 Lines

test/CodeGen/X86/shrink_vmul_illtype.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2
; PR31323: reduceVMULWidth doesn't handle illegal vector types like <3 x i8> or <5 x i16> correctly.
; For now, give up if such illegal vector types are seen.
@c = external global i32*, align 8
define void @mul_3xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64 %index) {
entry:
%pre = load i32*, i32** @c
%tmp6 = getelementptr inbounds i8, i8* %a, i64 %index
%tmp7 = bitcast i8* %tmp6 to <3 x i8>*
%wide.load = load <3 x i8>, <3 x i8>* %tmp7, align 1
%tmp8 = zext <3 x i8> %wide.load to <3 x i32>
%tmp10 = getelementptr inbounds i8, i8* %b, i64 %index
%tmp11 = bitcast i8* %tmp10 to <3 x i8>*
%wide.load17 = load <3 x i8>, <3 x i8>* %tmp11, align 1
%tmp12 = zext <3 x i8> %wide.load17 to <3 x i32>
%tmp13 = mul nuw nsw <3 x i32> %tmp12, %tmp8
%tmp14 = getelementptr inbounds i32, i32* %pre, i64 %index
%tmp15 = bitcast i32* %tmp14 to <3 x i32>*
store <3 x i32> %tmp13, <3 x i32>* %tmp15, align 4
ret void
}