Fix per-processor model scheduler definition completeness check

[uweigand]

Summary

The CodeGenSchedModels::checkCompleteness routine in TableGen/CodeGenSchedule.cpp is supposed to verify for each processor model that is marked as "complete" that it actually defines a scheduling class for each instruction.

However, we had noticed a while ago (as pointed out in comments to D17260), that this doesn't actually appear to work. I've now identified the reason for this:

if (SC.ItinClassDef != nullptr)
  continue;

This is apparently supposed to skip the processor model verification if the scheduling class defines an itinerary. However, the SC.ItinClassDef pointer never seems to be null; instead, for scheduling classes without itinerary, it points to a special "NoItinerary" record. Other places in the code check for that record instead.

By changing checkCompleteness to do the same, the completeness check now works. (It actually found a couple of problems in the SystemZ back-end, which have now been fixed in commits 288576 and 288577.

[atrick]

Thanks. This is great, as long as you tested all in-tree targets.

[uweigand]

Yes, the in-tree targets all look good.

llvm/trunk/utils/TableGen/CodeGenSchedule.cpp

for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
           Complete = false;
         }
         continue;
       }
 
       const CodeGenSchedClass &SC = getSchedClass(SCIdx);
       if (!SC.Writes.empty())
         continue;
-      if (SC.ItinClassDef != nullptr)
+      if (SC.ItinClassDef != nullptr &&
+          SC.ItinClassDef->getName() != "NoItinerary")
         continue;
 
       const RecVec &InstRWs = SC.InstRWs;
       auto I = find_if(InstRWs, [&ProcModel](const Record *R) {
         return R->getValueAsDef("SchedModel") == ProcModel.ModelDef;
       });
       if (I == InstRWs.end()) {
         PrintError("'" + ProcModel.ModelName + "' lacks information for '" +