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Differential D22580

Fix bug in clearance calculation
ClosedPublic

Authored by myatsina on Jul 20 2016, 12:28 PM.

Details

Reviewers
mkuper
Commits
rGc1fa163392f5: ExecutionDepsFix - Fix bug in clearance calculation
rL276266: ExecutionDepsFix - Fix bug in clearance calculation
Summary

The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.

Diff Detail

Event Timeline

myatsina updated this revision to Diff 64727.Jul 20 2016, 12:28 PM
myatsina retitled this revision from to Fix bug in clearance calculation.
myatsina updated this object.
myatsina added a reviewer: mkuper.
myatsina added a subscriber: llvm-commits.
mkuper accepted this revision.Jul 20 2016, 12:40 PM
mkuper edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jul 20 2016, 12:40 PM
Closed by commit rL276266: ExecutionDepsFix - Fix bug in clearance calculation (authored by myatsina). · Explain WhyJul 21 2016, 5:44 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
CodeGen/
2 lines
test/
CodeGen/
X86/
10 lines

Diff 64727

lib/CodeGen/ExecutionDepsFix.cpp

Show First 20 Lines • Show All 514 Lines • ▼ Show 20 Linesvoid ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
} }
const MCInstrDesc &MCID = MI->getDesc(); const MCInstrDesc &MCID = MI->getDesc();
for (unsigned i = 0, for (unsigned i = 0,
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
i != e; ++i) { i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
if (MO.isImplicit())
break;
if (MO.isUse()) if (MO.isUse())
continue; continue;
for (int rx : regIndices(MO.getReg())) { for (int rx : regIndices(MO.getReg())) {
// This instruction explicitly defines rx. // This instruction explicitly defines rx.
DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
<< '\t' << *MI); << '\t' << *MI);
// Check clearance before partial register updates. // Check clearance before partial register updates.
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines

test/CodeGen/X86/break-false-dep.ll

Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
;AVX-LABEL:@loopdep3 ;AVX-LABEL:@loopdep3
;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]] ;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmovsd [[XMM0]], ;AVX-NEXT: vmovsd [[XMM0]],
} }
define double @inlineasmdep(i64 %arg) {
top:
tail call void asm sideeffect "", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
%tmp1 = sitofp i64 %arg to double
ret double %tmp1
;AVX-LABEL:@inlineasmdep
;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]], [[XMM0]]
;AVX-NEXT: vcvtsi2sdq {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
}