ARM: Add -m[no-]crc to dis/enable CRC subtargetfeature from clang

[bogden]

Summary

Builds on llvm patch to allow users to disable or enable CRC subtarget feature.

Depends on D2036.

[rengolin]

Hi Bernie,

Looks good to me, thanks for removing "if arch == N" checks from the code. ;)

--renato

[bogden]

Closed by commit rL193600 (authored by @bogden).

cfe/trunk/docs/UsersManual.rst

.. option:: -mhwdiv=[values]
    Select the ARM modes (arm or thumb) that support hardware division
    instructions.
 
    Valid values are: ``arm``, ``thumb`` and ``arm,thumb``.
    This option is used to indicate which mode (arm or thumb) supports
    hardware division instructions. This only applies to the ARM
    architecture.
 
+.. option:: -m[no-]crc
+
+   Enable or disable CRC instructions.
+
+   This option is used to indicate whether CRC instructions are to
+   be generated. This only applies to the ARM architecture.
+
+   CRC instructions are enabled by default on ARMv8.
+
 
 Controlling Size of Debug Information
 -------------------------------------
 
 Debug info kind generated by Clang can be set by one of the flags listed
 below. If multiple flags are present, the last one is used.
 
 .. option:: -g0

cfe/trunk/include/clang/Driver/Options.td

 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_arm_Features_Group>,
   HelpText<"Force all memory accesses to be aligned (ARM only)">;
 def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (ARM only, same as mno-unaligned-access)">;
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
 def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,
   HelpText<"Reserve the r9 register (ARM only)">;
+def mcrc : Flag<["-"], "mcrc">, Group<m_arm_Features_Group>,
+  HelpText<"Allow use of CRC instructions (ARM only)">;
+def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>,
+  HelpText<"Disallow use of CRC instructions (ARM only)">;
 
 def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>;
 def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>;
 def mfprnd : Flag<["-"], "mfprnd">, Group<m_ppc_Features_Group>;
 def mno_fprnd : Flag<["-"], "mno-fprnd">, Group<m_ppc_Features_Group>;
 def mmfcrf : Flag<["-"], "mmfcrf">, Group<m_ppc_Features_Group>;
 def mno_mfcrf : Flag<["-"], "mno-mfcrf">, Group<m_ppc_Features_Group>;
 def mpopcntd : Flag<["-"], "mpopcntd">, Group<m_ppc_Features_Group>;

cfe/trunk/lib/Basic/Targets.cpp

class ARMTargetInfo : public TargetInfo {
   unsigned IsAAPCS : 1;
   unsigned IsThumb : 1;
   unsigned HWDiv : 2;
 
   // Initialized via features.
   unsigned SoftFloat : 1;
   unsigned SoftFloatABI : 1;
 
+  unsigned CRC : 1;
+
   static const Builtin::Info BuiltinInfo[];
 
   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
     // On linux, binaries targeting old cpus call functions in libgcc to
     // perform atomic operations. The implementation in libgcc then calls into
     // the kernel which on armv6 and newer uses ldrex and strex. The net result
     // is that if we assume the kernel is at least as recent as the hardware,
     // it is safe to use atomic instructions on armv6 and newer.
else if (CPU == "cortex-a5") {
       Features["neon"] = true;
       Features["hwdiv"] = true;
       Features["hwdiv-arm"] = true;
     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
       Features["fp-armv8"] = true;
       Features["neon"] = true;
       Features["hwdiv"] = true;
       Features["hwdiv-arm"] = true;
+      Features["crc"] = true;
     } else if (CPU == "cortex-r5" || CPU == "cortex-m3" ||
                CPU == "cortex-m4" ||
                // Enable the hwdiv extension for all v8a AArch32 cores by
                // default.
                ArchName == "armv8a" || ArchName == "armv8" ||
                ArchName == "thumbv8a" || ArchName == "thumbv8") {
       Features["hwdiv"] = true;
       Features["hwdiv-arm"] = true;
     }
   }
 
   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
                                     DiagnosticsEngine &Diags) {
     FPU = 0;
+    CRC = 0;
     SoftFloat = SoftFloatABI = false;
     HWDiv = 0;
     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
       if (Features[i] == "+soft-float")
         SoftFloat = true;
       else if (Features[i] == "+soft-float-abi")
         SoftFloatABI = true;
       else if (Features[i] == "+vfp2")
         FPU |= VFP2FPU;
       else if (Features[i] == "+vfp3")
         FPU |= VFP3FPU;
       else if (Features[i] == "+vfp4")
         FPU |= VFP4FPU;
       else if (Features[i] == "+fp-armv8")
         FPU |= FPARMV8;
       else if (Features[i] == "+neon")
         FPU |= NeonFPU;
       else if (Features[i] == "+hwdiv")
         HWDiv |= HWDivThumb;
       else if (Features[i] == "+hwdiv-arm")
         HWDiv |= HWDivARM;
+      else if (Features[i] == "+crc")
+        CRC = 1;
     }
 
     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
       return false;
     }
 
     if (FPMath == FP_Neon)
virtual void getTargetDefines(const LangOptions &Opts,
     
     // This only gets set when Neon instructions are actually available, unlike
     // the VFP define, hence the soft float and arch check. This is subtly
     // different from gcc, we follow the intent which was that it should be set
     // when Neon instructions are actually available.
     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7)
       Builder.defineMacro("__ARM_NEON__");
 
-    if (CPUArchVer == 8)
+    if (CRC)
       Builder.defineMacro("__ARM_FEATURE_CRC32");
 
     if (CPUArchVer >= 6 && CPUArch != "6M") {
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
     }

cfe/trunk/lib/Driver/Tools.cpp

if (const Arg *A = Args.getLastArg(options::OPT_mfpu_EQ))
     getARMFPUFeatures(D, A, Args, Features);
   if (const Arg *A = Args.getLastArg(options::OPT_mhwdiv_EQ))
     getARMHWDivFeatures(D, A, Args, Features);
 
   // Setting -msoft-float effectively disables NEON because of the GCC
   // implementation, although the same isn't true of VFP or VFP3.
   if (FloatABI == "soft")
     Features.push_back("-neon");
+
+  // En/disable crc
+  if (Arg *A = Args.getLastArg(options::OPT_mcrc,
+                               options::OPT_mnocrc)) {
+    if (A->getOption().matches(options::OPT_mcrc))
+      Features.push_back("+crc");
+    else
+      Features.push_back("-crc");
+  }
 }
 
 void Clang::AddARMTargetArgs(const ArgList &Args,
                              ArgStringList &CmdArgs,
                              bool KernelOrKext) const {
   const Driver &D = getToolChain().getDriver();
   // Get the effective triple, which takes into account the deployment target.
   std::string TripleStr = getToolChain().ComputeEffectiveClangTriple(Args);

cfe/trunk/test/Driver/arm-mfpu.c

 // RUN: %clang -target armv8 -mfpu=fp-armv8 %s -### 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-ARMV8-SOFT-FLOAT %s
 // CHECK-ARMV8-SOFT-FLOAT: "-target-feature" "+fp-armv8"
 // CHECK-ARMV8-SOFT-FLOAT: "-target-feature" "-crypto"
 // CHECK-ARMV8-SOFT-FLOAT: "-target-feature" "-neon"
 
 // RUN: %clang -target armv8-linux-gnueabihf -mfpu=fp-armv8 %s -### 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-FP-ARMV8 %s
+// CHECK-FP-ARMV8-NOT: "-target-feature" "+neon"
 // CHECK-FP-ARMV8: "-target-feature" "+fp-armv8"
 // CHECK-FP-ARMV8: "-target-feature" "-neon"
 // CHECK-FP-ARMV8: "-target-feature" "-crypto"
 
 // RUN: %clang -target armv8-linux-gnueabihf -mfpu=neon-fp-armv8 %s -### 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NEON-FP-ARMV8 %s
 // CHECK-NEON-FP-ARMV8: "-target-feature" "+fp-armv8"
 // CHECK-NEON-FP-ARMV8: "-target-feature" "+neon"

cfe/trunk/test/Driver/armv8-crc.c

+// RUN: %clang -target armv8 -mcrc -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-V8-CRC < %t %s
+// CHECK-V8-CRC: "-target-feature" "+crc"
+
+// RUN: %clang -target armv8 -mnocrc -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-V8-NOCRC < %t %s
+// CHECK-V8-NOCRC: "-target-feature" "-crc"
+

cfe/trunk/test/Preprocessor/arm-target-features.c

 // CHECK-V8-BAREHF-FP-NOT: __ARM_NEON__ 1
 // CHECK-V8-BAREHF-FP: __VFP_FP__ 1
 
 // RUN: %clang -target armv8a -mfloat-abi=hard -mfpu=neon-fp-armv8 -x c -E -dM %s | FileCheck --check-prefix=CHECK-V8-BAREHF-NEON-FP %s
 // RUN: %clang -target armv8a -mfloat-abi=hard -mfpu=crypto-neon-fp-armv8 -x c -E -dM %s | FileCheck --check-prefix=CHECK-V8-BAREHF-NEON-FP %s
 // CHECK-V8-BAREHF-NEON-FP: __ARM_NEON__ 1
 // CHECK-V8-BAREHF-NEON-FP: __VFP_FP__ 1
 
+// RUN: %clang -target armv8a -mnocrc -x c -E -dM %s | FileCheck --check-prefix=CHECK-V8-NOCRC %s
+// CHECK-V8-NOCRC-NOT: __ARM_FEATURE_CRC32 1
+
 // Check that -mhwdiv works properly for armv8/thumbv8 (enabled by default).
 
 // RUN: %clang -target armv8 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8 %s
 // ARMV8:#define __ARM_ARCH_EXT_IDIV__ 1
 
 // RUN: %clang -target armv8 -mthumb -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBV8 %s
 // THUMBV8:#define __ARM_ARCH_EXT_IDIV__ 1