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Sparc Add previously unsupported conditional testing for co-processor and traps.
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Authored by lero_chris on Mar 8 2016, 7:15 AM.

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Summary

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5".

The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided.

The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals.

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Event Timeline

lero_chris updated this revision to Diff 50041.Mar 8 2016, 7:15 AM
lero_chris retitled this revision from to Sparc Add previously unsupported conditional testing for co-processor and traps..
lero_chris updated this object.
lero_chris added a reviewer: jyknight.
lero_chris set the repository for this revision to rL LLVM.
lero_chris accepted this revision.Mar 22 2016, 3:34 AM
lero_chris added a reviewer: lero_chris.
This revision is now accepted and ready to land.Mar 22 2016, 3:34 AM
lero_chris closed this revision.Mar 22 2016, 3:34 AM

Closed, as well embedded into the codebase at this time.