Refactor: Simplify boolean conditional return statements in lib/Target/X86

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

228 ↗

(On Diff #26414)

Indent to start after the opening parenthese on the previous line.

lib/Target/X86/X86ISelLowering.cpp

2503

Push the negate through

4116

Push the negate through

lib/Target/X86/X86InstrInfo.cpp

2488–2489

Push negate through and fix indentation on second line.

4267

Fix indentation

[LegalizeAdulthood]

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

228 ↗

(On Diff #26414)

Fixed.

lib/Target/X86/X86ISelLowering.cpp

2503

Fixed.

4116

Fixed.

lib/Target/X86/X86InstrInfo.cpp

2488–2489

Fixed.

4267

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

Update from latest.
I do not have commit access.

[bruno]

lib/Target/X86/X86ISelLowering.cpp

3643

The curly braces are useless now, you should also remove them.

lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::selectScalarSSELoad(SDNode *Root,
                                           SDValue &PatternNodeWithChain) {
   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     PatternNodeWithChain = N.getOperand(0);
     if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
         PatternNodeWithChain.hasOneUse() &&
         IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
         IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
       LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
-      if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
-        return false;
-      return true;
+      return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp,
+                        Segment);
     }
   }
 
   // Also handle the case where we explicitly require zeros in the top
   // elements.  This is a vector shuffle from the zero vector.
   if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
       // Check to see if the top elements are all zeros (or bitcast of zeros).
       N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
if (Chain == Load.getValue(1)) {
     }
 
     if (ChainCheck)
       // Make a new TokenFactor with all the other input chains except
       // for the load.
       InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
                                    MVT::Other, ChainOps);
   }
-  if (!ChainCheck)
-    return false;
-
-  return true;
+  return ChainCheck;
 }
 
 /// Get the appropriate X86 opcode for an in-memory increment or decrement.
 /// Opc should be X86ISD::DEC or X86ISD::INC.
 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
   if (Opc == X86ISD::DEC) {
     if (LdVT == MVT::i64) return X86::DEC64m;
     if (LdVT == MVT::i32) return X86::DEC32m;

lib/Target/X86/X86ISelLowering.cpp

 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
   auto Attr =
       CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
   if (!CI->isTailCall() || Attr.getValueAsString() == "true")
     return false;
 
   CallSite CS(CI);
   CallingConv::ID CalleeCC = CS.getCallingConv();
-  if (!mayTailCallThisCC(CalleeCC))
-    return false;
-
-  return true;
+  return mayTailCallThisCC(CalleeCC);
 }
 
 SDValue
 X86TargetLowering::LowerMemArgument(SDValue Chain,
                                     CallingConv::ID CallConv,
                                     const SmallVectorImpl<ISD::InputArg> &Ins,
                                     SDLoc dl, SelectionDAG &DAG,
                                     const CCValAssign &VA,
bool X86TargetLowering::IsEligibleForTailCallOptimization(
 
   // Win64 functions have extra shadow space for argument homing. Don't do the
   // sibcall if the caller and callee have mismatched expectations for this
   // space.
   if (IsCalleeWin64 != IsCallerWin64)
     return false;
 
   if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
-    if (canGuaranteeTCO(CalleeCC) && CCMatch)
-      return true;
-    return false;
+    return canGuaranteeTCO(CalleeCC) && CCMatch;
   }
 
   // Look for obvious safe cases to perform tail call optimization that do not
   // require ABI changes. This is what gcc calls sibcall.
 
   // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
   // emit a special epilogue.
   const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
   if (RegInfo->needsStackRealignment(MF))

 
 /// \brief Returns true if it is beneficial to convert a load of a constant
 /// to just the constant itself.
 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                           Type *Ty) const {
   assert(Ty->isIntegerTy());
 
   unsigned BitSize = Ty->getPrimitiveSizeInBits();
-  if (BitSize == 0 || BitSize > 64)
-    return false;
-  return true;
+  return !(BitSize == 0 || BitSize > 64);
 }
 
 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
                                                 unsigned Index) const {
   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
     return false;
 
   return (Index == 0 || Index == ResVT.getVectorNumElements());

lib/Target/X86/X86InstrInfo.cpp

bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
 
   // For both LEA64 and LEA32 the register already has essentially the right
   // type (32-bit or 64-bit) we may just need to forbid SP.
   if (Opc != X86::LEA64_32r) {
     NewSrc = SrcReg;
     isKill = Src.isKill();
     isUndef = Src.isUndef();
 
-    if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
-        !MF.getRegInfo().constrainRegClass(NewSrc, RC))
-      return false;
-
-    return true;
+    return !(TargetRegisterInfo::isVirtualRegister(NewSrc) &&
+             !MF.getRegInfo().constrainRegClass(NewSrc, RC));
   }
 
   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
   // another we need to add 64-bit registers to the final MI.
   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
     ImplicitOp = Src;
     ImplicitOp.setImplicit();
 
if (((FlagI->getOpcode() == X86::CMP64rr &&
         OI->getOpcode() == X86::SUB8rr)) &&
       ((OI->getOperand(1).getReg() == SrcReg &&
         OI->getOperand(2).getReg() == SrcReg2) ||
        (OI->getOperand(1).getReg() == SrcReg2 &&
         OI->getOperand(2).getReg() == SrcReg)))
     return true;
 
   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
         OI->getOpcode() == X86::SUB64ri32) ||
        (FlagI->getOpcode() == X86::CMP64ri8 &&
         OI->getOpcode() == X86::SUB64ri8) ||
        (FlagI->getOpcode() == X86::CMP32ri &&
         OI->getOpcode() == X86::SUB32ri) ||
        (FlagI->getOpcode() == X86::CMP32ri8 &&
         OI->getOpcode() == X86::SUB32ri8) ||
        (FlagI->getOpcode() == X86::CMP16ri &&
         OI->getOpcode() == X86::SUB16ri) ||