Refactor: Simplify boolean conditional return statements in llvm/lib/CodeGen

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements.

[craig.topper]

lib/CodeGen/MachineLICM.cpp

946–947

Push the negate through

lib/CodeGen/PseudoSourceValue.cpp

97–98

Push the negate through and use ANDs

lib/CodeGen/TargetInstrInfo.cpp

202

Push the negate through

[LegalizeAdulthood]

lib/CodeGen/MachineLICM.cpp

946–947

Fixed.

lib/CodeGen/PseudoSourceValue.cpp

97–98

Fixed.

lib/CodeGen/TargetInstrInfo.cpp

202

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[MatzeB]

There's still two instances where you can push the negation to the leafs of the expression:

lib/CodeGen/Analysis.cpp

364–365

return BitsProvided >= BitsRequired &&

(AllowDifferingSizes || BitsProvided == BitsRequired);

lib/CodeGen/CodeGenPrepare.cpp

2285

return !isa<SelectInst>(Inst) || OpIdx != 0;

lib/CodeGen/Analysis.cpp

static bool slotOnlyDiscardsData(const Value *RetVal, const Value *CallVal,
   // same value.
   if (CallVal != RetVal || CallIndices != RetIndices)
     return false;
 
   // However, intervening truncates may have made the call non-tail. Make sure
   // all the bits that are needed by the "ret" have been provided by the "tail
   // call". FIXME: with sufficiently cunning bit-tracking, we could look through
   // extensions too.
-  if (BitsProvided < BitsRequired ||
-      (!AllowDifferingSizes && BitsProvided != BitsRequired))
-    return false;
-
-  return true;
+  return !(BitsProvided < BitsRequired ||
+           (!AllowDifferingSizes && BitsProvided != BitsRequired));
 }
 
 /// For an aggregate type, determine whether a given index is within bounds or
 /// not.
 static bool indexReallyValid(CompositeType *T, unsigned Idx) {
   if (ArrayType *AT = dyn_cast<ArrayType>(T))
     return Idx < AT->getNumElements();
 

lib/CodeGen/BranchFolding.cpp

static bool ProfitableToMerge(MachineBasicBlock *MBB1,
   if (EffectiveTailLen >= minCommonTailLength)
     return true;
 
   // If we are optimizing for code size, 2 instructions in common is enough if
   // we don't have to split a block.  At worst we will be introducing 1 new
   // branch instruction, which is likely to be smaller than the 2
   // instructions that would be deleted in the merge.
   MachineFunction *MF = MBB1->getParent();
-  if (EffectiveTailLen >= 2 &&
+  return EffectiveTailLen >= 2 &&
          MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
-      (I1 == MBB1->begin() || I2 == MBB2->begin()))
-    return true;
-
-  return false;
+         (I1 == MBB1->begin() || I2 == MBB2->begin());
 }
 
 /// ComputeSameTails - Look through all the blocks in MergePotentials that have
 /// hash CurHash (guaranteed to match the last element).  Build the vector
 /// SameTails of all those that have the (same) largest number of instructions
 /// in common of any pair of these blocks.  SameTails entries contain an
 /// iterator into MergePotentials (from which the MachineBasicBlock can be
 /// found) and a MachineBasicBlock::iterator into that MBB indicating the

lib/CodeGen/CallingConvLower.cpp

#endif
   }
 }
 
 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) {
   if (VT.isVector())
     return true; // Assume -msse-regparm might be in effect.
   if (!VT.isInteger())
     return false;
-  if (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall)
-    return true;
-  return false;
+  return CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall;
 }
 
 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
                                           MVT VT, CCAssignFn Fn) {
   unsigned SavedStackOffset = StackOffset;
   unsigned NumLocs = Locs.size();
 
   // Set the 'inreg' flag if it is used for this calling convention.

lib/CodeGen/CodeGenPrepare.cpp

static bool SinkCmpExpression(CmpInst *CI) {
 
   return MadeChange;
 }
 
 static bool OptimizeCmpExpression(CmpInst *CI) {
   if (SinkCmpExpression(CI))
     return true;
 
-  if (CombineUAddWithOverflow(CI))
-    return true;
-
-  return false;
+  return CombineUAddWithOverflow(CI);
 }
 
 /// isExtractBitsCandidateUse - Check if the candidates could
 /// be combined with shift instruction, which includes:
 /// 1. Truncate instruction
 /// 2. And instruction and the imm is a mask of the low bits:
 /// imm & (imm+1) == 0
 static bool isExtractBitsCandidateUse(Instruction *User) {
class TypePromotionHelper {
   /// ext opnd1 to ConsideredExtType.
   /// \p PromotedInsts maps the instructions to their type before promotion.
   static bool canGetThrough(const Instruction *Inst, Type *ConsideredExtType,
                             const InstrToOrigTy &PromotedInsts, bool IsSExt);
 
   /// \brief Utility function to determine if \p OpIdx should be promoted when
   /// promoting \p Inst.
   static bool shouldExtOperand(const Instruction *Inst, int OpIdx) {
-    if (isa<SelectInst>(Inst) && OpIdx == 0)
-      return false;
-    return true;
+    return !(isa<SelectInst>(Inst) && OpIdx == 0);
   }
 
   /// \brief Utility function to promote the operand of \p Ext when this
   /// operand is a promotable trunc or sext or zext.
   /// \p PromotedInsts maps the instructions to their type before promotion.
   /// \p CreatedInstsCost[out] contains the cost of all instructions
   /// created to promote the operand of Ext.
   /// Newly added extensions are inserted in \p Exts.
bool TypePromotionHelper::canGetThrough(const Instruction *Inst,
   if (It != PromotedInsts.end() && It->second.IsSExt == IsSExt)
     OpndType = It->second.Ty;
   else if ((IsSExt && isa<SExtInst>(Opnd)) || (!IsSExt && isa<ZExtInst>(Opnd)))
     OpndType = Opnd->getOperand(0)->getType();
   else
     return false;
 
   // #2 check that the truncate just drop extended bits.
-  if (Inst->getType()->getIntegerBitWidth() >= OpndType->getIntegerBitWidth())
-    return true;
-
-  return false;
+  return Inst->getType()->getIntegerBitWidth() >=
+         OpndType->getIntegerBitWidth();
 }
 
 TypePromotionHelper::Action TypePromotionHelper::getAction(
     Instruction *Ext, const SetOfInstrs &InsertedTruncs,
     const TargetLowering &TLI, const InstrToOrigTy &PromotedInsts) {
   assert((isa<SExtInst>(Ext) || isa<ZExtInst>(Ext)) &&
          "Unexpected instruction type");
   Instruction *ExtOpnd = dyn_cast<Instruction>(Ext->getOperand(0));

lib/CodeGen/LiveDebugVariables.cpp

 public:
   UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(D), LS(L) {}
 
   /// dominates - Return true if current scope dominates at least one machine
   /// instruction in a given machine basic block.
   bool dominates(MachineBasicBlock *MBB) {
     if (LBlocks.empty())
       LS.getMachineBasicBlocks(DL, LBlocks);
-    if (LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB))
-      return true;
-    return false;
+    return LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB);
   }
 };
 } // end anonymous namespace
 
 /// UserValue - A user value is a part of a debug info user variable.
 ///
 /// A DBG_VALUE instruction notes that (a sub-register of) a virtual register
 /// holds part of a user variable. The part is identified by a byte offset.

lib/CodeGen/LiveRangeEdit.cpp

else {
     assert(RM.OrigMI && "No defining instruction for remattable value");
   }
 
   // If only cheap remats were requested, bail out early.
   if (cheapAsAMove && !TII.isAsCheapAsAMove(RM.OrigMI))
     return false;
 
   // Verify that all used registers are available with the same values.
-  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
-    return false;
-
-  return true;
+  return allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx);
 }
 
 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
                                          unsigned DestReg,
                                          const Remat &RM,
                                          const TargetRegisterInfo &tri,
                                          bool Late) {

lib/CodeGen/MachineCombiner.cpp

bool MachineCombiner::preservesResourceLen(
   return ResLenAfterCombine <= ResLenBeforeCombine;
 }
 
 /// \returns true when new instruction sequence should be generated
 /// independent if it lengthens critical path or not
 bool MachineCombiner::doSubstitute(unsigned NewSize, unsigned OldSize) {
   if (OptSize && (NewSize < OldSize))
     return true;
-  if (!TSchedModel.hasInstrSchedModel())
-    return true;
-  return false;
+  return !TSchedModel.hasInstrSchedModel();
 }
 
 /// Substitute a slow code sequence with a faster one by
 /// evaluating instruction combining pattern.
 /// The prototype of such a pattern is MUl + ADD -> MADD. Performs instruction
 /// combining based on machine trace metrics. Only combine a sequence of
 /// instructions  when this neither lengthens the critical path nor increases
 /// resource pressure. When optimizing for codesize always combine when the new

lib/CodeGen/MachineLICM.cpp

if (!I.isSafeToMove(AA, DontMoveAcrossStore))
     return false;
 
   // If it is load then check if it is guaranteed to execute by making sure that
   // it dominates all exiting blocks. If it doesn't, then there is a path out of
   // the loop which does not execute this load, so we can't hoist it. Loads
   // from constant memory are not safe to speculate all the time, for example
   // indexed load from a jump table.
   // Stores and side effects are already checked by isSafeToMove.
-  if (I.mayLoad() && !isLoadFromGOTOrConstantPool(I) &&
-      !IsGuaranteedToExecute(I.getParent()))
-    return false;
-
-  return true;
+  return !I.mayLoad() || isLoadFromGOTOrConstantPool(I) ||
+         IsGuaranteedToExecute(I.getParent());
 }
 
 /// IsLoopInvariantInst - Returns true if the instruction is loop
 /// invariant. I.e., all virtual register operands are defined outside of the
 /// loop, physical registers aren't accessed explicitly, and there are no side
 /// effects that aren't captured by the operands or other flags.
 ///
 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {

lib/CodeGen/PseudoSourceValue.cpp

bool PseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
   if (this == getStack() ||
       this == getGOT() ||
       this == getConstantPool() ||
       this == getJumpTable())
     return false;
   llvm_unreachable("Unknown PseudoSourceValue!");
 }
 
 bool PseudoSourceValue::mayAlias(const MachineFrameInfo *MFI) const {
-  if (this == getGOT() ||
-      this == getConstantPool() ||
-      this == getJumpTable())
-    return false;
-  return true;
+  return this != getGOT() && this != getConstantPool() &&
+         this != getJumpTable();
 }
 
 bool FixedStackPseudoSourceValue::isConstant(const MachineFrameInfo *MFI) const{
   return MFI && MFI->isImmutableObjectIndex(FI);
 }
 
 bool FixedStackPseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
   if (!MFI)

lib/CodeGen/ScheduleDAGInstrs.cpp

void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
   VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
   if (DefI != VRegDefs.end() && DefI->SU != SU)
     DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
 }
 
 /// Return true if MI is an instruction we are unable to reason about
 /// (like a call or something with unmodeled side effects).
 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
-  if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
+  return MI->isCall() || MI->hasUnmodeledSideEffects() ||
          (MI->hasOrderedMemoryRef() &&
-       (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
-    return true;
-  return false;
+          (!MI->mayLoad() || !MI->isInvariantLoad(AA)));
 }
 
 // This MI might have either incomplete info, or known to be unsafe
 // to deal with (i.e. volatile object).
 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
                                         const MachineFrameInfo *MFI,
                                         const DataLayout &DL) {
   if (!MI || MI->memoperands_empty())

lib/CodeGen/StackProtector.cpp

if (SupportsSelectionDAGSP) {
       MDNode *Weights = MDBuilder(F->getContext())
                             .createBranchWeights(SuccessWeight, FailureWeight);
       B.CreateCondBr(Cmp, NewBB, FailBB, Weights);
     }
   }
 
   // Return if we didn't modify any basic blocks. i.e., there are no return
   // statements in the function.
-  if (!HasPrologue)
-    return false;
-
-  return true;
+  return HasPrologue;
 }
 
 /// CreateFailBB - Create a basic block to jump to when the stack protector
 /// check fails.
 BasicBlock *StackProtector::CreateFailBB() {
   LLVMContext &Context = F->getContext();
   BasicBlock *FailBB = BasicBlock::Create(Context, "CallStackCheckFailBlk", F);
   IRBuilder<> B(FailBB);

lib/CodeGen/TargetInstrInfo.cpp

bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
 
   const MCInstrDesc &MCID = MI->getDesc();
   if (!MCID.isCommutable())
     return false;
   // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
   // is not true, then the target must implement this.
   SrcOpIdx1 = MCID.getNumDefs();
   SrcOpIdx2 = SrcOpIdx1 + 1;
-  if (!MI->getOperand(SrcOpIdx1).isReg() ||
-      !MI->getOperand(SrcOpIdx2).isReg())
-    // No idea.
-    return false;
-  return true;
+  return MI->getOperand(SrcOpIdx1).isReg() && MI->getOperand(SrcOpIdx2).isReg();
 }
 
 
 bool
 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
   if (!MI->isTerminator()) return false;
 
   // Conditional branch is a special case.
bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
 
   // Don't attempt to schedule around any instruction that defines
   // a stack-oriented pointer, as it's unlikely to be profitable. This
   // saves compile time, because it doesn't require every single
   // stack slot reference to depend on the instruction that does the
   // modification.
   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
-  if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
-    return true;
-
-  return false;
+  return MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
 }
 
 // Provide a global flag for disabling the PreRA hazard recognizer that targets
 // may choose to honor.
 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
   return !DisableHazardRecognizer;
 }