[ARM] Fix typo in subtarget feature list for 7em triple

[john.brawn]

Summary

The list of subtarget features for the 7em triple contains 't2xtpk', which actually disables that subtarget feature. Correct that to '+t2xtpk' and test that the instructions enabled by that feature do actually work.

[t.p.northover]

Hi John,

This is fine. Easily obvious enough to go with post-commit review, in fact.

Cheers.

Tim.

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

case Triple::ARMSubArch_v7m:
     else
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
   case Triple::ARMSubArch_v7em:
     if (NoCPU)
       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
       //       FeatureT2XtPk, FeatureMClass
-      ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
+      ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
     else
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
   case Triple::ARMSubArch_v7s:
     if (NoCPU)
       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
       //      Swift

llvm/trunk/test/MC/ARM/thumb2-dsp-diag.s

-; RUN: not llvm-mc -triple=thumbv7m < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+@ RUN: not llvm-mc -triple=thumbv7m 2>&1 < %s | FileCheck --check-prefix=CHECK-ERRORS %s
+@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck --check-prefix=CHECK-7EM %s
 
 sxtab r0, r0, r0
 sxtah r0, r0, r0
 sxtab16 r0, r0, r0
 sxtb16 r0, r0
 sxtb16 r0, r0, ror #8
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-7EM: sxtab  r0, r0, r0              @ encoding: [0x40,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtah  r0, r0, r0              @ encoding: [0x00,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtab16  r0, r0, r0              @ encoding: [0x20,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtb16  r0, r0                  @ encoding: [0x2f,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtb16  r0, r0, ror #8          @ encoding: [0x2f,0xfa,0x90,0xf0]
 
 uxtab r0, r0, r0
 uxtah r0, r0, r0
 uxtab16 r0, r0, r0
 uxtb16 r0, r0
 uxtb16 r0, r0, ror #8
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: instruction requires: arm-mode
-; CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-7EM: uxtab  r0, r0, r0              @ encoding: [0x50,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtah  r0, r0, r0              @ encoding: [0x10,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtab16  r0, r0, r0              @ encoding: [0x30,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtb16  r0, r0                  @ encoding: [0x3f,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtb16  r0, r0, ror #8          @ encoding: [0x3f,0xfa,0x90,0xf0]