[Mips64] Add support for MCJIT for MIPS64r2 and MIPS64r6

[vradosavljevic]

Summary

Add support for resolving MIPS64r2 and MIPS64r6 relocations in MCJIT.

[dsanders]

This supersedes D5913 doesn't it? If so, could you mark that review abandoned.

I believe testcases similar to test/ExecutionEngine/RuntimeDyld/{AArch64,ARM,X86}/* will be required so that we can test the application of relocations without needing to execute JIT'ed code.

As with D5913, there are a couple big issues with this patch. The first is that checking for Triple::mips64/Triple::mips64el is insufficient since this (currently, see below) includes both N32 and N64 and these ABI's need to be treated differently. For example, the 3-in-1 reloc encoding is not used on N32. I don't mind if N32 support arrives in a later patch but this patch needs to identify N32 and N64 and error on N32 while handling N64 rather than quietly doing the wrong thing. The second issue is that using Triple::mips/Triple::mipsel vs Triple::mips64/Triple::mips64el to distinguish 32-bit and 64-bit ABI's is incorrect. It's valid to execute O32 binaries with a 64-bit triple, and N32/N64 binaries with a 32-bit triple. Admittedly, LLVM for Mips targets already has a number of issues in this area but I'd like to avoid adding more.

unittests/ExecutionEngine/MCJIT/MCJITTestBase.h

295 ↗

(On Diff #25477)

I think the answer is 'no' but: Does test/ExecutionEngine/MCJIT/lit.local.cfg need updating?

[lhames]

As dsanders noted, this needs some llvm-rtdyld checker tests along the lines of test/ExecutionEngine/RuntimeDyld/{AArch64,ARM,X86}/* .

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

124–139 ↗

(On Diff #25477)

Could you please note in the comments that these data structures are MIPS64 specific? At some point in the future we would like to split RuntimeDyldELF into multiple target-specific subclasses along the same lines as RuntimeDyldMachO. When that happens it will be very helpful to know that these data structures can be moved into the RuntimeDyldELF_MIPS64 subclass.

[vradosavljevic]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

124–139 ↗

(On Diff #25477)

Done.

unittests/ExecutionEngine/MCJIT/MCJITTestBase.h

295 ↗

(On Diff #25477)

We don't have to change test/ExecutionEngine/MCJIT/lit.local.cfg, because 'Mips' contains all Mips triples.
You can see that in autoconf/configure.ac.

mips-* | mips64-*)      host_arch="Mips" ;;
mipsel-* | mips64el-*)  host_arch="Mips" ;;

[vradosavljevic]

Comments addressed. Added llvm-rtdyld checker test, marked MCJIT and OrcMCJIT PIC tests as XFAIL only for mips32 architecture, and added an error report when using N32/O32 ABI's with Mips64 triple.

[dsanders]

Comments addressed. Added llvm-rtdyld checker test, marked MCJIT and OrcMCJIT PIC tests as XFAIL only for mips32 architecture, and added an error report when using N32/O32 ABI's with Mips64 triple.

There's still several triple checks that should be ABI checks. Using the triple for more than distinguishing the Mips target from the others is incorrect.

Also, the llvm-rtdyld test doesn't seem to cover many relocations. Could you expand on it?

lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp

777 ↗

(On Diff #25870)

Target triple -> ABI checks.

Only N64 should take this path.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

This particular overload of resolveMIPS64Relocation is only called from this function. So if we rename it to evaluateMIPS64Relocation(), stop it applying the reloc, and have it take/return the current calculated value we can use it as per this pseudo-code:

int64_t calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type, RE.Addend, RE.SectionID, RE.SymOffset, calculatedValue);
if (r_type2 == ELF::R_MIPS_NONE)
  applyMIPS64Relocation(Section.Address + RE.Offset, calculatedValue);

This is neater than passing values in side-channels such as member variables.

578–579 ↗

(On Diff #25870)

Endian bug. You can't use reinterpret_cast since the host and target may have different endians (particularly for test-cases). Use the endian-aware writeBytesUnaligned() or similar instead. Likewise for the other instances below.

1289 ↗

(On Diff #25870)

Triple checks -> ABI checks.

1603–1606 ↗

(On Diff #25870)

Not 100% sure about this one, but I think it's only correct for N64 due to pointer size differences. If this is the case, then we need an ABI check

1667 ↗

(On Diff #25870)

Triple check -> ABI check.

1670–1671 ↗

(On Diff #25870)

mips64/mips64el and O32 is not an error case, it's valid. Admittedly it doesn't work in LLVM at this point (this is a bug) so maybe including O32 in this error is ok for now. Could you add a comment explaining that.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

124–132 ↗

(On Diff #25870)

These three shouldn't be members variables. See below.

[vradosavljevic]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

My understanding of Mips64 ABI is there can be more relocation entries for the same instruction, so i'm using applyRelocation, useCalculatedValue and calculatedValue as members variables to keep them for the following relocation entry if that's the case.

Mips64 ABI allows us e.g.:
000000000000000c R_MIPS_GPREL16 main
000000000000000c R_MIPS_SUB *ABS*
000000000000000c R_MIPS_HI16 *ABS*

000000000000000c R_MIPS_GPREL16 main
000000000000000c R_MIPS_SUB *ABS*
000000000000000c R_MIPS_HI16 *ABS*

So if this is the case (theoretically), we should use result of r_type3 from the first relocation entry, for r_type in the second relocation entry (in our case we should use calculatedValue).

From Mips64 ABI:

Up to three operations may be specified per record, by the fields r_type , r_type2 , and r_type3 . They are applied in that order, and a zero field implies no further operations from this record. (The following record may continue the sequence if it references the same offset.)

1670–1671 ↗

(On Diff #25870)

Should i change triple checks for mips and mipsel to O32 ABI checks and report an error only for N32 ABI?

[dsanders]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

There are multiple ABI's that can be used on Mips64. When you refer to the 'Mips64 ABI', I believe you are referring to the N64 ABI. Is this correct? There is also an N32 ABI which behaves differently. For example, the 3-in-1 reloc encoding only applies to the N64 ABI and not the N32 ABI, and pointers/symbols are 4-bytes for N32 and 8-bytes for N64.
For the sake of completeness, there is also the O64 ABI and the EABI64 ABI but we haven't implemented those two.

My main issue with this chunk of code was its use of sideband mechanisms to implement argument/return value passing instead of using a normal function call. It passes arguments in by writing to a member, returns them by writing to a member, and reads the result by reading a member. Using function arguments and return values is much clearer and does not increase the size of the object unnecessarily.

Here's the example code with all three relocs accounted for and tidied up:

int64_t calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type, RE.Addend, RE.SectionID, RE.SymOffset, calculatedValue);
if (r_type2 != ELF::R_MIPS_NONE)
  calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type2, RE.Addend, RE.SectionID, RE.SymOffset, calculatedValue);
if (r_type3 != ELF::R_MIPS_NONE)
  calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type3, RE.Addend, RE.SectionID, RE.SymOffset, calculatedValue);
applyMIPS64Relocation(Section.Address + RE.Offset, calculatedValue);

1670–1671 ↗

(On Diff #25870)

Yes. It's ok to use triples to distinguish Mips from other targets, but not to determine the ABI. The only one we need to emit an error for is N32.

The combination of O32 and a mips64/mips64el triple won't work for now because the code generator will assert up front rather than allow the various bugs to confuse the user. However, we should still accept this combination here because we do the right thing in these layers.
The same applies to N32/N64 and mips/mipsel triples.

[vradosavljevic]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

Yes, i'm referring to Mips N64 ABI. This may not be the end of calculating, so we need to check if the next relocation entry is for the same instruction. If it is for the same instruction, we need to send calculatedValue to next relocation entry.

[dsanders]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

Ah, I see the complicating issue. I'm going to have to look up the details of relocation composition to comment on that. The main thing I'm wondering is why Mips needs to do this and other targets don't. I know that some relocation mechanisms would write the calculated value to the section data after one relocation and read it back for the next relocation.

[dsanders]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

I've now looked it up. The 64-bit ELF Object
File Specification (available at https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf), gives the following definition for the 'A' operands:

Represents an addend obtained as the value of the field being relocated
prior to relocation (.rel), from a .rela addend field, or as the preceding
result for a composed relocation (either).

Since N64 uses RELA relocations, I believe my example above should be passing in calculatedValue instead of RE.Addend for all except the first relocation for that address, like so:

int64_t calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type, RE.Addend, RE.SectionID, RE.SymOffset);
if (r_type2 != ELF::R_MIPS_NONE)
  calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type2, calculatedValue, RE.SectionID, RE.SymOffset);
if (r_type3 != ELF::R_MIPS_NONE)
  calculatedValue = evaluateMIPS64Relocation(Section, RE.Offset, Value, r_type3, calculatedValue, RE.SectionID, RE.SymOffset);
applyMIPS64Relocation(Section.Address + RE.Offset, calculatedValue);

It's possible that the two calculatedValue arguments should be 'calculatedValue + RE.Addend' but the spec was a bit unclear on this so I'm not 100% sure. Your current patch implements the former so I've gone with that.

Yes, i'm referring to Mips N64 ABI. This may not be the end of calculating, so we need
to check if the next relocation entry is for the same instruction. If it is for the same
instruction, we need to send calculatedValue to next relocation entry.

Why not handle composition of multiple relocs in resolveRelocationList?

The main thing I'm wondering is why Mips needs to do this and other targets don't.

To partially answer my own question, relocation composition isn't particularly unique to to Mips but it seems that we may use it more often than other targets.

[petarj]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

What Vladimir is trying to say is that - theoretically speaking - getting calculatedValue for r_type can require calculatedValue that we calculated from r_type3 in the previous RelocationEntry.

[dsanders]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

526–529 ↗

(On Diff #25870)

Yes, I understood that. What I'm trying to say is that you don't need sideband data to achieve that. resolveRelocationList can iterate over all the composed relocations, evaluating it as it goes, and then it can apply the calculated value.

[vradosavljevic]

New patch uploaded. Please take a look.

[dsanders]

Thanks, that's much cleaner. Most of my comments on the latest patch are nits or notes on things that will need to be followed up on. There is one question among them though, as well as one more comment below.

We seem to have lost the ability to compose distinct relocs in this patch. This should be ok in the immediate term (because we do handle our common composition case of the 3-in-1 relocs) but it's something we'll need to follow up on.

Assuming it's safe to only check r_type for R_MIPS_CALL16, R_MIPS_GOT_PAGE, or R_MIPS_GOT_DISP : LGTM with the nits fixed.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

191 ↗

(On Diff #26605)

Nit: Seems unnecessary. It's about to be destroyed anyway and we don't seem to be managing memory.

512–513 ↗

(On Diff #26605)

For follow-up: It would be preferable to use a MipsABIInfo object. It's essentially an enum representing the ABI but you can ask it questions (e.g. Does the current ABI use REL or RELA relocations? etc.) using the member functions.

I don't think we should do this now though. I think it should wait until Architectures have their own subclasses. If we tried to do it now it would probably require Mips support to always be compiled into LLVM and that's undesirable.

516–521 ↗

(On Diff #26605)

For follow-up: This is a good example of knowledge that would be suitable for MipsABIInfo. There are multiple places that need to know how to map ELF e_flags to the ABI.

536 ↗

(On Diff #26605)

Nit: Variables should begin with a capital.

r_type/r_type2/r_type3 are arguably ok since they are trying to match member names of an ELF64 structure so there's no need to change those.

559 ↗

(On Diff #26605)

Nit: Capitalization

561 ↗

(On Diff #26605)

Nit: Doesn't match the function name (the 'resolve' and the 'Mips')

579–581 ↗

(On Diff #26605)

Optional nit: Move the return into the cases. E.g:

case ELF::R_MIPS_64:
  return Value + Addend;

1035 ↗

(On Diff #26605)

Nit:

else
  llvm_unreachable("Mips ABI not handled");

1277–1280 ↗

(On Diff #26605)

Is it definitely only r_type that matters? Is it possible to have these relocs in r_type2 or r_type3?

1605 ↗

(On Diff #26605)

Nit:

else
  llvm_unreachable(...);

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

61 ↗

(On Diff #26605)

Nit: calculatedValue should begin with a capital

[vradosavljevic]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

191 ↗

(On Diff #26605)

Done.

536 ↗

(On Diff #26605)

Done.

561 ↗

(On Diff #26605)

Done.

579–581 ↗

(On Diff #26605)

Done.

1035 ↗

(On Diff #26605)

Done.

1277–1280 ↗

(On Diff #26605)

Yes only r_type matters, and in these cases r_type2 and r_type3 are R_MIPS_NONE.

1605 ↗

(On Diff #26605)

Done.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

61 ↗

(On Diff #26605)

Done.

[vradosavljevic]

Comments addressed.

[dsanders]

LGTM

[petarj]

In D9667#179660, @dsanders wrote:

We seem to have lost the ability to compose distinct relocs in this patch. This should be ok in the immediate term (because we do handle our common composition case of the 3-in-1 relocs) but it's something we'll need to follow up on.

Yes, we should not forget that. Vladimir, can you create a ticket for this one?
lgtm.

llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp

RuntimeDyldImpl::loadObjectImpl(const object::ObjectFile &Obj) {
 
   // Grab the first Section ID. We'll use this later to construct the underlying
   // range for the returned LoadedObjectInfo.
   unsigned SectionsAddedBeginIdx = Sections.size();
 
   // Save information about our target
   Arch = (Triple::ArchType)Obj.getArch();
   IsTargetLittleEndian = Obj.isLittleEndian();
+  setMipsABI(Obj);
 
   // Compute the memory size required to load all sections to be loaded
   // and pass this information to the memory manager
   if (MemMgr.needsToReserveAllocationSpace()) {
     uint64_t CodeSize = 0, DataSizeRO = 0, DataSizeRW = 0;
     computeTotalAllocSize(Obj, CodeSize, DataSizeRO, DataSizeRW);
     MemMgr.reserveAllocationSpace(CodeSize, DataSizeRO, DataSizeRW);
   }
if (Arch == Triple::aarch64 || Arch == Triple::aarch64_be) {
     writeBytesUnaligned(0xd61f0200, Addr+16, 4); // br ip0
 
     return Addr;
   } else if (Arch == Triple::arm || Arch == Triple::armeb) {
     // TODO: There is only ARM far stub now. We should add the Thumb stub,
     // and stubs for branches Thumb - ARM and ARM - Thumb.
     writeBytesUnaligned(0xe51ff004, Addr, 4); // ldr pc,<label>
     return Addr + 4;
-  } else if (Arch == Triple::mipsel || Arch == Triple::mips) {
+  } else if (IsMipsO32ABI) {
     // 0:   3c190000        lui     t9,%hi(addr).
     // 4:   27390000        addiu   t9,t9,%lo(addr).
     // 8:   03200008        jr      t9.
     // c:   00000000        nop.
     const unsigned LuiT9Instr = 0x3c190000, AdduiT9Instr = 0x27390000;
     const unsigned JrT9Instr = 0x03200008, NopInstr = 0x0;
 
     writeBytesUnaligned(LuiT9Instr, Addr, 4);

llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

 using namespace llvm;
 
 namespace llvm {
 
 class RuntimeDyldELF : public RuntimeDyldImpl {
 
   void resolveRelocation(const SectionEntry &Section, uint64_t Offset,
                          uint64_t Value, uint32_t Type, int64_t Addend,
-                         uint64_t SymOffset = 0);
+                         uint64_t SymOffset = 0, SID SectionID = 0);
 
   void resolveX86_64Relocation(const SectionEntry &Section, uint64_t Offset,
                                uint64_t Value, uint32_t Type, int64_t Addend,
                                uint64_t SymOffset);
 
   void resolveX86Relocation(const SectionEntry &Section, uint64_t Offset,
                             uint32_t Value, uint32_t Type, int32_t Addend);
 
   void resolveAArch64Relocation(const SectionEntry &Section, uint64_t Offset,
                                 uint64_t Value, uint32_t Type, int64_t Addend);
 
   void resolveARMRelocation(const SectionEntry &Section, uint64_t Offset,
                             uint32_t Value, uint32_t Type, int32_t Addend);
 
   void resolveMIPSRelocation(const SectionEntry &Section, uint64_t Offset,
                              uint32_t Value, uint32_t Type, int32_t Addend);
 
   void resolvePPC64Relocation(const SectionEntry &Section, uint64_t Offset,
                               uint64_t Value, uint32_t Type, int64_t Addend);
 
   void resolveSystemZRelocation(const SectionEntry &Section, uint64_t Offset,
                                 uint64_t Value, uint32_t Type, int64_t Addend);
 
+  void resolveMIPS64Relocation(const SectionEntry &Section, uint64_t Offset,
+                               uint64_t Value, uint32_t Type, int64_t Addend,
+                               uint64_t SymOffset, SID SectionID);
+
+  int64_t evaluateMIPS64Relocation(const SectionEntry &Section,
+                                   uint64_t Offset, uint64_t Value,
+                                   uint32_t Type,  int64_t Addend,
+                                   uint64_t SymOffset, SID SectionID);
+
+  void applyMIPS64Relocation(uint8_t *TargetPtr, int64_t CalculatedValue,
+                             uint32_t Type);
+
   unsigned getMaxStubSize() override {
     if (Arch == Triple::aarch64 || Arch == Triple::aarch64_be)
       return 20; // movz; movk; movk; movk; br
     if (Arch == Triple::arm || Arch == Triple::thumb)
       return 8; // 32-bit instruction and 32-bit address
-    else if (Arch == Triple::mipsel || Arch == Triple::mips)
+    else if (IsMipsO32ABI)
       return 16;
     else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le)
       return 44;
     else if (Arch == Triple::x86_64)
       return 6; // 2-byte jmp instruction + 32-bit relative address
     else if (Arch == Triple::systemz)
       return 16;
     else
       return 0;
   }
 
   unsigned getStubAlignment() override {
     if (Arch == Triple::systemz)
       return 8;
     else
       return 1;
   }
 
+  void setMipsABI(const ObjectFile &Obj) override;
+
   void findPPC64TOCSection(const ObjectFile &Obj,
                            ObjSectionToIDMap &LocalSections,
                            RelocationValueRef &Rel);
   void findOPDEntrySection(const ObjectFile &Obj,
                            ObjSectionToIDMap &LocalSections,
                            RelocationValueRef &Rel);
 
   size_t getGOTEntrySize();
class RuntimeDyldELF : public RuntimeDyldImpl {
   // The tentative ID for the GOT section
   unsigned GOTSectionID;
 
   // Records the current number of allocated slots in the GOT
   // (This would be equivalent to GOTEntries.size() were it not for relocations
   // that consume more than one slot)
   unsigned CurrentGOTIndex;
 
+  // A map from section to a GOT section that has entries for section's GOT
+  // relocations. (Mips64 specific)
+  DenseMap<SID, SID> SectionToGOTMap;
+
+  // A map to avoid duplicate got entries (Mips64 specific)
+  StringMap<uint64_t> GOTSymbolOffsets;
+
   // When a module is loaded we save the SectionID of the EH frame section
   // in a table until we receive a request to register all unregistered
   // EH frame sections with the memory manager.
   SmallVector<SID, 2> UnregisteredEHFrameSections;
   SmallVector<SID, 2> RegisteredEHFrameSections;
 
 public:
   RuntimeDyldELF(RuntimeDyld::MemoryManager &MemMgr,

llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

*TargetPtr =
       ((*TargetPtr) & 0xffff0000) | (((Value + 0x8000) >> 16) & 0xffff);
     break;
   case ELF::R_MIPS_LO16:
     *TargetPtr = ((*TargetPtr) & 0xffff0000) | (Value & 0xffff);
     break;
   }
 }
 
+void RuntimeDyldELF::setMipsABI(const ObjectFile &Obj) {
+  if (!StringRef(Triple::getArchTypePrefix(Arch)).equals("mips")) {
+    IsMipsO32ABI = false;
+    IsMipsN64ABI = false;
+    return;
+  }
+  unsigned AbiVariant;
+  Obj.getPlatformFlags(AbiVariant);
+  IsMipsO32ABI = AbiVariant & ELF::EF_MIPS_ABI_O32;
+  IsMipsN64ABI = Obj.getFileFormatName().equals("ELF64-mips");
+  if (AbiVariant & ELF::EF_MIPS_ABI2)
+    llvm_unreachable("Mips N32 ABI is not supported yet");
+}
+
+void RuntimeDyldELF::resolveMIPS64Relocation(const SectionEntry &Section,
+                                             uint64_t Offset, uint64_t Value,
+                                             uint32_t Type, int64_t Addend,
+                                             uint64_t SymOffset,
+                                             SID SectionID) {
+  uint32_t r_type = Type & 0xff;
+  uint32_t r_type2 = (Type >> 8) & 0xff;
+  uint32_t r_type3 = (Type >> 16) & 0xff;
+
+  // RelType is used to keep information for which relocation type we are
+  // applying relocation.
+  uint32_t RelType = r_type;
+  int64_t CalculatedValue = evaluateMIPS64Relocation(Section, Offset, Value,
+                                                     RelType, Addend,
+                                                     SymOffset, SectionID);
+  if (r_type2 != ELF::R_MIPS_NONE) {
+    RelType = r_type2;
+    CalculatedValue = evaluateMIPS64Relocation(Section, Offset, 0, RelType,
+                                               CalculatedValue, SymOffset,
+                                               SectionID);
+  }
+  if (r_type3 != ELF::R_MIPS_NONE) {
+    RelType = r_type3;
+    CalculatedValue = evaluateMIPS64Relocation(Section, Offset, 0, RelType,
+                                               CalculatedValue, SymOffset,
+                                               SectionID);
+  }
+  applyMIPS64Relocation(Section.Address + Offset, CalculatedValue, RelType);
+}
+
+int64_t
+RuntimeDyldELF::evaluateMIPS64Relocation(const SectionEntry &Section,
+                                         uint64_t Offset, uint64_t Value,
+                                         uint32_t Type, int64_t Addend,
+                                         uint64_t SymOffset, SID SectionID) {
+
+  DEBUG(dbgs() << "evaluateMIPS64Relocation, LocalAddress: 0x"
+               << format("%llx", Section.Address + Offset)
+               << " FinalAddress: 0x"
+               << format("%llx", Section.LoadAddress + Offset)
+               << " Value: 0x" << format("%llx", Value) << " Type: 0x"
+               << format("%x", Type) << " Addend: 0x" << format("%llx", Addend)
+               << " SymOffset: " << format("%x", SymOffset)
+               << "\n");
+
+  switch (Type) {
+  default:
+    llvm_unreachable("Not implemented relocation type!");
+    break;
+  case ELF::R_MIPS_JALR:
+  case ELF::R_MIPS_NONE:
+    break;
+  case ELF::R_MIPS_32:
+  case ELF::R_MIPS_64:
+    return Value + Addend;
+  case ELF::R_MIPS_26:
+    return ((Value + Addend) >> 2) & 0x3ffffff;
+  case ELF::R_MIPS_GPREL16: {
+    uint64_t GOTAddr = getSectionLoadAddress(SectionToGOTMap[SectionID]);
+    return Value + Addend - (GOTAddr + 0x7ff0);
+  }
+  case ELF::R_MIPS_SUB:
+    return Value - Addend;
+  case ELF::R_MIPS_HI16:
+    // Get the higher 16-bits. Also add 1 if bit 15 is 1.
+    return ((Value + Addend + 0x8000) >> 16) & 0xffff;
+  case ELF::R_MIPS_LO16:
+    return (Value + Addend) & 0xffff;
+  case ELF::R_MIPS_CALL16:
+  case ELF::R_MIPS_GOT_DISP:
+  case ELF::R_MIPS_GOT_PAGE: {
+    uint8_t *LocalGOTAddr =
+        getSectionAddress(SectionToGOTMap[SectionID]) + SymOffset;
+    uint64_t GOTEntry = readBytesUnaligned(LocalGOTAddr, 8);
+
+    Value += Addend;
+    if (Type == ELF::R_MIPS_GOT_PAGE)
+      Value = (Value + 0x8000) & ~0xffff;
+
+    if (GOTEntry)
+      assert(GOTEntry == Value &&
+                   "GOT entry has two different addresses.");
+    else
+      writeBytesUnaligned(Value, LocalGOTAddr, 8);
+
+    return (SymOffset - 0x7ff0) & 0xffff;
+  }
+  case ELF::R_MIPS_GOT_OFST: {
+    int64_t page = (Value + Addend + 0x8000) & ~0xffff;
+    return (Value + Addend - page) & 0xffff;
+  }
+  case ELF::R_MIPS_GPREL32: {
+    uint64_t GOTAddr = getSectionLoadAddress(SectionToGOTMap[SectionID]);
+    return Value + Addend - (GOTAddr + 0x7ff0);
+  }
+  case ELF::R_MIPS_PC16: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return ((Value + Addend - FinalAddress - 4) >> 2) & 0xffff;
+  }
+  case ELF::R_MIPS_PC18_S3: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return ((Value + Addend - ((FinalAddress | 7) ^ 7)) >> 3) & 0x3ffff;
+  }
+  case ELF::R_MIPS_PC19_S2: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return ((Value + Addend - FinalAddress) >> 2) & 0x7ffff;
+  }
+  case ELF::R_MIPS_PC21_S2: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return ((Value + Addend - FinalAddress) >> 2) & 0x1fffff;
+  }
+  case ELF::R_MIPS_PC26_S2: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return ((Value + Addend - FinalAddress) >> 2) & 0x3ffffff;
+  }
+  case ELF::R_MIPS_PCHI16: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return ((Value + Addend - FinalAddress + 0x8000) >> 16) & 0xffff;
+  }
+  case ELF::R_MIPS_PCLO16: {
+    uint64_t FinalAddress = (Section.LoadAddress + Offset);
+    return (Value + Addend - FinalAddress) & 0xffff;
+  }
+  }
+  return 0;
+}
+
+void RuntimeDyldELF::applyMIPS64Relocation(uint8_t *TargetPtr,
+                                           int64_t CalculatedValue,
+                                           uint32_t Type) {
+  uint32_t Insn = readBytesUnaligned(TargetPtr, 4);
+
+  switch (Type) {
+    default:
+      break;
+    case ELF::R_MIPS_32:
+    case ELF::R_MIPS_GPREL32:
+      writeBytesUnaligned(CalculatedValue & 0xffffffff, TargetPtr, 4);
+      break;
+    case ELF::R_MIPS_64:
+    case ELF::R_MIPS_SUB:
+      writeBytesUnaligned(CalculatedValue, TargetPtr, 8);
+      break;
+    case ELF::R_MIPS_26:
+    case ELF::R_MIPS_PC26_S2:
+      Insn = (Insn & 0xfc000000) | CalculatedValue;
+      writeBytesUnaligned(Insn, TargetPtr, 4);
+      break;
+    case ELF::R_MIPS_GPREL16:
+      Insn = (Insn & 0xffff0000) | (CalculatedValue & 0xffff);
+      writeBytesUnaligned(Insn, TargetPtr, 4);
+      break;
+    case ELF::R_MIPS_HI16:
+    case ELF::R_MIPS_LO16:
+    case ELF::R_MIPS_PCHI16:
+    case ELF::R_MIPS_PCLO16:
+    case ELF::R_MIPS_PC16:
+    case ELF::R_MIPS_CALL16:
+    case ELF::R_MIPS_GOT_DISP:
+    case ELF::R_MIPS_GOT_PAGE:
+    case ELF::R_MIPS_GOT_OFST:
+      Insn = (Insn & 0xffff0000) | CalculatedValue;
+      writeBytesUnaligned(Insn, TargetPtr, 4);
+      break;
+    case ELF::R_MIPS_PC18_S3:
+      Insn = (Insn & 0xfffc0000) | CalculatedValue;
+      writeBytesUnaligned(Insn, TargetPtr, 4);
+      break;
+    case ELF::R_MIPS_PC19_S2:
+      Insn = (Insn & 0xfff80000) | CalculatedValue;
+      writeBytesUnaligned(Insn, TargetPtr, 4);
+      break;
+    case ELF::R_MIPS_PC21_S2:
+      Insn = (Insn & 0xffe00000) | CalculatedValue;
+      writeBytesUnaligned(Insn, TargetPtr, 4);
+      break;
+    }
+}
+
 // Return the .TOC. section and offset.
 void RuntimeDyldELF::findPPC64TOCSection(const ObjectFile &Obj,
                                          ObjSectionToIDMap &LocalSections,
                                          RelocationValueRef &Rel) {
   // Set a default SectionID in case we do not find a TOC section below.
   // This may happen for references to TOC base base (sym@toc, .odp
   // relocation) without a .toc directive.  In this case just use the
   // first section (which is usually the .odp) since the code won't

 // current object Value will be the LoadAddress of the section in which
 // the symbol resides (RE.Addend provides additional information about the
 // symbol location).  For external symbols, Value will be the address of the
 // symbol in the target address space.
 void RuntimeDyldELF::resolveRelocation(const RelocationEntry &RE,
                                        uint64_t Value) {
   const SectionEntry &Section = Sections[RE.SectionID];
   return resolveRelocation(Section, RE.Offset, Value, RE.RelType, RE.Addend,
-                           RE.SymOffset);
+                           RE.SymOffset, RE.SectionID);
 }
 
 void RuntimeDyldELF::resolveRelocation(const SectionEntry &Section,
                                        uint64_t Offset, uint64_t Value,
                                        uint32_t Type, int64_t Addend,
-                                       uint64_t SymOffset) {
+                                       uint64_t SymOffset, SID SectionID) {
   switch (Arch) {
   case Triple::x86_64:
     resolveX86_64Relocation(Section, Offset, Value, Type, Addend, SymOffset);
     break;
   case Triple::x86:
     resolveX86Relocation(Section, Offset, (uint32_t)(Value & 0xffffffffL), Type,
                          (uint32_t)(Addend & 0xffffffffL));
     break;
   case Triple::aarch64:
   case Triple::aarch64_be:
     resolveAArch64Relocation(Section, Offset, Value, Type, Addend);
     break;
   case Triple::arm: // Fall through.
   case Triple::armeb:
   case Triple::thumb:
   case Triple::thumbeb:
     resolveARMRelocation(Section, Offset, (uint32_t)(Value & 0xffffffffL), Type,
                          (uint32_t)(Addend & 0xffffffffL));
     break;
   case Triple::mips: // Fall through.
   case Triple::mipsel:
+  case Triple::mips64:
+  case Triple::mips64el:
+    if (IsMipsO32ABI)
       resolveMIPSRelocation(Section, Offset, (uint32_t)(Value & 0xffffffffL),
                             Type, (uint32_t)(Addend & 0xffffffffL));
+    else if (IsMipsN64ABI)
+      resolveMIPS64Relocation(Section, Offset, Value, Type, Addend, SymOffset,
+                              SectionID);
+    else
+      llvm_unreachable("Mips ABI not handled");
     break;
   case Triple::ppc64: // Fall through.
   case Triple::ppc64le:
     resolvePPC64Relocation(Section, Offset, Value, Type, Addend);
     break;
   case Triple::systemz:
     resolveSystemZRelocation(Section, Offset, Value, Type, Addend);
     break;
if (RelType == ELF::R_ARM_PC24 || RelType == ELF::R_ARM_CALL ||
           RelType == ELF::R_ARM_ABS32) {
         Value.Addend += *Placeholder;
       } else if (RelType == ELF::R_ARM_MOVW_ABS_NC || RelType == ELF::R_ARM_MOVT_ABS) {
         // See ELF for ARM documentation
         Value.Addend += (int16_t)((*Placeholder & 0xFFF) | (((*Placeholder >> 16) & 0xF) << 12));
       }
       processSimpleRelocation(SectionID, Offset, RelType, Value);
     }
-  } else if ((Arch == Triple::mipsel || Arch == Triple::mips)) {
+  } else if (IsMipsO32ABI) {
     uint32_t *Placeholder = reinterpret_cast<uint32_t*>(computePlaceholderAddress(SectionID, Offset));
     if (RelType == ELF::R_MIPS_26) {
       // This is an Mips branch relocation, need to use a stub function.
       DEBUG(dbgs() << "\t\tThis is a Mips branch relocation.");
       SectionEntry &Section = Sections[SectionID];
 
       // Extract the addend from the instruction.
       // We shift up by two since the Value will be down shifted again
if (RelType == ELF::R_MIPS_26) {
       if (RelType == ELF::R_MIPS_HI16)
         Value.Addend += ((*Placeholder) & 0x0000ffff) << 16;
       else if (RelType == ELF::R_MIPS_LO16)
         Value.Addend += ((*Placeholder) & 0x0000ffff);
       else if (RelType == ELF::R_MIPS_32)
         Value.Addend += *Placeholder;
       processSimpleRelocation(SectionID, Offset, RelType, Value);
     }
+  } else if (IsMipsN64ABI) {
+    uint32_t r_type = RelType & 0xff;
+    RelocationEntry RE(SectionID, Offset, RelType, Value.Addend);
+    if (r_type == ELF::R_MIPS_CALL16 || r_type == ELF::R_MIPS_GOT_PAGE
+        || r_type == ELF::R_MIPS_GOT_DISP) {
+      StringMap<uint64_t>::iterator i = GOTSymbolOffsets.find(TargetName);
+      if (i != GOTSymbolOffsets.end())
+        RE.SymOffset = i->second;
+      else {
+        RE.SymOffset = allocateGOTEntries(SectionID, 1);
+        GOTSymbolOffsets[TargetName] = RE.SymOffset;
+      }
+    }
+    if (Value.SymbolName)
+      addRelocationForSymbol(RE, Value.SymbolName);
+    else
+      addRelocationForSection(RE, Value.SectionID);
   } else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le) {
     if (RelType == ELF::R_PPC64_REL24) {
       // Determine ABI variant in use for this object.
       unsigned AbiVariant;
       Obj.getPlatformFlags(AbiVariant);
       AbiVariant &= ELF::EF_PPC64_ABI;
       // A PPC branch relocation will need a stub function if the target is
       // an external symbol (Symbol::ST_Unknown) or if the target address
size_t RuntimeDyldELF::getGOTEntrySize() {
   case Triple::ppc64:
   case Triple::ppc64le:
   case Triple::systemz:
     Result = sizeof(uint64_t);
     break;
   case Triple::x86:
   case Triple::arm:
   case Triple::thumb:
+    Result = sizeof(uint32_t);
+    break;
   case Triple::mips:
   case Triple::mipsel:
+  case Triple::mips64:
+  case Triple::mips64el:
+    if (IsMipsO32ABI)
       Result = sizeof(uint32_t);
+    else if (IsMipsN64ABI)
+      Result = sizeof(uint64_t);
+    else
+      llvm_unreachable("Mips ABI not handled");
     break;
   default:
     llvm_unreachable("Unsupported CPU type!");
   }
   return Result;
 }
 
 uint64_t RuntimeDyldELF::allocateGOTEntries(unsigned SectionID, unsigned no)
if (GOTSectionID != 0) {
     Sections[GOTSectionID] = SectionEntry(".got", Addr, TotalSize, 0);
 
     if (Checker)
       Checker->registerSection(Obj.getFileName(), GOTSectionID);
 
     // For now, initialize all GOT entries to zero.  We'll fill them in as
     // needed when GOT-based relocations are applied.
     memset(Addr, 0, TotalSize);
+    if (IsMipsN64ABI) {
+      // To correctly resolve Mips GOT relocations, we need a mapping from
+      // object's sections to GOTs.
+      for (section_iterator SI = Obj.section_begin(), SE = Obj.section_end();
+           SI != SE; ++SI) {
+        if (SI->relocation_begin() != SI->relocation_end()) {
+          section_iterator RelocatedSection = SI->getRelocatedSection();
+          ObjSectionToIDMap::iterator i = SectionMap.find(*RelocatedSection);
+          assert (i != SectionMap.end());
+          SectionToGOTMap[i->second] = GOTSectionID;
+        }
+      }
+      GOTSymbolOffsets.clear();
+    }
   }
 
   // Look for and record the EH frame section.
   ObjSectionToIDMap::iterator i, e;
   for (i = SectionMap.begin(), e = SectionMap.end(); i != e; ++i) {
     const SectionRef &Section = i->first;
     StringRef Name;
     Section.getName(Name);

llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h

#define RTDYLD_INVALID_SECTION_ID ((RuntimeDyldImpl::SID)(-1))
   // modules.  This map is indexed by symbol name.
   StringMap<RelocationList> ExternalSymbolRelocations;
 
 
   typedef std::map<RelocationValueRef, uintptr_t> StubMap;
 
   Triple::ArchType Arch;
   bool IsTargetLittleEndian;
+  bool IsMipsO32ABI;
+  bool IsMipsN64ABI;
 
   // True if all sections should be passed to the memory manager, false if only
   // sections containing relocations should be. Defaults to 'false'.
   bool ProcessAllSections;
 
   // This mutex prevents simultaneously loading objects from two different
   // threads.  This keeps us from having to protect individual data structures
   // and guarantees that section allocation requests to the memory manager
void writeInt64BE(uint8_t *Addr, uint64_t Value) {
     *(Addr + 2) = (Value >> 40) & 0xFF;
     *(Addr + 3) = (Value >> 32) & 0xFF;
     *(Addr + 4) = (Value >> 24) & 0xFF;
     *(Addr + 5) = (Value >> 16) & 0xFF;
     *(Addr + 6) = (Value >> 8) & 0xFF;
     *(Addr + 7) = Value & 0xFF;
   }
 
+  virtual void setMipsABI(const ObjectFile &Obj) {
+    IsMipsO32ABI = false;
+    IsMipsN64ABI = false;
+  }
+
   /// Endian-aware read Read the least significant Size bytes from Src.
   uint64_t readBytesUnaligned(uint8_t *Src, unsigned Size) const;
 
   /// Endian-aware write. Write the least significant Size bytes from Value to
   /// Dst.
   void writeBytesUnaligned(uint64_t Value, uint8_t *Dst, unsigned Size) const;
 
   /// \brief Given the common symbols discovered in the object file, emit a

llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp

 extern "C" void LLVMInitializeMipsTargetInfo() {
   RegisterTarget<Triple::mips,
         /*HasJIT=*/true> X(TheMipsTarget, "mips", "Mips");
 
   RegisterTarget<Triple::mipsel,
         /*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel");
 
   RegisterTarget<Triple::mips64,
-        /*HasJIT=*/false> A(TheMips64Target, "mips64", "Mips64 [experimental]");
+        /*HasJIT=*/true> A(TheMips64Target, "mips64", "Mips64 [experimental]");
 
   RegisterTarget<Triple::mips64el,
-        /*HasJIT=*/false> B(TheMips64elTarget,
+        /*HasJIT=*/true> B(TheMips64elTarget,
                             "mips64el", "Mips64el [experimental]");
 }

llvm/trunk/test/ExecutionEngine/MCJIT/cross-module-sm-pic-a.ll

 ; RUN: %lli -extra-module=%p/Inputs/cross-module-b.ll -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386
+; XFAIL: mips-, mipsel-, i686, i386
 
 declare i32 @FB()
 
 define i32 @FA() {
   ret i32 0
 }
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/MCJIT/eh-lg-pic.ll

 ; RUN: %lli -relocation-model=pic -code-model=large %s
-; XFAIL: cygwin, win32, mingw, mips, i686, i386, aarch64, arm, asan, msan
+; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, aarch64, arm, asan, msan
 declare i8* @__cxa_allocate_exception(i64)
 declare void @__cxa_throw(i8*, i8*, i8*)
 declare i32 @__gxx_personality_v0(...)
 declare void @__cxa_end_catch()
 declare i8* @__cxa_begin_catch(i8*)
 
 @_ZTIi = external constant i8*
 

llvm/trunk/test/ExecutionEngine/MCJIT/eh-sm-pic.ll

 ; RUN: %lli -relocation-model=pic -code-model=small %s
-; XFAIL: cygwin, win32, mingw, mips, i686, i386, darwin, aarch64, arm, asan, msan
+; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, darwin, aarch64, arm, asan, msan
 declare i8* @__cxa_allocate_exception(i64)
 declare void @__cxa_throw(i8*, i8*, i8*)
 declare i32 @__gxx_personality_v0(...)
 declare void @__cxa_end_catch()
 declare i8* @__cxa_begin_catch(i8*)
 
 @_ZTIi = external constant i8*
 

llvm/trunk/test/ExecutionEngine/MCJIT/multi-module-sm-pic-a.ll

 ; RUN: %lli -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386
+; XFAIL: mips-, mipsel-, i686, i386
 
 declare i32 @FB()
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/MCJIT/remote/cross-module-sm-pic-a.ll

 ; RUN: %lli -extra-module=%p/Inputs/cross-module-b.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386, arm
+; XFAIL: mips-, mipsel-, i686, i386, arm
 
 declare i32 @FB()
 
 define i32 @FA() {
   ret i32 0
 }
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/MCJIT/remote/multi-module-sm-pic-a.ll

 ; RUN: %lli -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386, arm
+; XFAIL: mips-, mipsel-, i686, i386, arm
 
 declare i32 @FB()
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-sm-pic.ll

 ; RUN: %lli -remote-mcjit -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @count = global i32 1, align 4
 
 define i32 @main() nounwind uwtable {
 entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval

llvm/trunk/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-sm-pic.ll

 ; RUN: %lli -remote-mcjit -O0 -relocation-model=pic -code-model=small %s
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
 @ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
   %0 = load i8*, i8** @ptr, align 4
   %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
 }
 

llvm/trunk/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll

 ; RUN: %lli -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
-; XFAIL: mips, i686, i386, aarch64, arm
+; XFAIL: mips-, mipsel-, i686, i386, aarch64, arm
 
 define i32 @main() nounwind {
 entry:
   call void @lazily_compiled_address_is_consistent()
   ret i32 0
 }
 
 ; Test PR3043: @test should have the same address before and after

llvm/trunk/test/ExecutionEngine/MCJIT/test-global-init-nonzero-sm-pic.ll

 ; RUN: %lli -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @count = global i32 1, align 4
 
 define i32 @main() nounwind uwtable {
 entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval

llvm/trunk/test/ExecutionEngine/MCJIT/test-ptr-reloc-sm-pic.ll

 ; RUN: %lli -O0 -relocation-model=pic -code-model=small %s
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
 @ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
   %0 = load i8*, i8** @ptr, align 4
   %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
 }
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/cross-module-sm-pic-a.ll

 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386
+; XFAIL: mips-, mipsel-, i686, i386
 
 declare i32 @FB()
 
 define i32 @FA() {
   ret i32 0
 }
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=large %s
-; XFAIL: cygwin, win32, mingw, mips, i686, i386, aarch64, arm, asan, msan
+; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, aarch64, arm, asan, msan
 declare i8* @__cxa_allocate_exception(i64)
 declare void @__cxa_throw(i8*, i8*, i8*)
 declare i32 @__gxx_personality_v0(...)
 declare void @__cxa_end_catch()
 declare i8* @__cxa_begin_catch(i8*)
 
 @_ZTIi = external constant i8*
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/eh-sm-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=small %s
-; XFAIL: cygwin, win32, mingw, mips, i686, i386, darwin, aarch64, arm, asan, msan
+; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, darwin, aarch64, arm, asan, msan
 declare i8* @__cxa_allocate_exception(i64)
 declare void @__cxa_throw(i8*, i8*, i8*)
 declare i32 @__gxx_personality_v0(...)
 declare void @__cxa_end_catch()
 declare i8* @__cxa_begin_catch(i8*)
 
 @_ZTIi = external constant i8*
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/multi-module-sm-pic-a.ll

 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386
+; XFAIL: mips-, mipsel-, i686, i386
 
 declare i32 @FB()
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/remote/cross-module-sm-pic-a.ll

 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386, arm
+; XFAIL: mips-, mipsel-, i686, i386, arm
 
 declare i32 @FB()
 
 define i32 @FA() {
   ret i32 0
 }
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/remote/multi-module-sm-pic-a.ll

 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386, arm
+; XFAIL: mips-, mipsel-, i686, i386, arm
 
 declare i32 @FB()
 
 define i32 @main() {
   %r = call i32 @FB( )   ; <i32> [#uses=1]
   ret i32 %r
 }
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-sm-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @count = global i32 1, align 4
 
 define i32 @main() nounwind uwtable {
 entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval

llvm/trunk/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-sm-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -O0 -relocation-model=pic -code-model=small %s
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
 @ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
   %0 = load i8*, i8** @ptr, align 4
   %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
 }
 

llvm/trunk/test/ExecutionEngine/OrcMCJIT/stubs-sm-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
-; XFAIL: mips, i686, i386, aarch64, arm
+; XFAIL: mips-, mipsel-, i686, i386, aarch64, arm
 
 define i32 @main() nounwind {
 entry:
   call void @lazily_compiled_address_is_consistent()
   ret i32 0
 }
 
 ; Test PR3043: @test should have the same address before and after

llvm/trunk/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero-sm-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @count = global i32 1, align 4
 
 define i32 @main() nounwind uwtable {
 entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval

llvm/trunk/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc-sm-pic.ll

 ; RUN: %lli -jit-kind=orc-mcjit -O0 -relocation-model=pic -code-model=small %s
-; XFAIL: mips, aarch64, arm, i686, i386
+; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
 @ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
   %0 = load i8*, i8** @ptr, align 4
   %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
 }
 

llvm/trunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_Mips64r2N64_PIC_relocations.s

+# RUN: llvm-mc -triple=mips64el-unknown-linux -relocation-model=pic -code-model=small -filetype=obj -o %T/test_ELF_Mips64N64.o %s
+# RUN: llc -mtriple=mips64el-unknown-linux -relocation-model=pic -filetype=obj -o %T/test_ELF_ExternalFunction_Mips64N64.o %S/Inputs/ExternalFunction.ll
+# RUN: llvm-rtdyld -triple=mips64el-unknown-linux -verify -map-section test_ELF_Mips64N64.o,.text=0x1000 -map-section test_ELF_ExternalFunction_Mips64N64.o,.text=0x10000 -check=%s %/T/test_ELF_Mips64N64.o %T/test_ELF_ExternalFunction_Mips64N64.o
+
+  .text
+  .abicalls
+  .section  .mdebug.abi64,"",@progbits
+  .nan  legacy
+  .file "ELF_Mips64N64_PIC_relocations.ll"
+  .text
+  .globl  bar
+  .align  3
+  .type bar,@function
+  .set  nomicromips
+  .set  nomips16
+  .ent  bar
+bar:
+  .frame  $fp,40,$ra
+  .mask   0x00000000,0
+  .fmask  0x00000000,0
+  .set  noreorder
+  .set  nomacro
+  .set  noat
+  daddiu  $sp, $sp, -40
+  sd  $ra, 32($sp)
+  sd  $fp, 24($sp)
+  move   $fp, $sp
+  sd  $4, 16($fp)
+  lb  $2, 0($4)
+  sd  $4, 8($fp)
+
+# Test R_MIPS_26 relocation.
+# rtdyld-check:  decode_operand(insn1, 0)[25:0] = foo
+insn1:
+  jal   foo
+  nop
+
+# Test R_MIPS_PC16 relocation.
+# rtdyld-check:  decode_operand(insn2, 1)[15:0] = foo - insn2
+insn2:
+  bal   foo
+  nop
+
+  move   $sp, $fp
+  ld  $ra, 32($sp)
+  ld  $fp, 24($sp)
+  daddiu  $sp, $sp, 32
+  jr  $ra
+  nop
+  .set  at
+  .set  macro
+  .set  reorder
+  .end  bar
+$func_end0:
+  .size bar, ($func_end0)-bar
+
+  .globl  main
+  .align  3
+  .type main,@function
+  .set  nomicromips
+  .set  nomips16
+  .ent  main
+main:
+  .frame  $fp,32,$ra
+  .mask   0x00000000,0
+  .fmask  0x00000000,0
+  .set  noreorder
+  .set  nomacro
+  .set  noat
+  daddiu  $sp, $sp, -32
+  sd  $ra, 24($sp)
+  sd  $fp, 16($sp)
+  sd  $gp, 8($sp)
+  move   $fp, $sp
+
+# Check upper 16-bits of offset between the address of main function
+# and the global offset table.
+# rtdyld-check:  decode_operand(insn3, 1)[15:0] = ((section_addr(test_ELF_Mips64N64.o, .got) + 0x7ff0) - main + 0x8000)[31:16]
+insn3:
+  lui  $1, %hi(%neg(%gp_rel(main)))
+  daddu $1, $1, $25
+
+# Check lower 16-bits of offset between the address of main function
+# and the global offset table.
+# rtdyld-check:  decode_operand(insn4, 2)[15:0] = ((section_addr(test_ELF_Mips64N64.o, .got) + 0x7ff0) - main)[15:0]
+insn4:
+  daddiu  $1, $1, %lo(%neg(%gp_rel(main)))
+  sw  $zero, 4($fp)
+
+# $gp register contains address of the .got section + 0x7FF0. 0x7FF0 is
+# the offset of $gp from the beginning of the .got section. Check that we are
+# loading address of the page pointer from correct offset. In this case
+# the page pointer is the first entry in the .got section, so offset will be
+# 0 - 0x7FF0.
+# rtdyld-check:  decode_operand(insn5, 2)[15:0] = 0x8010
+#
+# Check that the global offset table contains the page pointer.
+# rtdyld-check: *{8}(section_addr(test_ELF_Mips64N64.o, .got)) = (_str + 0x8000) & 0xffffffffffff0000
+insn5:
+  ld  $25, %got_page(_str)($1)
+
+# Check the offset of _str from the page pointer.
+# rtdyld-check:  decode_operand(insn6, 2)[15:0] = _str[15:0]
+insn6:
+  daddiu  $25, $25, %got_ofst(_str)
+
+# Check that we are loading address of var from correct offset. In this case
+# var is the second entry in the .got section, so offset will be 8 - 0x7FF0.
+# rtdyld-check:  decode_operand(insn7, 2)[15:0] = 0x8018
+#
+# Check that the global offset table contains the address of the var.
+# rtdyld-check: *{8}(section_addr(test_ELF_Mips64N64.o, .got) + 8) = var
+insn7:
+  ld  $2, %got_disp(var)($1)
+  sd  $25, 0($2)
+
+# Check that we are loading address of bar from correct offset. In this case
+# bar is the third entry in the .got section, so offset will be 16 - 0x7FF0.
+# rtdyld-check:  decode_operand(insn8, 2)[15:0] = 0x8020
+#
+# Check that the global offset table contains the address of the bar.
+# rtdyld-check: *{8}(section_addr(test_ELF_Mips64N64.o, .got) + 16) = bar
+insn8:
+  ld  $2, %call16(bar)($1)
+
+  move   $4, $25
+  move   $gp, $1
+  move   $25, $2
+  jalr  $25
+  nop
+  move   $sp, $fp
+  ld  $gp, 8($sp)
+  ld  $fp, 16($sp)
+  ld  $ra, 24($sp)
+  daddiu  $sp, $sp, 32
+  jr  $ra
+  nop
+  .set  at
+  .set  macro
+  .set  reorder
+  .end  main
+$func_end1:
+  .size main, ($func_end1)-main
+
+  .type _str,@object
+  .section  .rodata.str1.1,"aMS",@progbits,1
+_str:
+  .asciz  "test"
+  .size _str, 5
+
+  .type var,@object
+  .comm var,8,8
+
+  .section  ".note.GNU-stack","",@progbits
+  .text

llvm/trunk/test/ExecutionEngine/RuntimeDyld/Mips/Inputs/ExternalFunction.ll

+define void @foo() {
+entry:
+  ret void
+}

llvm/trunk/test/ExecutionEngine/RuntimeDyld/Mips/lit.local.cfg

+if not 'Mips' in config.root.targets:
+    config.unsupported = True
+

llvm/trunk/unittests/ExecutionEngine/MCJIT/MCJITCAPITest.cpp

 protected:
   MCJITCAPITest() {
     // The architectures below are known to be compatible with MCJIT as they
     // are copied from test/ExecutionEngine/MCJIT/lit.local.cfg and should be
     // kept in sync.
     SupportedArchs.push_back(Triple::aarch64);
     SupportedArchs.push_back(Triple::arm);
     SupportedArchs.push_back(Triple::mips);
+    SupportedArchs.push_back(Triple::mips64);
+    SupportedArchs.push_back(Triple::mips64el);
     SupportedArchs.push_back(Triple::x86);
     SupportedArchs.push_back(Triple::x86_64);
 
     // Some architectures have sub-architectures in which tests will fail, like
     // ARM. These two vectors will define if they do have sub-archs (to avoid
     // extra work for those who don't), and if so, if they are listed to work
     HasSubArchs.push_back(Triple::arm);
     SupportedSubArchs.push_back("armv6");

llvm/trunk/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h

protected:
   {
     // The architectures below are known to be compatible with MCJIT as they
     // are copied from test/ExecutionEngine/MCJIT/lit.local.cfg and should be
     // kept in sync.
     SupportedArchs.push_back(Triple::aarch64);
     SupportedArchs.push_back(Triple::arm);
     SupportedArchs.push_back(Triple::mips);
     SupportedArchs.push_back(Triple::mipsel);
+    SupportedArchs.push_back(Triple::mips64);
+    SupportedArchs.push_back(Triple::mips64el);
     SupportedArchs.push_back(Triple::x86);
     SupportedArchs.push_back(Triple::x86_64);
 
     // Some architectures have sub-architectures in which tests will fail, like
     // ARM. These two vectors will define if they do have sub-archs (to avoid
     // extra work for those who don't), and if so, if they are listed to work
     HasSubArchs.push_back(Triple::arm);
     SupportedSubArchs.push_back("armv6");