RegAlloc: Fix assert if all registers in class reserved

[arsenm]

Summary

With a context instruction, this would produce a context
error. However, it would continue on and do an out of bounds access of
the empty allocation order array.

[arsenm]

ping

[arsenm]

1801e2aa249497adb5b0ab33e7fc5dd0ad4a4ab3

llvm/lib/CodeGen/RegAllocBase.cpp

if (AvailablePhysReg == ~0u) {
       for (MachineRegisterInfo::reg_instr_iterator
                I = MRI->reg_instr_begin(VirtReg->reg()),
                E = MRI->reg_instr_end();
            I != E;) {
         MI = &*(I++);
         if (MI->isInlineAsm())
           break;
       }
-      if (MI && MI->isInlineAsm()) {
+
+      const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg());
+      ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
+      if (AllocOrder.empty())
+        report_fatal_error("no registers from class available to allocate");
+      else if (MI && MI->isInlineAsm()) {
         MI->emitError("inline assembly requires more registers than available");
       } else if (MI) {
         LLVMContext &Context =
             MI->getParent()->getParent()->getMMI().getModule()->getContext();
         Context.emitError("ran out of registers during register allocation");
       } else {
         report_fatal_error("ran out of registers during register allocation");
       }
+
       // Keep going after reporting the error.
-      VRM->assignVirt2Phys(
-          VirtReg->reg(),
-          RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg())).front());
+      VRM->assignVirt2Phys(VirtReg->reg(), AllocOrder.front());
       continue;
     }
 
     if (AvailablePhysReg)
       Matrix->assign(*VirtReg, AvailablePhysReg);
 
     for (Register Reg : SplitVRegs) {
       assert(LIS->hasInterval(Reg));

llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir

+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=greedy -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
+
+# Check that there isn't an assert if we try to allocate a virtual register from
+# a class where all registers are reserved. All AGPRs are reserved on subtargets
+# that do not have them.
+
+# CHECK-NOT: ran out of registers during register allocation
+# CHECK: LLVM ERROR: no registers from class available to allocate
+# CHECK-NOT: ran out of registers during register allocation
+
+---
+name: use_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:agpr_32 = IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...