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Differential D93440

[NFC][AMDGPU] Format change to processr table in AMGPUUsage.rst
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Authored by t-tye on Dec 16 2020, 6:49 PM.

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rampitec
kzhuravl
Commits
rG8c6d516286d5: [NFC][AMDGPU] Reorganize description of scratch handling

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t-tye created this revision.Dec 16 2020, 6:49 PM
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t-tye updated this revision to Diff 312361.Dec 16 2020, 7:06 PM

Correct typo.

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rampitec accepted this revision.Dec 16 2020, 11:39 PM
This revision is now accepted and ready to land.Dec 16 2020, 11:39 PM
t-tye updated this revision to Diff 312396.Dec 17 2020, 12:49 AM

Reorganize scratch description.

Harbormaster completed remote builds in B82744: Diff 312396.Dec 17 2020, 1:21 AM
rampitec accepted this revision.Dec 17 2020, 10:45 AM
Closed by commit rG8c6d516286d5: [NFC][AMDGPU] Reorganize description of scratch handling (authored by t-tye). · Explain WhyDec 17 2020, 11:34 AM
This revision was automatically updated to reflect the committed changes.
t-tye added a commit: rG8c6d516286d5: [NFC][AMDGPU] Reorganize description of scratch handling.

Revision Contents

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llvm/
docs/
610 lines

Diff 312570

llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
Use the Clang options ``-mcpu=<target-id>`` or ``--offload-arch=<target-id>`` to Use the Clang options ``-mcpu=<target-id>`` or ``--offload-arch=<target-id>`` to
specify the AMDGPU processor together with optional target features. See specify the AMDGPU processor together with optional target features. See
:ref:`amdgpu-target-id` and :ref:`amdgpu-target-features` for AMD GPU target :ref:`amdgpu-target-id` and :ref:`amdgpu-target-features` for AMD GPU target
specific information. specific information.
.. table:: AMDGPU Processors .. table:: AMDGPU Processors
:name: amdgpu-processor-table :name: amdgpu-processor-table
=========== =============== ============ ===== ================= =========== =============== ====================== =========== =============== ============ ===== ================= =============== =============== ======================
Processor Alternative Target dGPU/ Target Target OS Support Example Processor Alternative Target dGPU/ Target Target OS Support Example
Processor Triple APU Features Properties *(see* Products Processor Triple APU Features Properties *(see* Products
Architecture Supported `amdgpu-os`_ Architecture Supported `amdgpu-os`_
*and *and
corresponding corresponding
runtime release runtime release
notes for notes for
current current
information and information and
level of level of
support)* support)*
=========== =============== ============ ===== ================= =========== =============== ====================== =========== =============== ============ ===== ================= =============== =============== ======================
**Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_ **Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``r600`` ``r600`` dGPU - Does not ``r600`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``r630`` ``r600`` dGPU - Does not ``r630`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``rs880`` ``r600`` dGPU - Does not ``rs880`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``rv670`` ``r600`` dGPU - Does not ``rv670`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
**Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_ **Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``rv710`` ``r600`` dGPU - Does not ``rv710`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``rv730`` ``r600`` dGPU - Does not ``rv730`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``rv770`` ``r600`` dGPU - Does not ``rv770`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
**Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_ **Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``cedar`` ``r600`` dGPU - Does not ``cedar`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``cypress`` ``r600`` dGPU - Does not ``cypress`` ``r600`` dGPU - Does not
support support
generic generic
Show All 10 Lines ``redwood`` ``r600`` dGPU - Does not
address address
space space
``sumo`` ``r600`` dGPU - Does not ``sumo`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
**Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_ **Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``barts`` ``r600`` dGPU - Does not ``barts`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``caicos`` ``r600`` dGPU - Does not ``caicos`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``cayman`` ``r600`` dGPU - Does not ``cayman`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
``turks`` ``r600`` dGPU - Does not ``turks`` ``r600`` dGPU - Does not
support support
generic generic
address address
space space
**GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_ **GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx600`` - ``tahiti`` ``amdgcn`` dGPU - Does not - *pal-amdpal* ``gfx600`` - ``tahiti`` ``amdgcn`` dGPU - Does not - *pal-amdpal*
support support
generic generic
address address
space space
``gfx601`` - ``pitcairn`` ``amdgcn`` dGPU - Does not - *pal-amdpal* ``gfx601`` - ``pitcairn`` ``amdgcn`` dGPU - Does not - *pal-amdpal*
- ``verde`` support - ``verde`` support
generic generic
address address
space space
``gfx602`` - ``hainan`` ``amdgcn`` dGPU - Does not - *pal-amdpal* ``gfx602`` - ``hainan`` ``amdgcn`` dGPU - Does not - *pal-amdpal*
- ``oland`` support - ``oland`` support
generic generic
address address
space space
**GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_ **GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx700`` - ``kaveri`` ``amdgcn`` APU - *rocm-amdhsa* - A6-7000 ``gfx700`` - ``kaveri`` ``amdgcn`` APU - Offset - *rocm-amdhsa* - A6-7000
- *pal-amdhsa* - A6 Pro-7050B flat - *pal-amdhsa* - A6 Pro-7050B
- *pal-amdpal* - A8-7100 scratch - *pal-amdpal* - A8-7100
- A8 Pro-7150B - A8 Pro-7150B
- A10-7300 - A10-7300
- A10 Pro-7350B - A10 Pro-7350B
- FX-7500 - FX-7500
- A8-7200P - A8-7200P
- A10-7400P - A10-7400P
- FX-7600P - FX-7600P
``gfx701`` - ``hawaii`` ``amdgcn`` dGPU - *rocm-amdhsa* - FirePro W8100 ``gfx701`` - ``hawaii`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - FirePro W8100
- *pal-amdhsa* - FirePro W9100 flat - *pal-amdhsa* - FirePro W9100
- *pal-amdpal* - FirePro S9150 scratch - *pal-amdpal* - FirePro S9150
- FirePro S9170 - FirePro S9170
``gfx702`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon R9 290 ``gfx702`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon R9 290
- *pal-amdhsa* - Radeon R9 290x flat - *pal-amdhsa* - Radeon R9 290x
- *pal-amdpal* - Radeon R390 scratch - *pal-amdpal* - Radeon R390
- Radeon R390x - Radeon R390x
``gfx703`` - ``kabini`` ``amdgcn`` APU - *pal-amdhsa* - E1-2100 ``gfx703`` - ``kabini`` ``amdgcn`` APU - Offset - *pal-amdhsa* - E1-2100
- ``mullins`` - *pal-amdpal* - E1-2200 - ``mullins`` flat - *pal-amdpal* - E1-2200
- E1-2500 scratch - E1-2500
- E2-3000 - E2-3000
- E2-3800 - E2-3800
- A4-5000 - A4-5000
- A4-5100 - A4-5100
- A6-5200 - A6-5200
- A4 Pro-3340B - A4 Pro-3340B
``gfx704`` - ``bonaire`` ``amdgcn`` dGPU - *pal-amdhsa* - Radeon HD 7790 ``gfx704`` - ``bonaire`` ``amdgcn`` dGPU - Offset - *pal-amdhsa* - Radeon HD 7790
- *pal-amdpal* - Radeon HD 8770 flat - *pal-amdpal* - Radeon HD 8770
- R7 260 scratch - R7 260
- R7 260X - R7 260X
``gfx705`` ``amdgcn`` APU - *pal-amdhsa* *TBA* ``gfx705`` ``amdgcn`` APU - Offset - *pal-amdhsa* *TBA*
- *pal-amdpal* flat - *pal-amdpal*
.. TODO:: scratch .. TODO::
Add product Add product
names. names.
**GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_ **GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx801`` - ``carrizo`` ``amdgcn`` APU - xnack - *rocm-amdhsa* - A6-8500P ``gfx801`` - ``carrizo`` ``amdgcn`` APU - xnack - Offset - *rocm-amdhsa* - A6-8500P
- *pal-amdhsa* - Pro A6-8500B flat - *pal-amdhsa* - Pro A6-8500B
- *pal-amdpal* - A8-8600P scratch - *pal-amdpal* - A8-8600P
- Pro A8-8600B - Pro A8-8600B
- FX-8800P - FX-8800P
- Pro A12-8800B - Pro A12-8800B
- A10-8700P - A10-8700P
- Pro A10-8700B - Pro A10-8700B
- A10-8780P - A10-8780P
- A10-9600P - A10-9600P
- A10-9630P - A10-9630P
- A12-9700P - A12-9700P
- A12-9730P - A12-9730P
- FX-9800P - FX-9800P
- FX-9830P - FX-9830P
- E2-9010 - E2-9010
- A6-9210 - A6-9210
- A9-9410 - A9-9410
``gfx802`` - ``iceland`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon R9 285 ``gfx802`` - ``iceland`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon R9 285
- ``tonga`` - *pal-amdhsa* - Radeon R9 380 - ``tonga`` flat - *pal-amdhsa* - Radeon R9 380
- *pal-amdpal* - Radeon R9 385 scratch - *pal-amdpal* - Radeon R9 385
``gfx803`` - ``fiji`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon R9 Nano ``gfx803`` - ``fiji`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon R9 Nano
- *pal-amdhsa* - Radeon R9 Fury - *pal-amdhsa* - Radeon R9 Fury
- *pal-amdpal* - Radeon R9 FuryX - *pal-amdpal* - Radeon R9 FuryX
- Radeon Pro Duo - Radeon Pro Duo
- FirePro S9300x2 - FirePro S9300x2
- Radeon Instinct MI8 - Radeon Instinct MI8
\ - ``polaris10`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon RX 470 \ - ``polaris10`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon RX 470
- *pal-amdhsa* - Radeon RX 480 flat - *pal-amdhsa* - Radeon RX 480
- *pal-amdpal* - Radeon Instinct MI6 scratch - *pal-amdpal* - Radeon Instinct MI6
\ - ``polaris11`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon RX 460 \ - ``polaris11`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon RX 460
- *pal-amdhsa* flat - *pal-amdhsa*
- *pal-amdpal* scratch - *pal-amdpal*
``gfx805`` - ``tongapro`` ``amdgcn`` dGPU - *rocm-amdhsa* - FirePro S7150 ``gfx805`` - ``tongapro`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - FirePro S7150
- *pal-amdhsa* - FirePro S7100 flat - *pal-amdhsa* - FirePro S7100
- *pal-amdpal* - FirePro W7100 scratch - *pal-amdpal* - FirePro W7100
- Mobile FirePro - Mobile FirePro
M7170 M7170
``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack - *rocm-amdhsa* *TBA* ``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack - Offset - *rocm-amdhsa* *TBA*
- *pal-amdhsa* flat - *pal-amdhsa*
- *pal-amdpal* .. TODO:: scratch - *pal-amdpal* .. TODO::
Add product Add product
names. names.
**GCN GFX9 (Vega)** [AMD-GCN-GFX9]_ **GCN GFX9 (Vega)** [AMD-GCN-GFX9]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx900`` ``amdgcn`` dGPU - xnack - *rocm-amdhsa* - Radeon Vega ``gfx900`` ``amdgcn`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega
- *pal-amdhsa* Frontier Edition flat - *pal-amdhsa* Frontier Edition
- *pal-amdpal* - Radeon RX Vega 56 scratch - *pal-amdpal* - Radeon RX Vega 56
- Radeon RX Vega 64 - Radeon RX Vega 64
- Radeon RX Vega 64 - Radeon RX Vega 64
Liquid Liquid
- Radeon Instinct MI25 - Radeon Instinct MI25
``gfx902`` ``amdgcn`` APU - xnack - *rocm-amdhsa* - Ryzen 3 2200G ``gfx902`` ``amdgcn`` APU - xnack - Absolute - *rocm-amdhsa* - Ryzen 3 2200G
- *pal-amdhsa* - Ryzen 5 2400G flat - *pal-amdhsa* - Ryzen 5 2400G
- *pal-amdpal* scratch - *pal-amdpal*
``gfx904`` ``amdgcn`` dGPU - xnack - *rocm-amdhsa* *TBA* ``gfx904`` ``amdgcn`` dGPU - xnack - *rocm-amdhsa* *TBA*
- *pal-amdhsa* - *pal-amdhsa*
- *pal-amdpal* .. TODO:: - *pal-amdpal* .. TODO::
Add product Add product
names. names.
``gfx906`` ``amdgcn`` dGPU - sramecc - *rocm-amdhsa* - Radeon Instinct MI50 ``gfx906`` ``amdgcn`` dGPU - sramecc - Absolute - *rocm-amdhsa* - Radeon Instinct MI50
- xnack - *pal-amdhsa* - Radeon Instinct MI60 - xnack flat - *pal-amdhsa* - Radeon Instinct MI60
- *pal-amdpal* - Radeon VII scratch - *pal-amdpal* - Radeon VII
- Radeon Pro VII - Radeon Pro VII
``gfx908`` ``amdgcn`` dGPU - sramecc - *rocm-amdhsa* *TBA* ``gfx908`` ``amdgcn`` dGPU - sramecc - *rocm-amdhsa* *TBA*
- xnack - xnack - Absolute
.. TODO:: flat .. TODO::
scratch
Add product Add product
names. names.
``gfx909`` ``amdgcn`` APU - xnack - *pal-amdpal* *TBA* ``gfx909`` ``amdgcn`` APU - xnack - Absolute - *pal-amdpal* *TBA*
flat
.. TODO:: scratch .. TODO::
Add product Add product
names. names.
``gfx90c`` ``amdgcn`` APU - xnack - *pal-amdpal* - Ryzen 7 4700G ``gfx90c`` ``amdgcn`` APU - xnack - Absolute - *pal-amdpal* - Ryzen 7 4700G
- Ryzen 7 4700GE flat - Ryzen 7 4700GE
- Ryzen 5 4600G scratch - Ryzen 5 4600G
- Ryzen 5 4600GE - Ryzen 5 4600GE
- Ryzen 3 4300G - Ryzen 3 4300G
- Ryzen 3 4300GE - Ryzen 3 4300GE
- Ryzen Pro 4000G - Ryzen Pro 4000G
- Ryzen 7 Pro 4700G - Ryzen 7 Pro 4700G
- Ryzen 7 Pro 4750GE - Ryzen 7 Pro 4750GE
- Ryzen 5 Pro 4650G - Ryzen 5 Pro 4650G
- Ryzen 5 Pro 4650GE - Ryzen 5 Pro 4650GE
- Ryzen 3 Pro 4350G - Ryzen 3 Pro 4350G
- Ryzen 3 Pro 4350GE - Ryzen 3 Pro 4350GE
**GCN GFX10 (RDNA 1)** [AMD-GCN-GFX10-RDNA1]_ **GCN GFX10 (RDNA 1)** [AMD-GCN-GFX10-RDNA1]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx1010`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* - Radeon RX 5700 ``gfx1010`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5700
- wavefrontsize64 - *pal-amdhsa* - Radeon RX 5700 XT - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5700 XT
- xnack - *pal-amdpal* - Radeon Pro 5600 XT - xnack scratch - *pal-amdpal* - Radeon Pro 5600 XT
- Radeon Pro 5600M - Radeon Pro 5600M
``gfx1011`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* *TBA* ``gfx1011`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* *TBA*
- wavefrontsize64 - *pal-amdhsa* - wavefrontsize64 - Absolute - *pal-amdhsa*
- xnack - *pal-amdpal* - xnack flat - *pal-amdpal*
.. TODO:: scratch .. TODO::
Add product Add product
names. names.
``gfx1012`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* - Radeon RX 5500 ``gfx1012`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5500
- wavefrontsize64 - *pal-amdhsa* - Radeon RX 5500 XT - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5500 XT
- xnack - *pal-amdpal* - xnack scratch - *pal-amdpal*
**GCN GFX10 (RDNA 2)** [AMD-GCN-GFX10-RDNA2]_ **GCN GFX10 (RDNA 2)** [AMD-GCN-GFX10-RDNA2]_
------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx1030`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* *TBA* ``gfx1030`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA*
- wavefrontsize64 - *pal-amdhsa* - wavefrontsize64 flat - *pal-amdhsa*
- *pal-amdpal* .. TODO:: scratch - *pal-amdpal* .. TODO::
Add product Add product
names. names.
``gfx1031`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* *TBA* ``gfx1031`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA*
- wavefrontsize64 - *pal-amdhsa* - wavefrontsize64 flat - *pal-amdhsa*
- *pal-amdpal* .. TODO:: scratch - *pal-amdpal* .. TODO::
Add product Add product
names. names.
``gfx1032`` ``amdgcn`` dGPU - cumode - *pal-amdhsa* *TBA* ``gfx1032`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA*
- wavefrontsize64 - *pal-amdhsa* - wavefrontsize64 flat - *pal-amdhsa*
- *pal-amdpal* .. TODO:: scratch - *pal-amdpal* .. TODO::
Add product Add product
names. names.
``gfx1033`` ``amdgcn`` APU - cumode - *pal-amdpal* *TBA* ``gfx1033`` ``amdgcn`` APU - cumode - Absolute - *pal-amdpal* *TBA*
- wavefrontsize64 - wavefrontsize64 flat
.. TODO:: scratch .. TODO::
Add product Add product
names. names.
=========== =============== ============ ===== ================= =========== =============== ====================== =========== =============== ============ ===== ================= =============== =============== ======================
.. _amdgpu-target-features: .. _amdgpu-target-features:
Target Features Target Features
--------------- ---------------
Target features control how code is generated to support certain Target features control how code is generated to support certain
processor specific features. Not all target features are supported by processor specific features. Not all target features are supported by
▲ Show 20 Lines • Show All 3,735 Lines • ▼ Show 20 Lines:ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
.. table:: SGPR Register Set Up Order .. table:: SGPR Register Set Up Order
:name: amdgpu-amdhsa-sgpr-register-set-up-order-table :name: amdgpu-amdhsa-sgpr-register-set-up-order-table
========== ========================== ====== ============================== ========== ========================== ====== ==============================
SGPR Order Name Number Description SGPR Order Name Number Description
(kernel descriptor enable of (kernel descriptor enable of
field) SGPRs field) SGPRs
========== ========================== ====== ============================== ========== ========================== ====== ==============================
First Private Segment Buffer 4 This is 4 SGPRs: First Private Segment Buffer 4 See
(enable_sgpr_private (enable_sgpr_private :ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`.
_segment_buffer) _segment_buffer)
V# that can be used,
together with Scratch
Wavefront Offset as an
offset, to access the
private memory space using a
segment address.
CP uses the value provided
by the runtime.
then Dispatch Ptr 2 64-bit address of AQL dispatch then Dispatch Ptr 2 64-bit address of AQL dispatch
(enable_sgpr_dispatch_ptr) packet for kernel dispatch (enable_sgpr_dispatch_ptr) packet for kernel dispatch
actually executing. actually executing.
then Queue Ptr 2 64-bit address of amd_queue_t then Queue Ptr 2 64-bit address of amd_queue_t
(enable_sgpr_queue_ptr) object for AQL queue on which (enable_sgpr_queue_ptr) object for AQL queue on which
the dispatch packet was the dispatch packet was
queued. queued.
then Kernarg Segment Ptr 2 64-bit address of Kernarg then Kernarg Segment Ptr 2 64-bit address of Kernarg
(enable_sgpr_kernarg segment. This is directly (enable_sgpr_kernarg segment. This is directly
_segment_ptr) copied from the _segment_ptr) copied from the
kernarg_address in the kernel kernarg_address in the kernel
dispatch packet. dispatch packet.
Having CP load it once avoids Having CP load it once avoids
loading it at the beginning of loading it at the beginning of
every wavefront. every wavefront.
then Dispatch Id 2 64-bit Dispatch ID of the then Dispatch Id 2 64-bit Dispatch ID of the
(enable_sgpr_dispatch_id) dispatch packet being (enable_sgpr_dispatch_id) dispatch packet being
executed. executed.
then Flat Scratch Init 2 This is 2 SGPRs: then Flat Scratch Init 2 See
(enable_sgpr_flat_scratch :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
_init) GFX6
Not supported.
GFX7-GFX8
The first SGPR is a 32-bit
byte offset from
``SH_HIDDEN_PRIVATE_BASE_VIMID``
to per SPI base of memory
for scratch for the queue
executing the kernel
dispatch. CP obtains this
from the runtime. (The
Scratch Segment Buffer base
address is
``SH_HIDDEN_PRIVATE_BASE_VIMID``
plus this offset.) The value
of Scratch Wavefront Offset must
be added to this offset by
the kernel machine code,
right shifted by 8, and
moved to the FLAT_SCRATCH_HI
SGPR register.
FLAT_SCRATCH_HI corresponds
to SGPRn-4 on GFX7, and
SGPRn-6 on GFX8 (where SGPRn
is the highest numbered SGPR
allocated to the wavefront).
FLAT_SCRATCH_HI is
multiplied by 256 (as it is
in units of 256 bytes) and
added to
``SH_HIDDEN_PRIVATE_BASE_VIMID``
to calculate the per wavefront
FLAT SCRATCH BASE in flat
memory instructions that
access the scratch
aperture.
The second SGPR is 32-bit
byte size of a single
work-item's scratch memory
usage. CP obtains this from
the runtime, and it is
always a multiple of DWORD.
CP checks that the value in
the kernel dispatch packet
Private Segment Byte Size is
not larger and requests the
runtime to increase the
queue's scratch size if
necessary. The kernel code
must move it to
FLAT_SCRATCH_LO which is
SGPRn-3 on GFX7 and SGPRn-5
on GFX8. FLAT_SCRATCH_LO is
used as the FLAT SCRATCH
SIZE in flat memory
instructions. Having CP load
it once avoids loading it at
the beginning of every
wavefront.
GFX9-GFX10
This is the
64-bit base address of the
per SPI scratch backing
memory managed by SPI for
the queue executing the
kernel dispatch. CP obtains
this from the runtime (and
divides it if there are
multiple Shader Arrays each
with its own SPI). The value
of Scratch Wavefront Offset must
be added by the kernel
machine code and the result
moved to the FLAT_SCRATCH
SGPR which is SGPRn-6 and
SGPRn-5. It is used as the
FLAT SCRATCH BASE in flat
memory instructions.
then Private Segment Size 1 The 32-bit byte size of a then Private Segment Size 1 The 32-bit byte size of a
(enable_sgpr_private single (enable_sgpr_private single
work-item's work-item's
scratch_segment_size) memory scratch_segment_size) memory
allocation. This is the allocation. This is the
value from the kernel value from the kernel
dispatch packet Private dispatch packet Private
Segment Byte Size rounded up Segment Byte Size rounded up
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines then Work-Group Id Y 1 32-bit work-group id in Y
(enable_sgpr_workgroup_id dimension of grid for (enable_sgpr_workgroup_id dimension of grid for
_Y) wavefront. _Y) wavefront.
then Work-Group Id Z 1 32-bit work-group id in Z then Work-Group Id Z 1 32-bit work-group id in Z
(enable_sgpr_workgroup_id dimension of grid for (enable_sgpr_workgroup_id dimension of grid for
_Z) wavefront. _Z) wavefront.
then Work-Group Info 1 {first_wavefront, 14'b0000, then Work-Group Info 1 {first_wavefront, 14'b0000,
(enable_sgpr_workgroup ordered_append_term[10:0], (enable_sgpr_workgroup ordered_append_term[10:0],
_info) threadgroup_size_in_wavefronts[5:0]} _info) threadgroup_size_in_wavefronts[5:0]}
then Scratch Wavefront Offset 1 This is 1 SGPR: then Scratch Wavefront Offset 1 See
(enable_sgpr_private (enable_sgpr_private :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
_segment_wavefront_offset) _segment_wavefront_offset) and
32-bit byte offset from base :ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`.
of scratch base of queue
executing the kernel
dispatch. Must be used as an
offset with Private segment
address when using Scratch
Segment Buffer. It must be
used to set up FLAT SCRATCH
for flat addressing (see
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`).
========== ========================== ====== ============================== ========== ========================== ====== ==============================
The order of the VGPR registers is defined, but the compiler can specify which The order of the VGPR registers is defined, but the compiler can specify which
ones are actually setup in the kernel descriptor using the ``enable_vgpr*`` bit ones are actually setup in the kernel descriptor using the ``enable_vgpr*`` bit
fields (see :ref:`amdgpu-amdhsa-kernel-descriptor`). The register numbers used fields (see :ref:`amdgpu-amdhsa-kernel-descriptor`). The register numbers used
for enabled registers are dense starting at VGPR0: the first enabled register is for enabled registers are dense starting at VGPR0: the first enabled register is
VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
VGPR number. VGPR number.
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The setting of registers is done by GPU CP/ADC/SPI hardware as follows: The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
1. SGPRs before the Work-Group Ids are set by CP using the 16 User Data 1. SGPRs before the Work-Group Ids are set by CP using the 16 User Data
registers. registers.
2. Work-group Id registers X, Y, Z are set by ADC which supports any 2. Work-group Id registers X, Y, Z are set by ADC which supports any
combination including none. combination including none.
3. Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why 3. Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
its value cannot be included with the flat scratch init value which is per its value cannot be included with the flat scratch init value which is per
queue. queue (see :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`).
4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y) 4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
or (X, Y, Z). or (X, Y, Z).
5. Flat Scratch register pair initialization is described in
See :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch` for Flat Scratch register :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
pair initialization.
The global segment can be accessed either using buffer instructions (GFX6 which The global segment can be accessed either using buffer instructions (GFX6 which
has V# 64-bit address support), flat instructions (GFX7-GFX10), or global has V# 64-bit address support), flat instructions (GFX7-GFX10), or global
instructions (GFX9-GFX10). instructions (GFX9-GFX10).
If buffer operations are used, then the compiler can generate a V# with the If buffer operations are used, then the compiler can generate a V# with the
following properties: following properties:
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kernel prolog. If a frame pointer is not required then all uses of the frame kernel prolog. If a frame pointer is not required then all uses of the frame
pointer are replaced with immediate ``0`` offsets. pointer are replaced with immediate ``0`` offsets.
.. _amdgpu-amdhsa-kernel-prolog-flat-scratch: .. _amdgpu-amdhsa-kernel-prolog-flat-scratch:
Flat Scratch Flat Scratch
++++++++++++ ++++++++++++
GFX6 There are different methods used for initializing flat scratch:
Flat scratch is not supported.
* If the *Target Properties* column of :ref:`amdgpu-processor-table`
specifies *Does not support generic address space*:
Flat scratch is not supported and there is no flat scratch register pair.
* If the *Target Properties* column of :ref:`amdgpu-processor-table`
specifies *Offset flat scratch*:
GFX7-GFX10
If the kernel or any function it calls may use flat operations to access If the kernel or any function it calls may use flat operations to access
scratch memory, the prolog code must set up the FLAT_SCRATCH register pair scratch memory, the prolog code must set up the FLAT_SCRATCH register pair
(FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which are in SGPRn-4/SGPRn-3). Initialization (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI). Initialization uses Flat Scratch Init and
uses Flat Scratch Init and Scratch Wavefront Offset SGPR registers (see Scratch Wavefront Offset SGPR registers (see
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`): :ref:`amdgpu-amdhsa-initial-kernel-execution-state`):
GFX7-GFX8 1. The low word of Flat Scratch Init is the 32-bit byte offset from
1. The low word of Flat Scratch Init is 32-bit byte offset from
``SH_HIDDEN_PRIVATE_BASE_VIMID`` to the base of scratch backing memory ``SH_HIDDEN_PRIVATE_BASE_VIMID`` to the base of scratch backing memory
being managed by SPI for the queue executing the kernel dispatch. This is being managed by SPI for the queue executing the kernel dispatch. This is
the same value used in the Scratch Segment Buffer V# base address. The the same value used in the Scratch Segment Buffer V# base address.
prolog must add the value of Scratch Wavefront Offset to get the
CP obtains this from the runtime. (The Scratch Segment Buffer base address
is ``SH_HIDDEN_PRIVATE_BASE_VIMID`` plus this offset.)
The prolog must add the value of Scratch Wavefront Offset to get the
wavefront's byte scratch backing memory offset from wavefront's byte scratch backing memory offset from
``SH_HIDDEN_PRIVATE_BASE_VIMID``. Since FLAT_SCRATCH_LO is in units of 256 ``SH_HIDDEN_PRIVATE_BASE_VIMID``.
bytes, the offset must be right shifted by 8 before moving into
FLAT_SCRATCH_LO. The Scratch Wavefront Offset must also be used as an offset with Private
segment address when using the Scratch Segment Buffer.
Since FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right
shifted by 8 before moving into FLAT_SCRATCH_HI.
FLAT_SCRATCH_HI corresponds to SGPRn-4 on GFX7, and SGPRn-6 on GFX8 (where
SGPRn is the highest numbered SGPR allocated to the wavefront).
FLAT_SCRATCH_HI is multiplied by 256 (as it is in units of 256 bytes) and
added to ``SH_HIDDEN_PRIVATE_BASE_VIMID`` to calculate the per wavefront
FLAT SCRATCH BASE in flat memory instructions that access the scratch
aperture.
2. The second word of Flat Scratch Init is 32-bit byte size of a single 2. The second word of Flat Scratch Init is 32-bit byte size of a single
work-items scratch memory usage. This is directly loaded from the kernel work-items scratch memory usage.
dispatch packet Private Segment Byte Size and rounded up to a multiple of
DWORD. Having CP load it once avoids loading it at the beginning of every
wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT
SCRATCH SIZE.
GFX9-GFX10 CP obtains this from the runtime, and it is always a multiple of DWORD. CP
The Flat Scratch Init is the 64-bit address of the base of scratch backing checks that the value in the kernel dispatch packet Private Segment Byte
memory being managed by SPI for the queue executing the kernel dispatch. The Size is not larger and requests the runtime to increase the queue's scratch
prolog must add the value of the wave's Scratch Wavefront Offset and moved size if necessary.
as a 64-bit value to the FLAT_SCRATCH pair for use as the flat scratch base
CP directly loads from the kernel dispatch packet Private Segment Byte Size
field and rounds up to a multiple of DWORD. Having CP load it once avoids
loading it at the beginning of every wavefront.
The kernel prolog code must move it to FLAT_SCRATCH_LO which is SGPRn-3 on
GFX7 and SGPRn-5 on GFX8. FLAT_SCRATCH_LO is used as the FLAT SCRATCH SIZE
in flat memory instructions. in flat memory instructions.
* If the *Target Properties* column of :ref:`amdgpu-processor-table`
specifies *Absolute flat scratch*:
If the kernel or any function it calls may use flat operations to access
scratch memory, the prolog code must set up the FLAT_SCRATCH register pair
(FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which are in SGPRn-4/SGPRn-3). Initialization
uses Flat Scratch Init and Scratch Wavefront Offset SGPR registers (see
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`):
The Flat Scratch Init is the 64-bit address of the base of scratch backing
memory being managed by SPI for the queue executing the kernel dispatch.
CP obtains this from the runtime.
The kernel prolog must add the value of the wave's Scratch Wavefront Offset
and move the result as a 64-bit value to the FLAT_SCRATCH SGPR register pair
which is SGPRn-6 and SGPRn-5. It is used as the FLAT SCRATCH BASE in flat
memory instructions.
The Scratch Wavefront Offset must also be used as an offset with Private
segment address when using the Scratch Segment Buffer (see
:ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`).
.. _amdgpu-amdhsa-kernel-prolog-private-segment-buffer: .. _amdgpu-amdhsa-kernel-prolog-private-segment-buffer:
Private Segment Buffer Private Segment Buffer
++++++++++++++++++++++ ++++++++++++++++++++++
A set of four SGPRs beginning at a four-aligned SGPR index are always selected Private Segment Buffer SGPR register is used to initilize 4 SGPRs
to serve as the scratch V# for the kernel as follows: that are used as a V# to access scratch. CP uses the value provided by the
runtime. It is used, together with Scratch Wavefront Offset as an offset, to
access the private memory space using a segment address. See
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`.
The scratch V# is a four-aligned SGPR and always selected for the kernel as
follows:
- If it is known during instruction selection that there is stack usage, - If it is known during instruction selection that there is stack usage,
SGPR0-3 is reserved for use as the scratch V#. Stack usage is assumed if SGPR0-3 is reserved for use as the scratch V#. Stack usage is assumed if
optimizations are disabled (``-O0``), if stack objects already exist (for optimizations are disabled (``-O0``), if stack objects already exist (for
locals, etc.), or if there are any function calls. locals, etc.), or if there are any function calls.
- Otherwise, four high numbered SGPRs beginning at a four-aligned SGPR index - Otherwise, four high numbered SGPRs beginning at a four-aligned SGPR index
are reserved for the tentative scratch V#. These will be used if it is are reserved for the tentative scratch V#. These will be used if it is
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