This is an archive of the discontinued LLVM Phabricator instance.

Differential D9339

[mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size directive. NFC.
ClosedPublic

Authored by dsanders on Apr 29 2015, 5:25 AM.

Details

Reviewers
vkalintiris
Commits
rGfa159165be95: [mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size…
rL236219: [mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size…
Summary

Depends on D9338

Diff Detail

Event Timeline

dsanders updated this revision to Diff 24615.Apr 29 2015, 5:25 AM
dsanders retitled this revision from to [mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size directive. NFC..
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added a reviewer: vkalintiris.
dsanders added a parent revision: D9338: [mips] Add missing signext attributes to MSA basic operations tests. NFC..
dsanders mentioned this in D9340: [mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFC.
dsanders added a subscriber: Unknown Object (MLST).
vkalintiris accepted this revision.Apr 29 2015, 8:42 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 29 2015, 8:42 AM
dsanders closed this revision.Apr 30 2015, 2:59 AM

Revision Contents

PathSize
test/
CodeGen/
Mips/
msa/
43 lines
15 lines

Diff 24615

test/CodeGen/Mips/msa/basic_operations.ll

Show All 36 Linesdefine void @const_v16i8() nounwind {
; MIPS32-LE-DAG: ori [[R2]], [[R2]], 513 ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 513
; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
; MIPS32-AE: .size const_v16i8
} }
define void @const_v8i16() nounwind { define void @const_v8i16() nounwind {
; MIPS32-AE-LABEL: const_v8i16: ; MIPS32-AE-LABEL: const_v8i16:
store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
Show All 14 Linesdefine void @const_v8i16() nounwind {
; MIPS32-LE-DAG: ori [[R2]], [[R2]], 1 ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 1
; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
; MIPS32-AE: .size const_v8i16
} }
define void @const_v4i32() nounwind { define void @const_v4i32() nounwind {
; MIPS32-AE-LABEL: const_v4i32: ; MIPS32-AE-LABEL: const_v4i32:
store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
Show All 14 Linesdefine void @const_v4i32() nounwind {
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
; MIPS32-AE: .size const_v4i32
} }
define void @const_v2i64() nounwind { define void @const_v2i64() nounwind {
; MIPS32-AE-LABEL: const_v2i64: ; MIPS32-AE-LABEL: const_v2i64:
store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64 store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0 ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
Show All 13 Linesdefine void @const_v2i64() nounwind {
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64 store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
; MIPS32-AE: .size const_v2i64
} }
define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind { define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
; MIPS32-AE-LABEL: nonconst_v16i8: ; MIPS32-AE-LABEL: nonconst_v16i8:
%1 = insertelement <16 x i8> undef, i8 %a, i32 0 %1 = insertelement <16 x i8> undef, i8 %a, i32 0
%2 = insertelement <16 x i8> %1, i8 %b, i32 1 %2 = insertelement <16 x i8> %1, i8 %b, i32 1
%3 = insertelement <16 x i8> %2, i8 %c, i32 2 %3 = insertelement <16 x i8> %2, i8 %c, i32 2
Show All 29 Linesdefine void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
; MIPS32-AE-DAG: insert.b [[R1]][12], [[R5]] ; MIPS32-AE-DAG: insert.b [[R1]][12], [[R5]]
; MIPS32-AE-DAG: insert.b [[R1]][13], [[R5]] ; MIPS32-AE-DAG: insert.b [[R1]][13], [[R5]]
; MIPS32-AE-DAG: insert.b [[R1]][14], [[R5]] ; MIPS32-AE-DAG: insert.b [[R1]][14], [[R5]]
; MIPS32-AE-DAG: insert.b [[R1]][15], [[R5]] ; MIPS32-AE-DAG: insert.b [[R1]][15], [[R5]]
store volatile <16 x i8> %16, <16 x i8>*@v16i8 store volatile <16 x i8> %16, <16 x i8>*@v16i8
ret void ret void
; MIPS32-AE: .size nonconst_v16i8
} }
define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind { define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind {
; MIPS32-AE-LABEL: nonconst_v8i16: ; MIPS32-AE-LABEL: nonconst_v8i16:
%1 = insertelement <8 x i16> undef, i16 %a, i32 0 %1 = insertelement <8 x i16> undef, i16 %a, i32 0
%2 = insertelement <8 x i16> %1, i16 %b, i32 1 %2 = insertelement <8 x i16> %1, i16 %b, i32 1
%3 = insertelement <8 x i16> %2, i16 %c, i32 2 %3 = insertelement <8 x i16> %2, i16 %c, i32 2
Show All 13 Linesdefine void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind {
; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 24($sp) ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 24($sp)
; MIPS32-AE-DAG: insert.h [[R1]][6], [[R2]] ; MIPS32-AE-DAG: insert.h [[R1]][6], [[R2]]
; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 28($sp) ; MIPS32-AE-DAG: lw [[R2:\$[0-9]+]], 28($sp)
; MIPS32-AE-DAG: insert.h [[R1]][7], [[R2]] ; MIPS32-AE-DAG: insert.h [[R1]][7], [[R2]]
store volatile <8 x i16> %8, <8 x i16>*@v8i16 store volatile <8 x i16> %8, <8 x i16>*@v8i16
ret void ret void
; MIPS32-AE: .size nonconst_v8i16
} }
define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; MIPS32-AE-LABEL: nonconst_v4i32: ; MIPS32-AE-LABEL: nonconst_v4i32:
%1 = insertelement <4 x i32> undef, i32 %a, i32 0 %1 = insertelement <4 x i32> undef, i32 %a, i32 0
%2 = insertelement <4 x i32> %1, i32 %b, i32 1 %2 = insertelement <4 x i32> %1, i32 %b, i32 1
%3 = insertelement <4 x i32> %2, i32 %c, i32 2 %3 = insertelement <4 x i32> %2, i32 %c, i32 2
%4 = insertelement <4 x i32> %3, i32 %d, i32 3 %4 = insertelement <4 x i32> %3, i32 %d, i32 3
; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4 ; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4
; MIPS32-AE: insert.w [[R1]][1], $5 ; MIPS32-AE: insert.w [[R1]][1], $5
; MIPS32-AE: insert.w [[R1]][2], $6 ; MIPS32-AE: insert.w [[R1]][2], $6
; MIPS32-AE: insert.w [[R1]][3], $7 ; MIPS32-AE: insert.w [[R1]][3], $7
store volatile <4 x i32> %4, <4 x i32>*@v4i32 store volatile <4 x i32> %4, <4 x i32>*@v4i32
ret void ret void
; MIPS32-AE: .size nonconst_v4i32
} }
define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind { define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind {
; MIPS32-AE-LABEL: nonconst_v2i64: ; MIPS32-AE-LABEL: nonconst_v2i64:
%1 = insertelement <2 x i64> undef, i64 %a, i32 0 %1 = insertelement <2 x i64> undef, i64 %a, i32 0
%2 = insertelement <2 x i64> %1, i64 %b, i32 1 %2 = insertelement <2 x i64> %1, i64 %b, i32 1
; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4 ; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4
; MIPS32-AE: insert.w [[R1]][1], $5 ; MIPS32-AE: insert.w [[R1]][1], $5
; MIPS32-AE: insert.w [[R1]][2], $6 ; MIPS32-AE: insert.w [[R1]][2], $6
; MIPS32-AE: insert.w [[R1]][3], $7 ; MIPS32-AE: insert.w [[R1]][3], $7
store volatile <2 x i64> %2, <2 x i64>*@v2i64 store volatile <2 x i64> %2, <2 x i64>*@v2i64
ret void ret void
; MIPS32-AE: .size nonconst_v2i64
} }
define i32 @extract_sext_v16i8() nounwind { define i32 @extract_sext_v16i8() nounwind {
; MIPS32-AE-LABEL: extract_sext_v16i8: ; MIPS32-AE-LABEL: extract_sext_v16i8:
%1 = load <16 x i8>, <16 x i8>* @v16i8 %1 = load <16 x i8>, <16 x i8>* @v16i8
; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
%2 = add <16 x i8> %1, %1 %2 = add <16 x i8> %1, %1
; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <16 x i8> %2, i32 1 %3 = extractelement <16 x i8> %2, i32 1
%4 = sext i8 %3 to i32 %4 = sext i8 %3 to i32
; MIPS32-AE-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1] ; MIPS32-AE-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
; MIPS32-AE-NOT: sll ; MIPS32-AE-NOT: sll
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
ret i32 %4 ret i32 %4
; MIPS32-AE: .size extract_sext_v16i8
} }
define i32 @extract_sext_v8i16() nounwind { define i32 @extract_sext_v8i16() nounwind {
; MIPS32-AE-LABEL: extract_sext_v8i16: ; MIPS32-AE-LABEL: extract_sext_v8i16:
%1 = load <8 x i16>, <8 x i16>* @v8i16 %1 = load <8 x i16>, <8 x i16>* @v8i16
; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
%2 = add <8 x i16> %1, %1 %2 = add <8 x i16> %1, %1
; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <8 x i16> %2, i32 1 %3 = extractelement <8 x i16> %2, i32 1
%4 = sext i16 %3 to i32 %4 = sext i16 %3 to i32
; MIPS32-AE-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1] ; MIPS32-AE-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
; MIPS32-AE-NOT: sll ; MIPS32-AE-NOT: sll
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
ret i32 %4 ret i32 %4
; MIPS32-AE: .size extract_sext_v8i16
} }
define i32 @extract_sext_v4i32() nounwind { define i32 @extract_sext_v4i32() nounwind {
; MIPS32-AE-LABEL: extract_sext_v4i32: ; MIPS32-AE-LABEL: extract_sext_v4i32:
%1 = load <4 x i32>, <4 x i32>* @v4i32 %1 = load <4 x i32>, <4 x i32>* @v4i32
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = add <4 x i32> %1, %1 %2 = add <4 x i32> %1, %1
; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x i32> %2, i32 1 %3 = extractelement <4 x i32> %2, i32 1
; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1] ; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1]
ret i32 %3 ret i32 %3
; MIPS32-AE: .size extract_sext_v4i32
} }
define i64 @extract_sext_v2i64() nounwind { define i64 @extract_sext_v2i64() nounwind {
; MIPS32-AE-LABEL: extract_sext_v2i64: ; MIPS32-AE-LABEL: extract_sext_v2i64:
%1 = load <2 x i64>, <2 x i64>* @v2i64 %1 = load <2 x i64>, <2 x i64>* @v2i64
; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = add <2 x i64> %1, %1 %2 = add <2 x i64> %1, %1
; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <2 x i64> %2, i32 1 %3 = extractelement <2 x i64> %2, i32 1
; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2] ; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
; MIPS32-AE-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3] ; MIPS32-AE-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
; MIPS32-AE-NOT: sll ; MIPS32-AE-NOT: sll
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
ret i64 %3 ret i64 %3
; MIPS32-AE: .size extract_sext_v2i64
} }
define i32 @extract_zext_v16i8() nounwind { define i32 @extract_zext_v16i8() nounwind {
; MIPS32-AE-LABEL: extract_zext_v16i8: ; MIPS32-AE-LABEL: extract_zext_v16i8:
%1 = load <16 x i8>, <16 x i8>* @v16i8 %1 = load <16 x i8>, <16 x i8>* @v16i8
; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
%2 = add <16 x i8> %1, %1 %2 = add <16 x i8> %1, %1
; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <16 x i8> %2, i32 1 %3 = extractelement <16 x i8> %2, i32 1
%4 = zext i8 %3 to i32 %4 = zext i8 %3 to i32
; MIPS32-AE-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1] ; MIPS32-AE-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
ret i32 %4 ret i32 %4
; MIPS32-AE: .size extract_zext_v16i8
} }
define i32 @extract_zext_v8i16() nounwind { define i32 @extract_zext_v8i16() nounwind {
; MIPS32-AE-LABEL: extract_zext_v8i16: ; MIPS32-AE-LABEL: extract_zext_v8i16:
%1 = load <8 x i16>, <8 x i16>* @v8i16 %1 = load <8 x i16>, <8 x i16>* @v8i16
; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
%2 = add <8 x i16> %1, %1 %2 = add <8 x i16> %1, %1
; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <8 x i16> %2, i32 1 %3 = extractelement <8 x i16> %2, i32 1
%4 = zext i16 %3 to i32 %4 = zext i16 %3 to i32
; MIPS32-AE-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1] ; MIPS32-AE-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
ret i32 %4 ret i32 %4
; MIPS32-AE: .size extract_zext_v8i16
} }
define i32 @extract_zext_v4i32() nounwind { define i32 @extract_zext_v4i32() nounwind {
; MIPS32-AE-LABEL: extract_zext_v4i32: ; MIPS32-AE-LABEL: extract_zext_v4i32:
%1 = load <4 x i32>, <4 x i32>* @v4i32 %1 = load <4 x i32>, <4 x i32>* @v4i32
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = add <4 x i32> %1, %1 %2 = add <4 x i32> %1, %1
; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x i32> %2, i32 1 %3 = extractelement <4 x i32> %2, i32 1
; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1] ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1]
ret i32 %3 ret i32 %3
; MIPS32-AE: .size extract_zext_v4i32
} }
define i64 @extract_zext_v2i64() nounwind { define i64 @extract_zext_v2i64() nounwind {
; MIPS32-AE-LABEL: extract_zext_v2i64: ; MIPS32-AE-LABEL: extract_zext_v2i64:
%1 = load <2 x i64>, <2 x i64>* @v2i64 %1 = load <2 x i64>, <2 x i64>* @v2i64
; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = add <2 x i64> %1, %1 %2 = add <2 x i64> %1, %1
; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <2 x i64> %2, i32 1 %3 = extractelement <2 x i64> %2, i32 1
; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2] ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
; MIPS32-AE-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3] ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
ret i64 %3 ret i64 %3
; MIPS32-AE: .size extract_zext_v2i64
} }
define i32 @extract_sext_v16i8_vidx() nounwind { define i32 @extract_sext_v16i8_vidx() nounwind {
; MIPS32-AE-LABEL: extract_sext_v16i8_vidx: ; MIPS32-AE-LABEL: extract_sext_v16i8_vidx:
%1 = load <16 x i8>, <16 x i8>* @v16i8 %1 = load <16 x i8>, <16 x i8>* @v16i8
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <16 x i8> %1, %1 %2 = add <16 x i8> %1, %1
; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <16 x i8> %2, i32 %3 %4 = extractelement <16 x i8> %2, i32 %3
%5 = sext i8 %4 to i32 %5 = sext i8 %4 to i32
; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24 ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
ret i32 %5 ret i32 %5
; MIPS32-AE: .size extract_sext_v16i8_vidx
} }
define i32 @extract_sext_v8i16_vidx() nounwind { define i32 @extract_sext_v8i16_vidx() nounwind {
; MIPS32-AE-LABEL: extract_sext_v8i16_vidx: ; MIPS32-AE-LABEL: extract_sext_v8i16_vidx:
%1 = load <8 x i16>, <8 x i16>* @v8i16 %1 = load <8 x i16>, <8 x i16>* @v8i16
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <8 x i16> %1, %1 %2 = add <8 x i16> %1, %1
; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <8 x i16> %2, i32 %3 %4 = extractelement <8 x i16> %2, i32 %3
%5 = sext i16 %4 to i32 %5 = sext i16 %4 to i32
; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16 ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
ret i32 %5 ret i32 %5
; MIPS32-AE: .size extract_sext_v8i16_vidx
} }
define i32 @extract_sext_v4i32_vidx() nounwind { define i32 @extract_sext_v4i32_vidx() nounwind {
; MIPS32-AE-LABEL: extract_sext_v4i32_vidx: ; MIPS32-AE-LABEL: extract_sext_v4i32_vidx:
%1 = load <4 x i32>, <4 x i32>* @v4i32 %1 = load <4 x i32>, <4 x i32>* @v4i32
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <4 x i32> %1, %1 %2 = add <4 x i32> %1, %1
; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <4 x i32> %2, i32 %3 %4 = extractelement <4 x i32> %2, i32 %3
; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
ret i32 %4 ret i32 %4
; MIPS32-AE: .size extract_sext_v4i32_vidx
} }
define i64 @extract_sext_v2i64_vidx() nounwind { define i64 @extract_sext_v2i64_vidx() nounwind {
; MIPS32-AE-LABEL: extract_sext_v2i64_vidx: ; MIPS32-AE-LABEL: extract_sext_v2i64_vidx:
%1 = load <2 x i64>, <2 x i64>* @v2i64 %1 = load <2 x i64>, <2 x i64>* @v2i64
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <2 x i64> %1, %1 %2 = add <2 x i64> %1, %1
; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <2 x i64> %2, i32 %3 %4 = extractelement <2 x i64> %2, i32 %3
; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
ret i64 %4 ret i64 %4
; MIPS32-AE: .size extract_sext_v2i64_vidx
} }
define i32 @extract_zext_v16i8_vidx() nounwind { define i32 @extract_zext_v16i8_vidx() nounwind {
; MIPS32-AE-LABEL: extract_zext_v16i8_vidx: ; MIPS32-AE-LABEL: extract_zext_v16i8_vidx:
%1 = load <16 x i8>, <16 x i8>* @v16i8 %1 = load <16 x i8>, <16 x i8>* @v16i8
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <16 x i8> %1, %1 %2 = add <16 x i8> %1, %1
; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <16 x i8> %2, i32 %3 %4 = extractelement <16 x i8> %2, i32 %3
%5 = zext i8 %4 to i32 %5 = zext i8 %4 to i32
; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24 ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
ret i32 %5 ret i32 %5
; MIPS32-AE: .size extract_zext_v16i8_vidx
} }
define i32 @extract_zext_v8i16_vidx() nounwind { define i32 @extract_zext_v8i16_vidx() nounwind {
; MIPS32-AE-LABEL: extract_zext_v8i16_vidx: ; MIPS32-AE-LABEL: extract_zext_v8i16_vidx:
%1 = load <8 x i16>, <8 x i16>* @v8i16 %1 = load <8 x i16>, <8 x i16>* @v8i16
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <8 x i16> %1, %1 %2 = add <8 x i16> %1, %1
; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <8 x i16> %2, i32 %3 %4 = extractelement <8 x i16> %2, i32 %3
%5 = zext i16 %4 to i32 %5 = zext i16 %4 to i32
; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16 ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
ret i32 %5 ret i32 %5
; MIPS32-AE: .size extract_zext_v8i16_vidx
} }
define i32 @extract_zext_v4i32_vidx() nounwind { define i32 @extract_zext_v4i32_vidx() nounwind {
; MIPS32-AE-LABEL: extract_zext_v4i32_vidx: ; MIPS32-AE-LABEL: extract_zext_v4i32_vidx:
%1 = load <4 x i32>, <4 x i32>* @v4i32 %1 = load <4 x i32>, <4 x i32>* @v4i32
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <4 x i32> %1, %1 %2 = add <4 x i32> %1, %1
; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <4 x i32> %2, i32 %3 %4 = extractelement <4 x i32> %2, i32 %3
; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-NOT: srl ; MIPS32-AE-NOT: srl
ret i32 %4 ret i32 %4
; MIPS32-AE: .size extract_zext_v4i32_vidx
} }
define i64 @extract_zext_v2i64_vidx() nounwind { define i64 @extract_zext_v2i64_vidx() nounwind {
; MIPS32-AE-LABEL: extract_zext_v2i64_vidx: ; MIPS32-AE-LABEL: extract_zext_v2i64_vidx:
%1 = load <2 x i64>, <2 x i64>* @v2i64 %1 = load <2 x i64>, <2 x i64>* @v2i64
; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = add <2 x i64> %1, %1 %2 = add <2 x i64> %1, %1
; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <2 x i64> %2, i32 %3 %4 = extractelement <2 x i64> %2, i32 %3
; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
; MIPS32-AE-NOT: srl ; MIPS32-AE-NOT: srl
ret i64 %4 ret i64 %4
; MIPS32-AE: .size extract_zext_v2i64_vidx
} }
define void @insert_v16i8(i32 signext %a) nounwind { define void @insert_v16i8(i32 signext %a) nounwind {
; MIPS32-AE-LABEL: insert_v16i8: ; MIPS32-AE-LABEL: insert_v16i8:
%1 = load <16 x i8>, <16 x i8>* @v16i8 %1 = load <16 x i8>, <16 x i8>* @v16i8
; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
%a2 = trunc i32 %a to i8 %a2 = trunc i32 %a to i8
%a3 = sext i8 %a2 to i32 %a3 = sext i8 %a2 to i32
%a4 = trunc i32 %a3 to i8 %a4 = trunc i32 %a3 to i8
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
%2 = insertelement <16 x i8> %1, i8 %a4, i32 1 %2 = insertelement <16 x i8> %1, i8 %a4, i32 1
; MIPS32-AE-DAG: insert.b [[R1]][1], $4 ; MIPS32-AE-DAG: insert.b [[R1]][1], $4
store <16 x i8> %2, <16 x i8>* @v16i8 store <16 x i8> %2, <16 x i8>* @v16i8
; MIPS32-AE-DAG: st.b [[R1]] ; MIPS32-AE-DAG: st.b [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v16i8
} }
define void @insert_v8i16(i32 signext %a) nounwind { define void @insert_v8i16(i32 signext %a) nounwind {
; MIPS32-AE-LABEL: insert_v8i16: ; MIPS32-AE-LABEL: insert_v8i16:
%1 = load <8 x i16>, <8 x i16>* @v8i16 %1 = load <8 x i16>, <8 x i16>* @v8i16
; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
%a2 = trunc i32 %a to i16 %a2 = trunc i32 %a to i16
%a3 = sext i16 %a2 to i32 %a3 = sext i16 %a2 to i32
%a4 = trunc i32 %a3 to i16 %a4 = trunc i32 %a3 to i16
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
%2 = insertelement <8 x i16> %1, i16 %a4, i32 1 %2 = insertelement <8 x i16> %1, i16 %a4, i32 1
; MIPS32-AE-DAG: insert.h [[R1]][1], $4 ; MIPS32-AE-DAG: insert.h [[R1]][1], $4
store <8 x i16> %2, <8 x i16>* @v8i16 store <8 x i16> %2, <8 x i16>* @v8i16
; MIPS32-AE-DAG: st.h [[R1]] ; MIPS32-AE-DAG: st.h [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v8i16
} }
define void @insert_v4i32(i32 signext %a) nounwind { define void @insert_v4i32(i32 signext %a) nounwind {
; MIPS32-AE-LABEL: insert_v4i32: ; MIPS32-AE-LABEL: insert_v4i32:
%1 = load <4 x i32>, <4 x i32>* @v4i32 %1 = load <4 x i32>, <4 x i32>* @v4i32
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
%2 = insertelement <4 x i32> %1, i32 %a, i32 1 %2 = insertelement <4 x i32> %1, i32 %a, i32 1
; MIPS32-AE-DAG: insert.w [[R1]][1], $4 ; MIPS32-AE-DAG: insert.w [[R1]][1], $4
store <4 x i32> %2, <4 x i32>* @v4i32 store <4 x i32> %2, <4 x i32>* @v4i32
; MIPS32-AE-DAG: st.w [[R1]] ; MIPS32-AE-DAG: st.w [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v4i32
} }
define void @insert_v2i64(i64 signext %a) nounwind { define void @insert_v2i64(i64 signext %a) nounwind {
; MIPS32-AE-LABEL: insert_v2i64: ; MIPS32-AE-LABEL: insert_v2i64:
%1 = load <2 x i64>, <2 x i64>* @v2i64 %1 = load <2 x i64>, <2 x i64>* @v2i64
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
%2 = insertelement <2 x i64> %1, i64 %a, i32 1 %2 = insertelement <2 x i64> %1, i64 %a, i32 1
; MIPS32-AE-DAG: insert.w [[R1]][2], $4 ; MIPS32-AE-DAG: insert.w [[R1]][2], $4
; MIPS32-AE-DAG: insert.w [[R1]][3], $5 ; MIPS32-AE-DAG: insert.w [[R1]][3], $5
store <2 x i64> %2, <2 x i64>* @v2i64 store <2 x i64> %2, <2 x i64>* @v2i64
; MIPS32-AE-DAG: st.w [[R1]] ; MIPS32-AE-DAG: st.w [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v2i64
} }
define void @insert_v16i8_vidx(i32 signext %a) nounwind { define void @insert_v16i8_vidx(i32 signext %a) nounwind {
; MIPS32-AE: insert_v16i8_vidx: ; MIPS32-AE-LABEL: insert_v16i8_vidx:
%1 = load <16 x i8>, <16 x i8>* @v16i8 %1 = load <16 x i8>, <16 x i8>* @v16i8
; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
%2 = load i32, i32* @i32 %2 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%a2 = trunc i32 %a to i8 %a2 = trunc i32 %a to i8
%a3 = sext i8 %a2 to i32 %a3 = sext i8 %a2 to i32
%a4 = trunc i32 %a3 to i8 %a4 = trunc i32 %a3 to i8
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
%3 = insertelement <16 x i8> %1, i8 %a4, i32 %2 %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]] ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
; MIPS32-AE-DAG: insert.b [[R1]][0], $4 ; MIPS32-AE-DAG: insert.b [[R1]][0], $4
; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <16 x i8> %3, <16 x i8>* @v16i8 store <16 x i8> %3, <16 x i8>* @v16i8
; MIPS32-AE-DAG: st.b [[R1]] ; MIPS32-AE-DAG: st.b [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v16i8_vidx
} }
define void @insert_v8i16_vidx(i32 signext %a) nounwind { define void @insert_v8i16_vidx(i32 %a) nounwind {
; MIPS32-AE: insert_v8i16_vidx: ; MIPS32-AE-LABEL: insert_v8i16_vidx:
%1 = load <8 x i16>, <8 x i16>* @v8i16 %1 = load <8 x i16>, <8 x i16>* @v8i16
; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
%2 = load i32, i32* @i32 %2 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
Show All 9 Linesdefine void @insert_v8i16_vidx(i32 %a) nounwind {
; MIPS32-AE-DAG: insert.h [[R1]][0], $4 ; MIPS32-AE-DAG: insert.h [[R1]][0], $4
; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <8 x i16> %3, <8 x i16>* @v8i16 store <8 x i16> %3, <8 x i16>* @v8i16
; MIPS32-AE-DAG: st.h [[R1]] ; MIPS32-AE-DAG: st.h [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v8i16_vidx
} }
define void @insert_v4i32_vidx(i32 signext %a) nounwind { define void @insert_v4i32_vidx(i32 signext %a) nounwind {
; MIPS32-AE: insert_v4i32_vidx: ; MIPS32-AE-LABEL: insert_v4i32_vidx:
%1 = load <4 x i32>, <4 x i32>* @v4i32 %1 = load <4 x i32>, <4 x i32>* @v4i32
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = load i32, i32* @i32 %2 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
; MIPS32-AE-NOT: andi ; MIPS32-AE-NOT: andi
; MIPS32-AE-NOT: sra ; MIPS32-AE-NOT: sra
%3 = insertelement <4 x i32> %1, i32 %a, i32 %2 %3 = insertelement <4 x i32> %1, i32 %a, i32 %2
; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
; MIPS32-AE-DAG: insert.w [[R1]][0], $4 ; MIPS32-AE-DAG: insert.w [[R1]][0], $4
; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <4 x i32> %3, <4 x i32>* @v4i32 store <4 x i32> %3, <4 x i32>* @v4i32
; MIPS32-AE-DAG: st.w [[R1]] ; MIPS32-AE-DAG: st.w [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v4i32_vidx
} }
define void @insert_v2i64_vidx(i64 signext %a) nounwind { define void @insert_v2i64_vidx(i64 signext %a) nounwind {
; MIPS32-AE: insert_v2i64_vidx: ; MIPS32-AE-LABEL: insert_v2i64_vidx:
%1 = load <2 x i64>, <2 x i64>* @v2i64 %1 = load <2 x i64>, <2 x i64>* @v2i64
; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = load i32, i32* @i32 %2 = load i32, i32* @i32
; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
Show All 16 Linesdefine void @insert_v2i64_vidx(i64 signext %a) nounwind {
; MIPS32-AE-DAG: insert.w [[R1]][0], $5 ; MIPS32-AE-DAG: insert.w [[R1]][0], $5
; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <2 x i64> %3, <2 x i64>* @v2i64 store <2 x i64> %3, <2 x i64>* @v2i64
; MIPS32-AE-DAG: st.w [[R1]] ; MIPS32-AE-DAG: st.w [[R1]]
ret void ret void
; MIPS32-AE: .size insert_v2i64_vidx
} }
define void @truncstore() nounwind { define void @truncstore() nounwind {
; MIPS32-AE-LABEL: truncstore: ; MIPS32-AE-LABEL: truncstore:
store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8 store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8
; TODO: What code should be emitted? ; TODO: What code should be emitted?
ret void ret void
; MIPS32-AE: .size truncstore
} }

test/CodeGen/Mips/msa/basic_operations_float.ll

Show All 29 Linesdefine void @const_v4f32() nounwind {
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
; MIPS32: .size const_v4f32
} }
define void @const_v2f64() nounwind { define void @const_v2f64() nounwind {
; MIPS32-LABEL: const_v2f64: ; MIPS32-LABEL: const_v2f64:
store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
Show All 17 Linesdefine void @const_v2f64() nounwind {
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
; MIPS32: .size const_v2f64
} }
define void @nonconst_v4f32() nounwind { define void @nonconst_v4f32() nounwind {
; MIPS32-LABEL: nonconst_v4f32: ; MIPS32-LABEL: nonconst_v4f32:
%1 = load float , float *@f32 %1 = load float , float *@f32
%2 = insertelement <4 x float> undef, float %1, i32 0 %2 = insertelement <4 x float> undef, float %1, i32 0
%3 = insertelement <4 x float> %2, float %1, i32 1 %3 = insertelement <4 x float> %2, float %1, i32 1
%4 = insertelement <4 x float> %3, float %1, i32 2 %4 = insertelement <4 x float> %3, float %1, i32 2
%5 = insertelement <4 x float> %4, float %1, i32 3 %5 = insertelement <4 x float> %4, float %1, i32 3
store volatile <4 x float> %5, <4 x float>*@v4f32 store volatile <4 x float> %5, <4 x float>*@v4f32
; MIPS32: lwc1 $f[[R1:[0-9]+]], 0( ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]] ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
ret void ret void
; MIPS32: .size nonconst_v4f32
} }
define void @nonconst_v2f64() nounwind { define void @nonconst_v2f64() nounwind {
; MIPS32-LABEL: nonconst_v2f64: ; MIPS32-LABEL: nonconst_v2f64:
%1 = load double , double *@f64 %1 = load double , double *@f64
%2 = insertelement <2 x double> undef, double %1, i32 0 %2 = insertelement <2 x double> undef, double %1, i32 0
%3 = insertelement <2 x double> %2, double %1, i32 1 %3 = insertelement <2 x double> %2, double %1, i32 1
store volatile <2 x double> %3, <2 x double>*@v2f64 store volatile <2 x double> %3, <2 x double>*@v2f64
; MIPS32: ldc1 $f[[R1:[0-9]+]], 0( ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]] ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
ret void ret void
; MIPS32: .size nonconst_v2f64
} }
define float @extract_v4f32() nounwind { define float @extract_v4f32() nounwind {
; MIPS32-LABEL: extract_v4f32: ; MIPS32-LABEL: extract_v4f32:
%1 = load <4 x float>, <4 x float>* @v4f32 %1 = load <4 x float>, <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1 %2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 1 %3 = extractelement <4 x float> %2, i32 1
; Element 1 can be obtained by splatting it across the vector and extracting ; Element 1 can be obtained by splatting it across the vector and extracting
; $w0:sub_lo ; $w0:sub_lo
; MIPS32-DAG: splati.w $w0, [[R1]][1] ; MIPS32-DAG: splati.w $w0, [[R1]][1]
ret float %3 ret float %3
; MIPS32: .size extract_v4f32
} }
define float @extract_v4f32_elt0() nounwind { define float @extract_v4f32_elt0() nounwind {
; MIPS32-LABEL: extract_v4f32_elt0: ; MIPS32-LABEL: extract_v4f32_elt0:
%1 = load <4 x float>, <4 x float>* @v4f32 %1 = load <4 x float>, <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1 %2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]] ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 0 %3 = extractelement <4 x float> %2, i32 0
; Element 0 can be obtained by extracting $w0:sub_lo ($f0) ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
; MIPS32-NOT: copy_u.w ; MIPS32-NOT: copy_u.w
; MIPS32-NOT: mtc1 ; MIPS32-NOT: mtc1
ret float %3 ret float %3
; MIPS32: .size extract_v4f32_elt0
} }
define float @extract_v4f32_elt2() nounwind { define float @extract_v4f32_elt2() nounwind {
; MIPS32-LABEL: extract_v4f32_elt2: ; MIPS32-LABEL: extract_v4f32_elt2:
%1 = load <4 x float>, <4 x float>* @v4f32 %1 = load <4 x float>, <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1 %2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 2 %3 = extractelement <4 x float> %2, i32 2
; Element 2 can be obtained by splatting it across the vector and extracting ; Element 2 can be obtained by splatting it across the vector and extracting
; $w0:sub_lo ; $w0:sub_lo
; MIPS32-DAG: splati.w $w0, [[R1]][2] ; MIPS32-DAG: splati.w $w0, [[R1]][2]
ret float %3 ret float %3
; MIPS32: .size extract_v4f32_elt2
} }
define float @extract_v4f32_vidx() nounwind { define float @extract_v4f32_vidx() nounwind {
; MIPS32-LABEL: extract_v4f32_vidx: ; MIPS32-LABEL: extract_v4f32_vidx:
%1 = load <4 x float>, <4 x float>* @v4f32 %1 = load <4 x float>, <4 x float>* @v4f32
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = fadd <4 x float> %1, %1 %2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <4 x float> %2, i32 %3 %4 = extractelement <4 x float> %2, i32 %3
; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]] ; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
ret float %4 ret float %4
; MIPS32: .size extract_v4f32_vidx
} }
define double @extract_v2f64() nounwind { define double @extract_v2f64() nounwind {
; MIPS32-LABEL: extract_v2f64: ; MIPS32-LABEL: extract_v2f64:
%1 = load <2 x double>, <2 x double>* @v2f64 %1 = load <2 x double>, <2 x double>* @v2f64
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = fadd <2 x double> %1, %1 %2 = fadd <2 x double> %1, %1
; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <2 x double> %2, i32 1 %3 = extractelement <2 x double> %2, i32 1
; Element 1 can be obtained by splatting it across the vector and extracting ; Element 1 can be obtained by splatting it across the vector and extracting
; $w0:sub_64 ; $w0:sub_64
; MIPS32-DAG: splati.d $w0, [[R1]][1] ; MIPS32-DAG: splati.d $w0, [[R1]][1]
; MIPS32-NOT: copy_u.w ; MIPS32-NOT: copy_u.w
; MIPS32-NOT: mtc1 ; MIPS32-NOT: mtc1
; MIPS32-NOT: mthc1 ; MIPS32-NOT: mthc1
; MIPS32-NOT: sll ; MIPS32-NOT: sll
; MIPS32-NOT: sra ; MIPS32-NOT: sra
ret double %3 ret double %3
; MIPS32: .size extract_v2f64
} }
define double @extract_v2f64_elt0() nounwind { define double @extract_v2f64_elt0() nounwind {
; MIPS32-LABEL: extract_v2f64_elt0: ; MIPS32-LABEL: extract_v2f64_elt0:
%1 = load <2 x double>, <2 x double>* @v2f64 %1 = load <2 x double>, <2 x double>* @v2f64
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = fadd <2 x double> %1, %1 %2 = fadd <2 x double> %1, %1
; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]] ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
%3 = extractelement <2 x double> %2, i32 0 %3 = extractelement <2 x double> %2, i32 0
; Element 0 can be obtained by extracting $w0:sub_64 ($f0) ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
; MIPS32-NOT: copy_u.w ; MIPS32-NOT: copy_u.w
; MIPS32-NOT: mtc1 ; MIPS32-NOT: mtc1
; MIPS32-NOT: mthc1 ; MIPS32-NOT: mthc1
; MIPS32-NOT: sll ; MIPS32-NOT: sll
; MIPS32-NOT: sra ; MIPS32-NOT: sra
ret double %3 ret double %3
; MIPS32: .size extract_v2f64_elt0
} }
define double @extract_v2f64_vidx() nounwind { define double @extract_v2f64_vidx() nounwind {
; MIPS32-LABEL: extract_v2f64_vidx: ; MIPS32-LABEL: extract_v2f64_vidx:
%1 = load <2 x double>, <2 x double>* @v2f64 %1 = load <2 x double>, <2 x double>* @v2f64
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = fadd <2 x double> %1, %1 %2 = fadd <2 x double> %1, %1
; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32, i32* @i32 %3 = load i32, i32* @i32
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <2 x double> %2, i32 %3 %4 = extractelement <2 x double> %2, i32 %3
; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]] ; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
ret double %4 ret double %4
; MIPS32: .size extract_v2f64_vidx
} }
define void @insert_v4f32(float %a) nounwind { define void @insert_v4f32(float %a) nounwind {
; MIPS32-LABEL: insert_v4f32: ; MIPS32-LABEL: insert_v4f32:
%1 = load <4 x float>, <4 x float>* @v4f32 %1 = load <4 x float>, <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = insertelement <4 x float> %1, float %a, i32 1 %2 = insertelement <4 x float> %1, float %a, i32 1
; float argument passed in $f12 ; float argument passed in $f12
; MIPS32-DAG: insve.w [[R1]][1], $w12[0] ; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
store <4 x float> %2, <4 x float>* @v4f32 store <4 x float> %2, <4 x float>* @v4f32
; MIPS32-DAG: st.w [[R1]] ; MIPS32-DAG: st.w [[R1]]
ret void ret void
; MIPS32: .size insert_v4f32
} }
define void @insert_v2f64(double %a) nounwind { define void @insert_v2f64(double %a) nounwind {
; MIPS32-LABEL: insert_v2f64: ; MIPS32-LABEL: insert_v2f64:
%1 = load <2 x double>, <2 x double>* @v2f64 %1 = load <2 x double>, <2 x double>* @v2f64
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = insertelement <2 x double> %1, double %a, i32 1 %2 = insertelement <2 x double> %1, double %a, i32 1
; double argument passed in $f12 ; double argument passed in $f12
; MIPS32-DAG: insve.d [[R1]][1], $w12[0] ; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
store <2 x double> %2, <2 x double>* @v2f64 store <2 x double> %2, <2 x double>* @v2f64
; MIPS32-DAG: st.d [[R1]] ; MIPS32-DAG: st.d [[R1]]
ret void ret void
; MIPS32: .size insert_v2f64
} }
define void @insert_v4f32_vidx(float %a) nounwind { define void @insert_v4f32_vidx(float %a) nounwind {
; MIPS32-LABEL: insert_v4f32_vidx: ; MIPS32-LABEL: insert_v4f32_vidx:
%1 = load <4 x float>, <4 x float>* @v4f32 %1 = load <4 x float>, <4 x float>* @v4f32
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
Show All 9 Linesdefine void @insert_v4f32_vidx(float %a) nounwind {
; MIPS32-DAG: insve.w [[R1]][0], $w12[0] ; MIPS32-DAG: insve.w [[R1]][0], $w12[0]
; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <4 x float> %3, <4 x float>* @v4f32 store <4 x float> %3, <4 x float>* @v4f32
; MIPS32-DAG: st.w [[R1]] ; MIPS32-DAG: st.w [[R1]]
ret void ret void
; MIPS32: .size insert_v4f32_vidx
} }
define void @insert_v2f64_vidx(double %a) nounwind { define void @insert_v2f64_vidx(double %a) nounwind {
; MIPS32-LABEL: insert_v2f64_vidx: ; MIPS32-LABEL: insert_v2f64_vidx:
%1 = load <2 x double>, <2 x double>* @v2f64 %1 = load <2 x double>, <2 x double>* @v2f64
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
Show All 9 Linesdefine void @insert_v2f64_vidx(double %a) nounwind {
; MIPS32-DAG: insve.d [[R1]][0], $w12[0] ; MIPS32-DAG: insve.d [[R1]][0], $w12[0]
; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <2 x double> %3, <2 x double>* @v2f64 store <2 x double> %3, <2 x double>* @v2f64
; MIPS32-DAG: st.d [[R1]] ; MIPS32-DAG: st.d [[R1]]
ret void ret void
; MIPS32: .size insert_v2f64_vidx
} }