Sparc: Add the alternate address space load/store instructions.

[jyknight]

Summary

Sparc: Add the "alternate address space" load/store instructions.

• Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma.

• Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa)

This does not attempt to hook these instructions up to pointer address
spaces in LLVM, although that would probably be a reasonable thing to
do in the future.

[jyknight]

Ping

[echristo]

Some inline comments. Can you elaborate on the patch description as to what you're doing and why here?

Thanks!

-eric

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

635 ↗

(On Diff #23437)

Comments are complete sentences with periods.

lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

308 ↗

(On Diff #23437)

No blocks around single stmt if conditionals.

490 ↗

(On Diff #23437)

Ditto on the single block stmts after conditionals.

lib/Target/Sparc/SparcInstr64Bit.td

488 ↗

(On Diff #23437)

Can you comment on the asi magic value here and why you put it as part of the let stmt?

[jyknight]

Updated per echristo's review comments.

[jyknight]

lib/Target/Sparc/SparcInstr64Bit.td

488 ↗

(On Diff #23437)

That magic value was a "template" parameter to F3_1_asi before, but I wanted it to be a passed-in immediate, from the asm, for the other new uses of F3_1_asi.

[jyknight]

ping

[echristo]

A few comments inline, but at least for assembly this is probably ok. You'll need to add some comments/code generation options to the patterns, but for the first part it's ok. Don't worry about getting a fresh LGTM with the comments, I'll post-commit review those.

-eric

lib/Target/Sparc/SparcInstr64Bit.td

489 ↗

(On Diff #25092)

What I meant in my request is "what's this magic number? Can you add an appropriate comment as to what it is?" Feel free to do that after since you're just moving an existing magic number around.

lib/Target/Sparc/SparcInstrInfo.td

292 ↗

(On Diff #25092)

You probably want a pattern if you expect to match anything during code generation. If you don't plan on adding that now then having a couple of block comments would be good.

llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

if (ResTy != MatchOperand_Success)
       return ResTy;
 
     if (!getLexer().is(AsmToken::RBrac))
       return MatchOperand_ParseFail;
 
     Operands.push_back(SparcOperand::CreateToken("]",
                                                  Parser.getTok().getLoc()));
     Parser.Lex(); // Eat the ]
+
+    // Parse an optional address-space identifier after the address.
+    if (getLexer().is(AsmToken::Integer)) {
+      std::unique_ptr<SparcOperand> Op;
+      ResTy = parseSparcAsmOperand(Op, false);
+      if (ResTy != MatchOperand_Success || !Op)
+        return MatchOperand_ParseFail;
+      Operands.push_back(std::move(Op));
+    }
     return MatchOperand_Success;
   }
 
   std::unique_ptr<SparcOperand> Op;
 
   ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
   if (ResTy != MatchOperand_Success || !Op)
     return MatchOperand_ParseFail;

llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
                                    const void *Decoder);
 
 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
                               const void *Decoder,
                               bool isLoad, DecodeFunc DecodeRD) {
   unsigned rd = fieldFromInstruction(insn, 25, 5);
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   bool isImm = fieldFromInstruction(insn, 13, 1);
+  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
+  unsigned asi = fieldFromInstruction(insn, 5, 8);
   unsigned rs2 = 0;
   unsigned simm13 = 0;
   if (isImm)
     simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
   else
     rs2 = fieldFromInstruction(insn, 0, 5);
 
   DecodeStatus status;
static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
   if (isImm)
     MI.addOperand(MCOperand::createImm(simm13));
   else {
     status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
 
+  if (hasAsi)
+    MI.addOperand(MCOperand::createImm(asi));
+
   if (!isLoad) {
     status = DecodeRD(MI, rd, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 

 }
 
 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
                                const void *Decoder) {
 
   unsigned rd = fieldFromInstruction(insn, 25, 5);
   unsigned rs1 = fieldFromInstruction(insn, 14, 5);
   unsigned isImm = fieldFromInstruction(insn, 13, 1);
+  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
+  unsigned asi = fieldFromInstruction(insn, 5, 8);
   unsigned rs2 = 0;
   unsigned simm13 = 0;
   if (isImm)
     simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
   else
     rs2 = fieldFromInstruction(insn, 0, 5);
 
   // Decode RD.
static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
   // Decode RS1 | SIMM13.
   if (isImm)
     MI.addOperand(MCOperand::createImm(simm13));
   else {
     status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
+
+  if (hasAsi)
+    MI.addOperand(MCOperand::createImm(asi));
+
   return MCDisassembler::Success;
 }

llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td

 let Predicates = [Is64Bit], isCodeGenOnly = 1 in {
 def SETHIXi : F2_1<0b100,
                    (outs IntRegs:$rd), (ins i64imm:$imm22),
                    "sethi $imm22, $rd",
                    [(set i64:$rd, SETHIimm:$imm22)]>;
 }
 
 // ATOMICS.
-let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
-  def CASXrr: F3_1_asi<3, 0b111110, 0b10000000,
+let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
+  def CASXrr: F3_1_asi<3, 0b111110,
                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
                                      I64Regs:$swap),
                  "casx [$rs1], $rs2, $rd",
                  [(set i64:$rd,
                      (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
 
 } // Predicates = [Is64Bit], Constraints = ...
 

llvm/trunk/lib/Target/Sparc/SparcInstrFormats.td

class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
   let op{1} = 1;   // Op = 2 or 3
   let Inst{29-25} = rd;
   let Inst{24-19} = op3;
   let Inst{18-14} = rs1;
 }
 
 // Specific F3 classes: SparcV8 manual, page 44
 //
-class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
+class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+  bits<8> asi;
   bits<5> rs2;
 
   let op         = opVal;
   let op3        = op3val;
 
   let Inst{13}   = 0;     // i field = 0
   let Inst{12-5} = asi;   // address space identifier
   let Inst{4-0}  = rs2;
 }
 
 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
-       list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
-                                                     asmstr, pattern>;
+       list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins,
+                                                     asmstr, pattern> {
+  let asi = 0;
+}
 
 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
   bits<13> simm13;
 
   let op         = opVal;
   let op3        = op3val;
 

llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td

def rr  : F3_1<3, Op3Val,
                  !strconcat(OpcStr, " [$addr], $dst"),
                  [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
   def ri  : F3_2<3, Op3Val,
                  (outs RC:$dst), (ins MEMri:$addr),
                  !strconcat(OpcStr, " [$addr], $dst"),
                  [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
 }
 
+// LoadA multiclass - As above, but also define alternate address space variant
+multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
+                 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
+             Load<OpcStr, Op3Val, OpNode, RC, Ty> {
+  // TODO: The LD*Arr instructions are currently asm only; hooking up
+  // CodeGen's address spaces to use these is a future task.
+  def Arr  : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
+                !strconcat(OpcStr, "a [$addr] $asi, $dst"),
+                []>;
+}
+
 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
            RegisterClass RC, ValueType Ty> {
   def rr  : F3_1<3, Op3Val,
                  (outs), (ins MEMrr:$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRrr:$addr)]>;
   def ri  : F3_2<3, Op3Val,
                  (outs), (ins MEMri:$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRri:$addr)]>;
 }
 
+multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
+                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
+             Store<OpcStr, Op3Val, OpNode, RC, Ty> {
+  // TODO: The ST*Arr instructions are currently asm only; hooking up
+  // CodeGen's address spaces to use these is a future task.
+  def Arr  : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
+                  !strconcat(OpcStr, "a $rd, [$addr] $asi"),
+                  []>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 // Pseudo instructions.
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
    : InstSP<outs, ins, asmstr, pattern> {
   let isCodeGenOnly = 1;
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
   def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
                        "rett $addr", []>;
   def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
                        "rett $addr", []>;
 }
 
 // Section B.1 - Load Integer Instructions, p. 90
 let DecoderMethod = "DecodeLoadInt" in {
-  defm LDSB : Load<"ldsb", 0b001001, sextloadi8,  IntRegs, i32>;
-  defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
-  defm LDUB : Load<"ldub", 0b000001, zextloadi8,  IntRegs, i32>;
-  defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
-  defm LD   : Load<"ld",   0b000000, load,        IntRegs, i32>;
+  defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
+  defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
+  defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
+  defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
+  defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
 }
 
 // Section B.2 - Load Floating-point Instructions, p. 92
 let DecoderMethod = "DecodeLoadFP" in
   defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
 let DecoderMethod = "DecodeLoadDFP" in
   defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
 let DecoderMethod = "DecodeLoadQFP" in
   defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
                Requires<[HasV9, HasHardQuad]>;
 
 // Section B.4 - Store Integer Instructions, p. 95
 let DecoderMethod = "DecodeStoreInt" in {
-  defm STB   : Store<"stb", 0b000101, truncstorei8,  IntRegs, i32>;
-  defm STH   : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
-  defm ST    : Store<"st",  0b000100, store,         IntRegs, i32>;
+  defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
+  defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
+  defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
 }
 
 // Section B.5 - Store Floating-point Instructions, p. 97
 let DecoderMethod = "DecodeStoreFP" in
   defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
 let DecoderMethod = "DecodeStoreDFP" in
   defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
 let DecoderMethod = "DecodeStoreQFP" in
let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
   def SWAPrr : F3_1<3, 0b001111,
                  (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
                  "swap [$addr], $dst",
                  [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
   def SWAPri : F3_2<3, 0b001111,
                  (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
                  "swap [$addr], $dst",
                  [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
+  def SWAPArr : F3_1_asi<3, 0b011111,
+                 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
+                 "swapa [$addr] $asi, $dst",
+                 [/*FIXME: pattern?*/]>;
 }
 
-let Predicates = [HasV9], Constraints = "$swap = $rd" in
-  def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
+// TODO: Should add a CASArr variant. In fact, the CAS instruction,
+// unlike other instructions, only comes in a form which requires an
+// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
+// default unprivileged ASI for SparcV9.  (Also of note: some modern
+// SparcV8 implementations provide CASA as an extension, but require
+// the use of SparcV8's default ASI, 0xA ("User Data") instead.)
+let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
+  def CASrr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap),
                  "cas [$rs1], $rs2, $rd",
                  [(set i32:$rd,
                      (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
 
 let Defs = [ICC] in {
 defm TADDCC   : F3_12np<"taddcc",   0b100000>;

llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt

 # CHECK:     swap [%i0+32], %o2
 0xd4 0x7e 0x20 0x20
 
 # CHECK:     swap [%g1], %o2
 0xd4 0x78 0x60 0x00
 
 # CHECK:     swap [%g1], %o2
 0xd4 0x78 0x40 0x00
+
+# CHECK:     swapa [%i0+%l6] 131, %o2
+0xd4 0xfe 0x10 0x76
+
+# CHECK:     swapa [%g1] 131, %o2
+0xd4 0xf8 0x50 0x60

llvm/trunk/test/MC/Sparc/sparc-atomic-instructions.s

 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
-
-        ! CHECK: membar 15             ! encoding: [0x81,0x43,0xe0,0x0f]
-        membar 15
+! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
 
         ! CHECK: stbar                 ! encoding: [0x81,0x43,0xc0,0x00]
         stbar
 
         ! CHECK: swap [%i0+%l6], %o2   ! encoding: [0xd4,0x7e,0x00,0x16]
         swap [%i0+%l6], %o2
 
         ! CHECK: swap [%i0+32], %o2    ! encoding: [0xd4,0x7e,0x20,0x20]
         swap [%i0+32], %o2
 
-        ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
-        cas [%i0], %l6, %o2
-
-        ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
-        casx [%i0], %l6, %o2
+        ! CHECK: swapa [%i0+%l6] 131, %o2   ! encoding: [0xd4,0xfe,0x10,0x76]
+        swapa [%i0+%l6] 131, %o2

llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s

 ! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 
         ! CHECK: ldsb [%i0+%l6], %o2  ! encoding: [0xd4,0x4e,0x00,0x16]
         ldsb [%i0 + %l6], %o2
         ! CHECK: ldsb [%i0+32], %o2   ! encoding: [0xd4,0x4e,0x20,0x20]
         ldsb [%i0 + 32], %o2
         ! CHECK: ldsb [%g1], %o4      ! encoding: [0xd8,0x48,0x40,0x00]
         ldsb [%g1], %o4
+        ! CHECK: ldsba [%i0+%l6] 131, %o2  ! encoding: [0xd4,0xce,0x10,0x76]
+        ldsba [%i0 + %l6] 131, %o2
 
         ! CHECK: ldsh [%i0+%l6], %o2  ! encoding: [0xd4,0x56,0x00,0x16]
         ldsh [%i0 + %l6], %o2
         ! CHECK: ldsh [%i0+32], %o2   ! encoding: [0xd4,0x56,0x20,0x20]
         ldsh [%i0 + 32], %o2
         ! CHECK: ldsh [%g1], %o4      ! encoding: [0xd8,0x50,0x40,0x00]
         ldsh [%g1], %o4
+        ! CHECK: ldsha [%i0+%l6] 131, %o2 ! encoding: [0xd4,0xd6,0x10,0x76]
+        ldsha [%i0 + %l6] 131, %o2
 
         ! CHECK: ldub [%i0+%l6], %o2  ! encoding: [0xd4,0x0e,0x00,0x16]
         ldub [%i0 + %l6], %o2
         ! CHECK: ldub [%i0+32], %o2   ! encoding: [0xd4,0x0e,0x20,0x20]
         ldub [%i0 + 32], %o2
         ! CHECK: ldub [%g1], %o2      ! encoding: [0xd4,0x08,0x40,0x00]
         ldub [%g1], %o2
+        ! CHECK: lduba [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x8e,0x10,0x76]
+        lduba [%i0 + %l6] 131, %o2
 
         ! CHECK: lduh [%i0+%l6], %o2  ! encoding: [0xd4,0x16,0x00,0x16]
         lduh [%i0 + %l6], %o2
         ! CHECK: lduh [%i0+32], %o2   ! encoding: [0xd4,0x16,0x20,0x20]
         lduh [%i0 + 32], %o2
         ! CHECK: lduh [%g1], %o2      ! encoding: [0xd4,0x10,0x40,0x00]
         lduh [%g1], %o2
+        ! CHECK: lduha [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x96,0x10,0x76]
+        lduha [%i0 + %l6] 131, %o2
 
         ! CHECK: ld [%i0+%l6], %o2    ! encoding: [0xd4,0x06,0x00,0x16]
         ld [%i0 + %l6], %o2
         ! CHECK: ld [%i0+32], %o2     ! encoding: [0xd4,0x06,0x20,0x20]
         ld [%i0 + 32], %o2
         ! CHECK: ld [%g1], %o2        ! encoding: [0xd4,0x00,0x40,0x00]
         ld [%g1], %o2
+        ! CHECK: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
+        lda [%i0 + %l6] 131, %o2
 
         ! CHECK: stb %o2, [%i0+%l6]   ! encoding: [0xd4,0x2e,0x00,0x16]
         stb %o2, [%i0 + %l6]
         ! CHECK: stb %o2, [%i0+32]    ! encoding: [0xd4,0x2e,0x20,0x20]
         stb %o2, [%i0 + 32]
         ! CHECK: stb %o2, [%g1]       ! encoding: [0xd4,0x28,0x40,0x00]
         stb %o2, [%g1]
+        ! CHECK: stba %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xae,0x10,0x76]
+        stba %o2, [%i0 + %l6] 131
 
         ! CHECK: sth %o2, [%i0+%l6]   ! encoding: [0xd4,0x36,0x00,0x16]
         sth %o2, [%i0 + %l6]
         ! CHECK: sth %o2, [%i0+32]    ! encoding: [0xd4,0x36,0x20,0x20]
         sth %o2, [%i0 + 32]
         ! CHECK: sth %o2, [%g1]       ! encoding: [0xd4,0x30,0x40,0x00]
         sth %o2, [%g1]
+        ! CHECK: stha %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xb6,0x10,0x76]
+        stha %o2, [%i0 + %l6] 131
 
         ! CHECK: st %o2, [%i0+%l6]    ! encoding: [0xd4,0x26,0x00,0x16]
         st %o2, [%i0 + %l6]
         ! CHECK: st %o2, [%i0+32]     ! encoding: [0xd4,0x26,0x20,0x20]
         st %o2, [%i0 + 32]
         ! CHECK: st %o2, [%g1]        ! encoding: [0xd4,0x20,0x40,0x00]
         st %o2, [%g1]
+        ! CHECK: sta %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xa6,0x10,0x76]
+        sta %o2, [%i0 + %l6] 131

llvm/trunk/test/MC/Sparc/sparcv9-atomic-instructions.s

+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+
+        ! CHECK: membar 15             ! encoding: [0x81,0x43,0xe0,0x0f]
+        membar 15
+
+        ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+        cas [%i0], %l6, %o2
+
+        ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
+        casx [%i0], %l6, %o2