[AMDGPU] Add patterns for mad/mac legacy f32 instructions

[foad]

Summary

Note that all subtargets up to GFX10.1 have v_mad_legacy_f32, but GFX8/9
lack v_mac_legacy_f32. GFX10.3 has no mad/mac f32 instructions at all.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstructions.td

887–888

But these do have modifiers?

[foad]

llvm/lib/Target/AMDGPU/SIInstructions.td

887–888

Sure, but that's covered by the TODO at line 869. I could repeat the comment here. I assume there was some reason it wasn't totally straightforward (maybe something to do with the tied operands?) else it would've been done already.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstructions.td

887–888

I think it is straightforward, and just n/nobody bothered to do it

[foad]

llvm/lib/Target/AMDGPU/SIInstructions.td

887–888

Having looked into this some more, I think there is no point selecting v_mac with modifiers, because that would force VOP3 encoding, at which point there is no downside to using v_mad instead:

• it's always available (there are subtargets with only v_mad but none with only v_mac)
• it's no bigger
• it lets you use different registers for dst and src2
• it lets you ave modifiers on all three inputs

If this sounds reasonable I'll update the comments but leave the implementation as-is.

[foad]

Update comments for NoMods patterns.

[foad]

Fix a couple more problems shown up by running the MC tests:

• Update asm/dis special cases for V_MAC_LEGACY_F32 now that it uses the VOP_MAC_F32 profile.
• Fix use of OtherPredicates in VOP2 pseudos.

[foad]

I'll rebase this after D89000 lands, since it touches some of the same code in VOP2Instructions.td and gfx1030_err.s.

[foad]

Rebase after D89000.

[nhaehnle]

Looks reasonable to me.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
 
   // Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):
   // it has src2 register operand that is tied to dst operand
   // we don't allow modifiers for this operand in assembler so src2_modifiers
   // should be 0.
   if (Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
       Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
       Opc == AMDGPU::V_MAC_F32_e64_vi ||
+      Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
+      Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
       Opc == AMDGPU::V_MAC_F16_e64_vi ||
       Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
       Opc == AMDGPU::V_FMAC_F32_e64_vi ||
       Opc == AMDGPU::V_FMAC_F16_e64_gfx10) {
     auto it = Inst.begin();
     std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));
     it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2
     ++it;

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

do {
     if (Res) break;
 
     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
   } while (false);
 
   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
+              MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
+              MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
     // Insert dummy unused src2_modifiers.
     insertNamedMCOperand(MI, MCOperand::createImm(0),
                          AMDGPU::OpName::src2_modifiers);
   }

llvm/lib/Target/AMDGPU/SIInstructions.td

def : GCNPat <
   (f16 (uint_to_fp i32:$src)),
   (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 VSrc_b32:$src))
 >;
 
 //===----------------------------------------------------------------------===//
 // VOP2 Patterns
 //===----------------------------------------------------------------------===//
 
-// TODO: Check only no src2 mods?
+// NoMods pattern used for mac. If there are any source modifiers then it's
+// better to select mad instead of mac.
 class FMADPat <ValueType vt, Instruction inst, SDPatternOperator node>
   : GCNPat <(vt (node (vt (VOP3NoMods vt:$src0)),
                       (vt (VOP3NoMods vt:$src1)),
                       (vt (VOP3NoMods vt:$src2)))),
     (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
           SRCMODS.NONE, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
 >;
 
-
 // Prefer mac form when there are no modifiers.
 let AddedComplexity = 9 in {
+let OtherPredicates = [HasMadMacF32Insts] in {
 def : FMADPat <f32, V_MAC_F32_e64, fmad>;
 def : FMADPat <f32, V_MAC_F32_e64, AMDGPUfmad_ftz>;
 
+// Don't allow source modifiers. If there are any source modifiers then it's
+// better to select mad instead of mac.
+let SubtargetPredicate = isGFX6GFX7GFX10 in
+def : GCNPat <
+      (f32 (fadd (AMDGPUfmul_legacy (VOP3NoMods f32:$src0),
+                                    (VOP3NoMods f32:$src1)),
+                 (VOP3NoMods f32:$src2))),
+      (V_MAC_LEGACY_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
+                            SRCMODS.NONE, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
+>;
+} // OtherPredicates = [HasMadMacF32Insts]
+
 let SubtargetPredicate = Has16BitInsts in {
 def : FMADPat <f16, V_MAC_F16_e64, fmad>;
 def : FMADPat <f16, V_MAC_F16_e64, AMDGPUfmad_ftz>;
-}
-
-}
+} // SubtargetPredicate = Has16BitInsts
+} // AddedComplexity = 9
 
 class FMADModsPat<ValueType Ty, Instruction inst, SDPatternOperator mad_opr>
   : GCNPat<
   (Ty (mad_opr (Ty (VOP3Mods Ty:$src0, i32:$src0_mod)),
                (Ty (VOP3Mods Ty:$src1, i32:$src1_mod)),
                (Ty (VOP3Mods Ty:$src2, i32:$src2_mod)))),
   (inst $src0_mod, $src0, $src1_mod, $src1,
   $src2_mod, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
 >;
 
-let SubtargetPredicate = HasMadMacF32Insts in
+let OtherPredicates = [HasMadMacF32Insts] in {
 def : FMADModsPat<f32, V_MAD_F32, AMDGPUfmad_ftz>;
-def : FMADModsPat<f16, V_MAD_F16, AMDGPUfmad_ftz> {
-  let SubtargetPredicate = Has16BitInsts;
-}
+
+def : GCNPat <
+      (f32 (fadd (AMDGPUfmul_legacy (VOP3Mods f32:$src0, i32:$src0_mod),
+                                    (VOP3Mods f32:$src1, i32:$src1_mod)),
+                 (VOP3Mods f32:$src2, i32:$src2_mod))),
+      (V_MAD_LEGACY_F32 $src0_mod, $src0, $src1_mod, $src1,
+                        $src2_mod, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
+>;
+} // OtherPredicates = [HasMadMacF32Insts]
+
+let SubtargetPredicate = Has16BitInsts in
+def : FMADModsPat<f16, V_MAD_F16, AMDGPUfmad_ftz>;
 
 class VOPSelectModsPat <ValueType vt> : GCNPat <
   (vt (select i1:$src0, (VOP3Mods vt:$src1, i32:$src1_mods),
                         (VOP3Mods vt:$src2, i32:$src2_mods))),
   (V_CNDMASK_B32_e64 FP32InputMods:$src2_mods, VSrc_b32:$src2,
                      FP32InputMods:$src1_mods, VSrc_b32:$src1, SSrc_i1:$src0)
 >;
 

llvm/lib/Target/AMDGPU/VOP2Instructions.td

 defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
 defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
 
 let mayRaiseFPException = 0 in {
 let OtherPredicates = [HasMadMacF32Insts] in {
 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
     isConvertibleToThreeAddress = 1 in {
 defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
-}
+
+let SubtargetPredicate = isGFX6GFX7GFX10 in
+defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_F32>;
+} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
+  //     isConvertibleToThreeAddress = 1
 
 def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
 } // End OtherPredicates = [HasMadMacF32Insts]
-}
+} // End mayRaiseFPException = 0
 
 // No patterns so that the scalar instructions are always selected.
 // The scalar versions will be replaced with vector when needed later.
 defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
 defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
 defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
 defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
 defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;

 
 
 let SubtargetPredicate = isGFX6GFX7 in {
 defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
 defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
 } // End SubtargetPredicate = isGFX6GFX7
 
 let isCommutable = 1 in {
-let SubtargetPredicate = isGFX6GFX7GFX10 in {
-let OtherPredicates = [HasMadMacF32Insts] in
-defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
-} // End SubtargetPredicate = isGFX6GFX7GFX10
 let SubtargetPredicate = isGFX6GFX7 in {
 defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
 defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
 defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
 } // End SubtargetPredicate = isGFX6GFX7
 } // End isCommutable = 1
 
 
let SubtargetPredicate = isGFX6GFX7 in {
   def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
   def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
   def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
 } // End SubtargetPredicate = isGFX6GFX7
 
 defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
 defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
 defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
-let OtherPredicates = [HasMadMacF32Insts] in
 defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
 defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
 defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
 defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
 defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
 defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
 defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
 defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=tonga   -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX101 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX103 %s
 
 define float @v_mul_legacy_f32(float %a, float %b) {
-; GCN-LABEL: v_mul_legacy_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   ret float %result
 }
 
 define float @v_mul_legacy_undef0_f32(float %a) {
-; GCN-LABEL: v_mul_legacy_undef0_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_undef0_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_undef0_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_undef0_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_undef0_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_undef0_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a)
   ret float %result
 }
 
 define float @v_mul_legacy_undef1_f32(float %a) {
-; GCN-LABEL: v_mul_legacy_undef1_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_undef1_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_undef1_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_undef1_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_undef1_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_undef1_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, s4, v0
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef)
   ret float %result
 }
 
 define float @v_mul_legacy_undef_f32() {
-; GCN-LABEL: v_mul_legacy_undef_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e64 v0, s4, s4
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_undef_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e64 v0, s4, s4
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_undef_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e64 v0, s4, s4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_undef_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e64 v0, s4, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_undef_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e64 v0, s4, s4
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_undef_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e64 v0, s4, s4
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float undef, float undef)
   ret float %result
 }
 
 define float @v_mul_legacy_fabs_f32(float %a, float %b) {
-; GCN-LABEL: v_mul_legacy_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e64 v0, |v0|, |v1|
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_fabs_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e64 v0, |v0|, |v1|
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_fabs_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e64 v0, |v0|, |v1|
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_fabs_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e64 v0, |v0|, |v1|
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_fabs_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e64 v0, |v0|, |v1|
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_fabs_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e64 v0, |v0|, |v1|
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %a.fabs = call float @llvm.fabs.f32(float %a)
   %b.fabs = call float @llvm.fabs.f32(float %b)
   %result = call float @llvm.amdgcn.fmul.legacy(float %a.fabs, float %b.fabs)
   ret float %result
 }
 
 define float @v_mul_legacy_fneg_f32(float %a, float %b) {
-; GCN-LABEL: v_mul_legacy_fneg_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %a.fabs = fneg float %a
-  %b.fabs = fneg float %b
-  %result = call float @llvm.amdgcn.fmul.legacy(float %a.fabs, float %b.fabs)
+; GFX6-LABEL: v_mul_legacy_fneg_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_fneg_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_fneg_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_fneg_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_fneg_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
+  %a.fneg = fneg float %a
+  %b.fneg = fneg float %b
+  %result = call float @llvm.amdgcn.fmul.legacy(float %a.fneg, float %b.fneg)
   ret float %result
 }
 
-; TODO: Should match mac_legacy/mad_legacy
 define float @v_mad_legacy_f32(float %a, float %b, float %c) {
-; GCN-LABEL: v_mad_legacy_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
-; GCN-NEXT:    v_add_f32_e32 v0, v0, v2
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mad_legacy_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mac_legacy_f32_e64 v2, v0, v1
+; GFX6-NEXT:    v_mov_b32_e32 v0, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mad_legacy_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mad_legacy_f32 v0, v0, v1, v2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mad_legacy_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mad_legacy_f32 v0, v0, v1, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mad_legacy_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mac_legacy_f32_e64 v2, v0, v1
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    v_mov_b32_e32 v0, v2
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mad_legacy_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    v_add_f32_e32 v0, v0, v2
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   %add = fadd float %mul, %c
   ret float %add
 }
 
+define float @v_mad_legacy_fneg_f32(float %a, float %b, float %c) {
+; GFX6-LABEL: v_mad_legacy_fneg_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mad_legacy_f32 v0, -v0, -v1, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mad_legacy_fneg_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mad_legacy_f32 v0, -v0, -v1, v2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mad_legacy_fneg_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mad_legacy_f32 v0, -v0, -v1, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mad_legacy_fneg_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mad_legacy_f32 v0, -v0, -v1, v2
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mad_legacy_fneg_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e64 v0, -v0, -v1
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    v_add_f32_e32 v0, v0, v2
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
+  %a.fneg = fneg float %a
+  %b.fneg = fneg float %b
+  %mul = call float @llvm.amdgcn.fmul.legacy(float %a.fneg, float %b.fneg)
+  %add = fadd float %mul, %c
+  ret float %add
+}
+
 define amdgpu_ps float @s_mul_legacy_f32(float inreg %a, float inreg %b) {
-; GCN-LABEL: s_mul_legacy_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    v_mov_b32_e32 v0, s1
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
-; GCN-NEXT:    ; return to shader part epilog
+; GFX6-LABEL: s_mul_legacy_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_legacy_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s1
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_legacy_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX101-LABEL: s_mul_legacy_f32:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    v_mul_legacy_f32_e64 v0, s0, s1
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    ; return to shader part epilog
+;
+; GFX103-LABEL: s_mul_legacy_f32:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    v_mul_legacy_f32_e64 v0, s0, s1
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    ; return to shader part epilog
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   ret float %result
 }
 
 define float @v_mul_legacy_f32_1.0(float %a) {
-; GCN-LABEL: v_mul_legacy_f32_1.0:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_f32_1.0:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_f32_1.0:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_f32_1.0:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_f32_1.0:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_f32_1.0:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float 1.0)
   ret float %result
 }
 
 define float @v_mul_legacy_f32_1.0_swap(float %b) {
-; GCN-LABEL: v_mul_legacy_f32_1.0_swap:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_f32_1.0_swap:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_f32_1.0_swap:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_f32_1.0_swap:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_f32_1.0_swap:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_f32_1.0_swap:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, 1.0, v0
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float 1.0, float %b)
   ret float %result
 }
 
 define float @v_mul_legacy_f32_2.0(float %a) {
-; GCN-LABEL: v_mul_legacy_f32_2.0:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_f32_2.0:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_f32_2.0:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_f32_2.0:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_f32_2.0:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_f32_2.0:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float 2.0)
   ret float %result
 }
 
 define float @v_mul_legacy_f32_2.0_swap(float %b) {
-; GCN-LABEL: v_mul_legacy_f32_2.0_swap:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX6-LABEL: v_mul_legacy_f32_2.0_swap:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_legacy_f32_2.0_swap:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_legacy_f32_2.0_swap:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX101-LABEL: v_mul_legacy_f32_2.0_swap:
+; GFX101:       ; %bb.0:
+; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX101-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX101-NEXT:    ; implicit-def: $vcc_hi
+; GFX101-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX103-LABEL: v_mul_legacy_f32_2.0_swap:
+; GFX103:       ; %bb.0:
+; GFX103-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX103-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX103-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
+; GFX103-NEXT:    ; implicit-def: $vcc_hi
+; GFX103-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.amdgcn.fmul.legacy(float 2.0, float %b)
   ret float %result
 }
 
 declare float @llvm.fabs.f32(float) #0
 declare float @llvm.amdgcn.fmul.legacy(float, float) #1
 
 attributes #0 = { nounwind readnone speculatable willreturn }
 attributes #1 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll

-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-
+; RUN: llc -march=amdgcn -mcpu=tahiti  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX6 %s
+; RUN: llc -march=amdgcn -mcpu=tonga   -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX8 %s
+; RUN: llc -march=amdgcn -mcpu=gfx900  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX101 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOMADMACF32,GFX103 %s
 
 ; GCN-LABEL: {{^}}test_mul_legacy_f32:
-; GCN: v_mul_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_mul_legacy_f32(float addrspace(1)* %out, float %a, float %b) #0 {
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_mul_legacy_undef0_f32:
-; GCN: v_mul_legacy_f32_e32
+; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_mul_legacy_undef0_f32(float addrspace(1)* %out, float %a) #0 {
   %result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_mul_legacy_undef1_f32:
-; GCN: v_mul_legacy_f32_e32
+; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_mul_legacy_undef1_f32(float addrspace(1)* %out, float %a) #0 {
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_mul_legacy_fabs_f32:
-; GCN: v_mul_legacy_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|, |v{{[0-9]+}}|
+; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, |s{{[0-9]+}}|, |{{[sv][0-9]+}}|
 define amdgpu_kernel void @test_mul_legacy_fabs_f32(float addrspace(1)* %out, float %a, float %b) #0 {
   %a.fabs = call float @llvm.fabs.f32(float %a)
   %b.fabs = call float @llvm.fabs.f32(float %b)
   %result = call float @llvm.amdgcn.fmul.legacy(float %a.fabs, float %b.fabs)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
-; TODO: Should match mac_legacy/mad_legacy
 ; GCN-LABEL: {{^}}test_mad_legacy_f32:
-; GCN: v_mul_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
-; GCN: v_add_f32_e32
+; GFX6: v_mac_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; GFX8: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; GFX9: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; GFX101: v_mac_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GFX103: v_mul_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+; GFX103: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
 define amdgpu_kernel void @test_mad_legacy_f32(float addrspace(1)* %out, float %a, float %b, float %c) #0 {
   %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   %add = fadd float %mul, %c
   store float %add, float addrspace(1)* %out, align 4
   ret void
 }
 
+; GCN-LABEL: {{^}}test_mad_legacy_fneg_f32:
+; MADMACF32: v_mad_legacy_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -{{[sv][0-9]+}}, v{{[0-9]+}}
+; NOMADMACF32: v_mul_legacy_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}, -s{{[0-9]+}}
+; NOMADMACF32: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @test_mad_legacy_fneg_f32(float addrspace(1)* %out, float %a, float %b, float %c) #0 {
+  %a.fneg = fneg float %a
+  %b.fneg = fneg float %b
+  %mul = call float @llvm.amdgcn.fmul.legacy(float %a.fneg, float %b.fneg)
+  %add = fadd float %mul, %c
+  store float %add, float addrspace(1)* %out, align 4
+  ret void
+}
+
 declare float @llvm.fabs.f32(float) #1
 declare float @llvm.amdgcn.fmul.legacy(float, float) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }