Use movw/movt instead of constant pool loads to lower byval parameter copies

[dschuff]

Summary

The ARM backend can use a loop to implement copying byval parameters before
a call. In non-thumb2 mode it uses a constant pool load to materialize the
trip count. For targets that need movt instead (e.g. Native Client), use
the same code as in thumb2 mode to materialize the trip count.

[jfb]

lgtm, I'd leave open for a short while if a wild @echristo or @t.p.northover appear.

[t.p.northover]

Couple of minor points:

lib/Target/ARM/ARMISelLowering.cpp

7143 ↗

(On Diff #22262)

Couldn't this be simplified to just Subtarget->useMovt(*MF)?

test/CodeGen/ARM/struct_byval.ll

6 ↗

(On Diff #22262)

Not tests like this are a bit sketchy. There's a massive range of incorrect behaviour that could be produced but get past. Especially as you've actually added ARM code, I think you should be testing that's correct.

It'd also be good to make sure we don't try to produce movw/movt on CPUs that don't actually have them. That's surprisingly easy to do with C++ code manually using BuildMI.

[dschuff]

• tnorthover review

[dschuff]

thanks for the review.

lib/Target/ARM/ARMISelLowering.cpp

7143 ↗

(On Diff #22262)

Yes, done.

test/CodeGen/ARM/struct_byval.ll

6 ↗

(On Diff #22262)

Done.

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::EmitStructByval(MachineInstr *MI,
 
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
   // Load an immediate to varEnd.
   unsigned varEnd = MRI.createVirtualRegister(TRC);
-  if (IsThumb2) {
+  if (Subtarget->useMovt(*MF)) {
     unsigned Vtmp = varEnd;
     if ((LoopSize & 0xFFFF0000) != 0)
       Vtmp = MRI.createVirtualRegister(TRC);
-    AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
-                       .addImm(LoopSize & 0xFFFF));
+    AddDefaultPred(BuildMI(BB, dl,
+                           TII->get(IsThumb2 ? ARM::t2MOVi16 : ARM::MOVi16),
+                           Vtmp).addImm(LoopSize & 0xFFFF));
 
     if ((LoopSize & 0xFFFF0000) != 0)
-      AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
-                         .addReg(Vtmp).addImm(LoopSize >> 16));
+      AddDefaultPred(BuildMI(BB, dl,
+                             TII->get(IsThumb2 ? ARM::t2MOVTi16 : ARM::MOVTi16),
+                             varEnd)
+                         .addReg(Vtmp)
+                         .addImm(LoopSize >> 16));
   } else {
     MachineConstantPool *ConstantPool = MF->getConstantPool();
     Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
     const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
 
     // MachineConstantPool wants an explicit alignment.
     unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
     if (Align == 0)

llvm/trunk/test/CodeGen/ARM/struct_byval.ll

 ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL
+; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT
+
+; NOMOVT-NOT: movt
 
 ; rdar://9877866
 %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] }
 %struct.LargeStruct = type { i32, [1001 x i8], [300 x i32] }
 
 define i32 @f() nounwind ssp {
 entry:
 ; CHECK-LABEL: f:

 ; CHECK: sub
 ; CHECK: str
 ; CHECK: bne
 ; THUMB-LABEL: g:
 ; THUMB: ldr
 ; THUMB: sub
 ; THUMB: str
 ; THUMB: bne
+; NACL-LABEL: g:
+; Ensure that use movw instead of constpool for the loop trip count. But don't
+; match the __stack_chk_guard movw
+; NACL: movw r{{[1-9]}}, #
+; NACL: ldr
+; NACL: sub
+; NACL: str
+; NACL: bne
   %st = alloca %struct.LargeStruct, align 4
   %call = call i32 @e2(%struct.LargeStruct* byval %st)
   ret i32 0
 }
 
 ; Generate a loop using NEON instructions
 define i32 @h() nounwind ssp {
 entry:
 ; CHECK-LABEL: h:
 ; CHECK: vld1
 ; CHECK: sub
 ; CHECK: vst1
 ; CHECK: bne
 ; THUMB-LABEL: h:
 ; THUMB: vld1
 ; THUMB: sub
 ; THUMB: vst1
 ; THUMB: bne
+; NACL: movw r{{[1-9]}}, #
+; NACL: vld1
+; NACL: sub
+; NACL: vst1
+; NACL: bne
   %st = alloca %struct.LargeStruct, align 16
   %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st)
   ret i32 0
 }
 
 declare i32 @e1(%struct.SmallStruct* nocapture byval %in) nounwind
 declare i32 @e2(%struct.LargeStruct* nocapture byval %in) nounwind
 declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind