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[AMDGPU] Define DWARF encoding for condition code registers
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Authored by t-tye on Jun 24 2020, 7:39 PM.

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Summary
  • Define DWARF register numbers for vector and scalar condition codes.
  • Document intended purpose of reserved DWARF register numbers.

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Event Timeline

t-tye created this revision.Jun 24 2020, 7:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2020, 7:39 PM
scott.linder accepted this revision.Jun 26 2020, 9:38 AM
This revision is now accepted and ready to land.Jun 26 2020, 9:38 AM
This revision was automatically updated to reflect the committed changes.