[hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.

[dsanders]

Summary

But still handle them the same way since I don't know how they differ on
this target.

No functional change intended. Depends on D8173.

[dsanders]

One thing I need to mention about this patch. I couldn't tell which additional constraints are supposed to be accepted by clang since the clang implementation currently accepts every possible constraint (HexagonTargetInfo::validateAsmConstraint() always returns true). For now, I've made Hexagon accept 'o', 'v', and 'm' in the backend but I'm happy to correct it if you can tell me which additional constraint codes should be there.

[colinl]

LGTM, Krzysztof, do you see any issues?

include/llvm/IR/InlineAsm.h

enum : uint32_t {
     Kind_Mem = 6,                // Memory operand, "m".
 
     // Memory constraint codes.
     // These could be tablegenerated but there's little need to do that since
     // there's plenty of space in the encoding to support the union of all
     // constraint codes for all targets.
     Constraint_Unknown = 0,
     Constraint_m,
-    Constraint_o, // Unused at the moment since Constraint_m is always used.
-    Constraint_v, // Unused at the moment since Constraint_m is always used.
+    Constraint_o,
+    Constraint_v,
     Constraint_Q,
     Constraint_Uv,
     Constraints_Max = Constraint_Uv,
     Constraints_ShiftAmount = 16,
 
     Flag_MatchingOperand = 0x80000000
   };
   

lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

 
 
 bool HexagonDAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
   SDValue Op0, Op1;
 
   switch (ConstraintID) {
-  case InlineAsm::Constraint_o:   // Offsetable.
-  case InlineAsm::Constraint_v:   // Not offsetable.
-  default: return true;
-  case InlineAsm::Constraint_m:   // Memory.
+  default: return true;
+  case InlineAsm::Constraint_o: // Offsetable.
+  case InlineAsm::Constraint_v: // Not offsetable.
+  case InlineAsm::Constraint_m: // Memory.
     if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
       return true;
     break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   return false;

lib/Target/Hexagon/HexagonISelLowering.h

public:
 
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  const std::string &Constraint,
                                  MVT VT) const override;
 
     unsigned getInlineAsmMemConstraint(
         const std::string ConstraintCode) const override {
-      // FIXME: Map different constraints differently.
-      return InlineAsm::Constraint_m;
+      if (ConstraintCode == "o")
+        return InlineAsm::Constraint_o;
+      else if (ConstraintCode == "v")
+        return InlineAsm::Constraint_v;
+      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
     }
 
     // Intrinsics
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
     /// The type may be VoidTy, in which case only return true if the addressing
     /// mode is legal for a load/store of any legal type.