[AArch64] Adjusts Cortex-A57 machine model to handle zero shift.

[cestes]

Summary

Integer ADD and SUB instructions on Cortex-A57 have different
latencies and processor resource usage (pipeline) when they have a
shift of zero vs. non-zero. This patches uses a SchedWriteVariant
to capture both.

[jmolloy]

LGTM, as far as I can tell.

[apazos]

I did not detect performance gain in the tests I ran (internal workload), but you are modelling is more precise now. LGTM.

[mcrosier]

Committed in r234593.

lib/Target/AArch64/AArch64SchedA57.td

 
 // Branch Instructions
 // -----------------------------------------------------------------------------
 
 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
 
 
+// Shifted Register with Shift == 0
+// ----------------------------------------------------------------------------
+
+def A57WriteISReg : SchedWriteVariant<[
+       SchedVar<RegShiftedPred, [WriteISReg]>,
+       SchedVar<NoSchedPred, [WriteI]>]>;
+def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
+
+
 // Divide and Multiply Instructions
 // -----------------------------------------------------------------------------
 
 // Multiply high
 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
 
 
 // Miscellaneous Data-Processing Instructions