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Differential D7849

[Mips][AsmBackend] Use MCTargetOptions to decide between elf32/64 based on ABI
Needs ReviewPublic

Authored by vmedic on Feb 24 2015, 1:53 AM.

Details

Reviewers
echristo
dsanders
Summary

This patch represents Mips specific part of D6476. It uses MCTargetOptions parameter passed to AsmBackend and base on ABI value initiates ELFObjectWriter to create ELF32/64 output. Consequently, it changes the way target triple is decided based on ELF header fields.

Diff Detail

Event Timeline

vmedic updated this revision to Diff 20578.Feb 24 2015, 1:53 AM
vmedic retitled this revision from to [Mips][AsmBackend] Use MCTargetOptions to decide between elf32/64 based on ABI.
vmedic updated this object.
vmedic edited the test plan for this revision. (Show Details)
vmedic added reviewers: dsanders, echristo.
vmedic added a parent revision: D6476: [Mips][ABI]The ELF container needs to depend on the ABI rather than the target triple..
vmedic added a subscriber: Unknown Object (MLST).
dsanders resigned from this revision.Jul 12 2019, 4:11 PM
Herald added subscribers: atanasyan, arichardson, sdardis. · View Herald TranscriptJul 12 2019, 4:11 PM

Revision Contents

PathSize
include/
llvm/
Object/
17 lines
lib/
Target/
Mips/
MCTargetDesc/
6 lines
15 lines
5 lines
3 lines
test/
MC/
Mips/
18 lines
mips64r6/
24 lines

Diff 20578

include/llvm/Object/ELFObjectFile.h

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case ELF::EM_HEXAGON: case ELF::EM_HEXAGON:
return Triple::hexagon; return Triple::hexagon;
case ELF::EM_MIPS: case ELF::EM_MIPS:
switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) { switch (EF.getHeader()->e_flags & ELF::EF_MIPS_ARCH) {
case ELF::ELFCLASS32: case ELF::EF_MIPS_ARCH_32R6:
case ELF::EF_MIPS_ARCH_32R2:
case ELF::EF_MIPS_ARCH_32:
case ELF::EF_MIPS_ARCH_2:
case ELF::EF_MIPS_ARCH_1:
return IsLittleEndian ? Triple::mipsel : Triple::mips; return IsLittleEndian ? Triple::mipsel : Triple::mips;
case ELF::ELFCLASS64: case ELF::EF_MIPS_ARCH_64R6:
case ELF::EF_MIPS_ARCH_64R2:
case ELF::EF_MIPS_ARCH_64:
case ELF::EF_MIPS_ARCH_5:
case ELF::EF_MIPS_ARCH_4:
case ELF::EF_MIPS_ARCH_3:
return IsLittleEndian ? Triple::mips64el : Triple::mips64; return IsLittleEndian ? Triple::mips64el : Triple::mips64;
default: default:
report_fatal_error("Invalid ELFCLASS!"); report_fatal_error("Invalid MIPS ARCH!");
} }
case ELF::EM_PPC: case ELF::EM_PPC:
return Triple::ppc; return Triple::ppc;
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lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

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Triple::OSType OSType; Triple::OSType OSType;
bool IsLittle; // Big or little endian bool IsLittle; // Big or little endian
bool Is64Bit; // 32 or 64 bit words bool Is64Bit; // 32 or 64 bit words
bool IsN64; // Is ABI n64
public: public:
MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle, MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle,
bool _is64Bit) bool _is64Bit, bool _isN64)
: MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), : MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
Is64Bit(_is64Bit) {} Is64Bit(_is64Bit), IsN64(_isN64) {}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const override; MCObjectWriter *createObjectWriter(raw_ostream &OS) const override;
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lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

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#include "MCTargetDesc/MipsFixupKinds.h" #include "MCTargetDesc/MipsFixupKinds.h"
#include "MCTargetDesc/MipsAsmBackend.h" #include "MCTargetDesc/MipsAsmBackend.h"
#include "MCTargetDesc/MipsMCTargetDesc.h" #include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MCTargetDesc/MipsABIInfo.h"
#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h" #include "llvm/MC/MCContext.h"
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MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const { MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
return createMipsELFObjectWriter(OS, return createMipsELFObjectWriter(OS,
MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit, IsN64);
} }
// Little-endian fixup data byte ordering: // Little-endian fixup data byte ordering:
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StringRef TT, StringRef TT,
StringRef CPU, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
return new MipsAsmBackend(T, Triple(TT).getOS(), return new MipsAsmBackend(T, Triple(TT).getOS(),
/*IsLittle*/true, /*Is64Bit*/false); /*IsLittle*/true, /*Is64Bit*/false, ABI.IsN64());
} }
MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
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StringRef TT, StringRef TT,
StringRef CPU, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
return new MipsAsmBackend(T, Triple(TT).getOS(), return new MipsAsmBackend(T, Triple(TT).getOS(),
/*IsLittle*/false, /*Is64Bit*/false); /*IsLittle*/false, /*Is64Bit*/false, ABI.IsN64());
} }
MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
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StringRef TT, StringRef TT,
StringRef CPU, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
return new MipsAsmBackend(T, Triple(TT).getOS(), return new MipsAsmBackend(T, Triple(TT).getOS(),
/*IsLittle*/true, /*Is64Bit*/true); /*IsLittle*/true, /*Is64Bit*/true, ABI.IsN64());
} }
MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
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StringRef TT, StringRef TT,
StringRef CPU, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
return new MipsAsmBackend(T, Triple(TT).getOS(), return new MipsAsmBackend(T, Triple(TT).getOS(),
/*IsLittle*/false, /*Is64Bit*/true); /*IsLittle*/false, /*Is64Bit*/true, ABI.IsN64());
} }
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lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

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MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS, MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS,
uint8_t OSABI, uint8_t OSABI,
bool IsLittleEndian, bool IsLittleEndian,
bool Is64Bit) { bool Is64Bit,
MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(Is64Bit, OSABI, bool IsN64) {
MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(IsN64, OSABI,
(Is64Bit) ? true : false, (Is64Bit) ? true : false,
IsLittleEndian); IsLittleEndian);
return createELFObjectWriter(MOTW, OS, IsLittleEndian); return createELFObjectWriter(MOTW, OS, IsLittleEndian);
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lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

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const MCTargetOptions &Options); const MCTargetOptions &Options);
MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI, MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
bool IsLittleEndian, bool Is64Bit); bool IsLittleEndian,
bool Is64Bit, bool IsN64);
namespace MIPS_MC { namespace MIPS_MC {
StringRef selectMipsCPU(StringRef TT, StringRef CPU); StringRef selectMipsCPU(StringRef TT, StringRef CPU);
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test/MC/Mips/cpsetup.s

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# NXX: sd $gp, 8($sp) # NXX: sd $gp, 8($sp)
# NXX: lui $gp, 0 # NXX: lui $gp, 0
# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror # N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
# N23: R_MIPS_GPREL16 __cerror
# NXX: addiu $gp, $gp, 0 # NXX: addiu $gp, $gp, 0
# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
# N32: R_MIPS_GPREL16 __cerror
# N32: addu $gp, $gp, $25 # N32: addu $gp, $gp, $25
# N64: daddu $gp, $gp, $25 # N64: daddu $gp, $gp, $25
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# NXX: move $2, $gp # NXX: move $2, $gp
# NXX: lui $gp, 0 # NXX: lui $gp, 0
# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror # N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
# N32: R_MIPS_GPREL16 __cerror
# NXX: addiu $gp, $gp, 0 # NXX: addiu $gp, $gp, 0
# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
# N32: R_MIPS_GPREL16 __cerror
# N32: addu $gp, $gp, $25 # N32: addu $gp, $gp, $25
# N64: daddu $gp, $gp, $25 # N64: daddu $gp, $gp, $25
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# NXX: move $2, $gp # NXX: move $2, $gp
# NXX: lui $gp, 0 # NXX: lui $gp, 0
# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 $tmp0 # N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 $tmp0
# N32: R_MIPS_GPREL16 $tmp0
# NXX: addiu $gp, $gp, 0 # NXX: addiu $gp, $gp, 0
# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 $tmp0 # N32: R_MIPS_GPREL16 $tmp0
# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 $tmp0
# N32: addu $gp, $gp, $25 # N32: addu $gp, $gp, $25
# N64: daddu $gp, $gp, $25 # N64: daddu $gp, $gp, $25
# NXX: nop # NXX: nop
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test/MC/Mips/mips64r6/relocations.s

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# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-ELF: Relocations [ # CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 # CHECK-ELF: 0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0 # CHECK-ELF: 0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0 # CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 # CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC18_S3 bar 0x0 # CHECK-ELF: 0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
addiupc $2,bar addiupc $2,bar
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