[PowerPC] Implement miscellaneous vector logical operations introduced in POWER8

[kbarton]

Summary

This change implements the following three logical vector operations:

• veqv (vector equivalence)
• vnand
• vorc

I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions.

[wschmidt]

This LGTM -- could you expand on the FIXME to indicate what we discussed the other day? I.e., that the patterns should be differentiated by HasVSX and !HasVSX so that uses of AddedComplexity are minimized?

[hfinkel]

In D7469#119824, @wschmidt wrote:

This LGTM -- could you expand on the FIXME to indicate what we discussed the other day? I.e., that the patterns should be differentiated by HasVSX and !HasVSX so that uses of AddedComplexity are minimized?

LGTM too. My hope is that if we disable competing Altivec patterns when VSX is enabled (thus allowing the VSX patterns to be selected, which reduces register pressure), then we won't need the added complexity for the VSX patterns at all. Another option might be to treat the added complexity for VSX patterns in a more principled way (adding only 1 or 2 under the theory that using VSX over Altivec could save one or two extra copies from the register allocator).

[kbarton]

How is the following:

FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
VSX equivalents. We need to fix this up at some point. Two possible
solutions for this problem:
1. Disable Altivec patterns that compete with VSX patterns using the
!HasVSX predicate. This essentially favours VSX over Altivec, in
hopes of reducing register pressure (larger register set using VSX
instructions then VMX instructions)
2. Employ a more disciplined use of AddedComplexity, which would provide
more fine-grained control then option 1. This would be beneficial
if we find situations where Altivec is really preferred over VSX.

[hfinkel]

In D7469#119843, @kbarton wrote:

How is the following:

FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
VSX equivalents. We need to fix this up at some point. Two possible
solutions for this problem:
1. Disable Altivec patterns that compete with VSX patterns using the
!HasVSX predicate. This essentially favours VSX over Altivec, in
hopes of reducing register pressure (larger register set using VSX
instructions then VMX instructions)
2. Employ a more disciplined use of AddedComplexity, which would provide
// more fine-grained control then option 1. This would be beneficial

then -> than

// if we find situations where Altivec is really preferred over VSX.

LGTM, thanks!

[kbarton]

Patch submitted in r228580.

lib/Target/PowerPC/PPCInstrAltivec.td

def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
                         "vpopcnth $vD, $vB", IIC_VecGeneral,
                         [(set v8i16:$vD, (ctpop v8i16:$vB))]>;
 def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
                         "vpopcntw $vD, $vB", IIC_VecGeneral,
                         [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
                         "vpopcntd $vD, $vB", IIC_VecGeneral,
                         [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
+
+let isCommutable = 1 in {
+let AddedComplexity = 500 in {
+// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the VSX equivalents. We need to fix this up at some point. 
+def VEQV  : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                     "veqv $vD, $vA, $vB", IIC_VecGeneral,
+                     [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
+def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                     "vnand $vD, $vA, $vB", IIC_VecGeneral,
+                     [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
+def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                      "vorc $vD, $vA, $vB", IIC_VecGeneral,
+                      [(set v4i32:$vD, (or v4i32:$vA,
+                                           (vnot_ppc v4i32:$vB)))]>;
+} // AddedComplexity = 500
+} // isCommutable
 } // end HasP8Altivec

test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll

+; Check the miscellaneous logical vector operations added in P8
+; 
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+; Test x eqv y
+define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: veqv 2, 2, 3
+}
+
+; Test x vnand y
+define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = and <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: vnand 2, 2, 3
+}
+
+; Test x vorc y
+define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
+       %ret_val = or <4 x i32> %x, %tmp
+       ret <4 x i32> %ret_val
+; CHECK: vorc 2, 2, 3      
+}

test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x43 0x26 0x86
 
 # CHECK: vand 2, 3, 4                    
 0x10 0x43 0x24 0x04
 
 # CHECK: vandc 2, 3, 4                   
 0x10 0x43 0x24 0x44
 
+# CHECK: veqv 2, 3, 4
+0x10 0x43 0x26 0x84
+
+# CHECK: vnand 2, 3, 4
+0x10 0x43 0x25 0x84
+
+# CHECK: vorc 2, 3, 4
+0x10 0x43 0x25 0x44
+
 # CHECK: vnor 2, 3, 4                    
 0x10 0x43 0x25 0x04
 
 # CHECK: vor 2, 3, 4                     
 0x10 0x43 0x24 0x84
 
 # CHECK: vxor 2, 3, 4                    
 0x10 0x43 0x24 0xc4

test/MC/PowerPC/ppc64-encoding-vmx.s

 # Vector integer logical instructions
 
 # CHECK-BE: vand 2, 3, 4                    # encoding: [0x10,0x43,0x24,0x04]
 # CHECK-LE: vand 2, 3, 4                    # encoding: [0x04,0x24,0x43,0x10]
             vand 2, 3, 4
 # CHECK-BE: vandc 2, 3, 4                   # encoding: [0x10,0x43,0x24,0x44]
 # CHECK-LE: vandc 2, 3, 4                   # encoding: [0x44,0x24,0x43,0x10]
             vandc 2, 3, 4
+# CHECK-BE: veqv 2, 3, 4                    # encoding: [0x10,0x43,0x26,0x84]
+# CHECK-LE: veqv 2, 3, 4                    # encoding: [0x84,0x26,0x43,0x10]
+            veqv 2, 3, 4
+# CHECK-BE: vnand 2, 3, 4                   # encoding: [0x10,0x43,0x25,0x84]
+# CHECK-LE: vnand 2, 3, 4                   # encoding: [0x84,0x25,0x43,0x10]
+            vnand 2, 3, 4
+# CHECK-BE: vorc 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x44]
+# CHECK-LE: vorc 2, 3, 4                    # encoding: [0x44,0x25,0x43,0x10]
+            vorc 2, 3, 4
 # CHECK-BE: vnor 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x04]
 # CHECK-LE: vnor 2, 3, 4                    # encoding: [0x04,0x25,0x43,0x10]
             vnor 2, 3, 4
 # CHECK-BE: vor 2, 3, 4                     # encoding: [0x10,0x43,0x24,0x84]
 # CHECK-LE: vor 2, 3, 4                     # encoding: [0x84,0x24,0x43,0x10]
             vor 2, 3, 4
 # CHECK-BE: vxor 2, 3, 4                    # encoding: [0x10,0x43,0x24,0xc4]
 # CHECK-LE: vxor 2, 3, 4                    # encoding: [0xc4,0x24,0x43,0x10]