PR20778: [SelectionDAG] Teach the vector scalarizer about FP conversions.

[ab]

Summary

[SelectionDAG] Teach the vector scalarizer about FP conversions.

This adds support for legalization of instructions of the form:

[fp_conv] <1 x i1> %op to <1 x double>

where fp_conv is one of fpto[us]i, [us]itofp. This used to assert
because they were simply missing from the vector operand scalarizer.

A similar problem arose in r190830, with trunc instead.

Also, fix typos in comment and assert message (separate commit).

[arsenm]

The test isn't really accomplishing anything by using FileCheck. It should either add check lines for the conversions, or not use FileCheck

[ab]

Right. The output doesn't really matter, so removing FileCheck altogether. Thanks!

-Ahmed

[ab]

Don't use FileCheck: we aren't testing the codegen of the operations, but the fact that they're scalarized correctly.

[echristo]

FWIW you should probably add some lines for the instruction patterns you expect to see and check for that. "Don't crash" is a pretty minimal test.

[ab]

Add back relevant instruction checks.

[qcolombet]

Hi Ahmed,

LGTM.

Thanks,
-Quentin

[echristo]

As a note we could make the code generated worse in any number of ways and still pass this test. Might be worth a test with the preferred code?

[ab]

Closed by commit rL220533 (authored by @ab).

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
       llvm_unreachable("Do not know how to scalarize this operator's operand!");
     case ISD::BITCAST:
       Res = ScalarizeVecOp_BITCAST(N);
       break;
     case ISD::ANY_EXTEND:
     case ISD::ZERO_EXTEND:
     case ISD::SIGN_EXTEND:
     case ISD::TRUNCATE:
+    case ISD::FP_TO_SINT:
+    case ISD::FP_TO_UINT:
+    case ISD::SINT_TO_FP:
+    case ISD::UINT_TO_FP:
       Res = ScalarizeVecOp_UnaryOp(N);
       break;
     case ISD::CONCAT_VECTORS:
       Res = ScalarizeVecOp_CONCAT_VECTORS(N);
       break;
     case ISD::EXTRACT_VECTOR_ELT:
       Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
       break;

llvm/trunk/test/CodeGen/AArch64/fpconv-vector-op-scalarize.ll

+; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
+
+; PR20778
+; Check that the legalizer doesn't crash when scalarizing FP conversion
+; instructions' operands.  The operands are all illegal on AArch64,
+; ensuring they are legalized.  The results are all legal.
+
+define <1 x double> @test_sitofp(<1 x i1> %in) {
+; CHECK-LABEL: test_sitofp:
+; CHECK:       sbfx  w8, w0, #0, #1
+; CHECK-NEXT:  scvtf d0, w8
+; CHECK-NEXT:  ret
+entry:
+  %0 = sitofp <1 x i1> %in to <1 x double>
+  ret <1 x double> %0
+}
+
+define <1 x double> @test_uitofp(<1 x i1> %in) {
+; CHECK-LABEL: test_uitofp:
+; CHECK:       and   w8, w0, #0x1
+; CHECK-NEXT:  ucvtf d0, w8
+; CHECK-NEXT:  ret
+entry:
+  %0 = uitofp <1 x i1> %in to <1 x double>
+  ret <1 x double> %0
+}
+
+define <1 x i64> @test_fptosi(<1 x fp128> %in) {
+; CHECK-LABEL: test_fptosi:
+; CHECK:       bl    ___fixtfdi
+; CHECK-NEXT:  fmov  d0, x0
+entry:
+  %0 = fptosi <1 x fp128> %in to <1 x i64>
+  ret <1 x i64> %0
+}
+
+define <1 x i64> @test_fptoui(<1 x fp128> %in) {
+; CHECK-LABEL: test_fptoui:
+; CHECK:       bl    ___fixunstfdi
+; CHECK-NEXT:  fmov  d0, x0
+entry:
+  %0 = fptoui <1 x fp128> %in to <1 x i64>
+  ret <1 x i64> %0
+}