This is an archive of the discontinued LLVM Phabricator instance.

[mips] Add support for COP1's Branch-On-Cond-Likely instructions
ClosedPublic

Authored by vkalintiris on Oct 15 2014, 9:22 AM.

Diff Detail

Repository
rL LLVM

Event Timeline

vkalintiris retitled this revision from to [mips] Add support for COP1's Branch-On-Cond-Likely instructions.
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Oct 16 2014, 1:48 AM
dsanders edited edge metadata.

LGTM with hasDelaySlot changed to 0 for the branch likelies and a test that ensures that the assembler doesn't insert nop's after branch likelies

lib/Target/Mips/MipsInstrFPU.td
565 ↗(On Diff #14949)

BC1F_FT is almost right but hasDelaySlot needs to be 0 for branch likelies.

This revision is now accepted and ready to land.Oct 16 2014, 1:48 AM
vkalintiris edited edge metadata.
  • Allow BC1F_FT instances to specify whether the have a delay slot or not.
vkalintiris closed this revision.Oct 17 2014, 7:19 AM
vkalintiris updated this revision to Diff 15074.

Closed by commit rL220042 (authored by @vkalintiris).