Add PIC-level support in LLVM, and implement it for PowerPC

[jhibbits]

Summary

This adds PIC-level (small/large) support to LLVM, and implements the
appropriate levels for PowerPC. The PIC Level argument added to
LLVMTargetMachine is ignored by most architectures, but understood by PowerPC
currently (can be added to SPARC, too). The necessary Clang change is in a
separate commit.

[jhibbits]

Remove vestiges of secure-PLT (pointed out by Joerg Sonnenberger), which belongs in a separate commit.

[echristo]

Go ahead and separate out the relocation bits from the pic level bits please.

Thanks!

include/llvm/MC/MCCodeGenInfo.h

27

Comment to match.

include/llvm/MC/MCExpr.h

253 ↗

(On Diff #13423)

Separate patch from the pic level stuff?

[jhibbits]

Break out PIC level ABI change. Usage for PowerPC will be separate.

[joerg]

Any reason for introducing the "default" level and not just go with large? I think that what's almost all software is using anyway.

[jhibbits]

In D5252#11, @joerg wrote:

Any reason for introducing the "default" level and not just go with large? I think that what's almost all software is using anyway.

I modeled it after the -relocation-model option. By allowing architecture defaults, the default for any given architecture can change without modifying any other arch.

[jhibbits]

Add missing files from previous diff.

[jhibbits]

Abandoning in favor of D5332 and subsequent PowerPC commit

include/llvm/CodeGen/CommandFlags.h

RelocModel("relocation-model",
               clEnumValN(Reloc::Static, "static",
                       "Non-relocatable code"),
               clEnumValN(Reloc::PIC_, "pic",
                       "Fully relocatable, position independent code"),
               clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
                       "Relocatable external references, non-relocatable code"),
               clEnumValEnd));
 
+cl::opt<PICLevel::Level>
+PLevel("pic-level",
+           cl::desc("Choose PIC level (small or large)"),
+           cl::init(PICLevel::Default),
+           cl::values(
+              clEnumValN(PICLevel::Default, "default",
+                      "Target default PIC level"),
+              clEnumValN(PICLevel::Small, "small",
+                      "Small PIC model (-fpic)"),
+              clEnumValN(PICLevel::Large, "large",
+                      "Large PIC model (-fPIC)"),
+              clEnumValEnd));
+
 cl::opt<ThreadModel::Model>
 TMModel("thread-model",
         cl::desc("Choose threading model"),
         cl::init(ThreadModel::POSIX),
         cl::values(clEnumValN(ThreadModel::POSIX, "posix",
                               "POSIX thread model"),
                    clEnumValN(ThreadModel::Single, "single",
                               "Single thread model"),

include/llvm/ExecutionEngine/ExecutionEngine.h

private:
   EngineKind::Kind WhichEngine;
   std::string *ErrorStr;
   CodeGenOpt::Level OptLevel;
   RTDyldMemoryManager *MCJMM;
   JITMemoryManager *JMM;
   TargetOptions Options;
   Reloc::Model RelocModel;
   CodeModel::Model CMModel;
+  PICLevel::Level PLevel;
   std::string MArch;
   std::string MCPU;
   SmallVector<std::string, 4> MAttrs;
   bool VerifyModules;
 
   /// InitEngine - Does the common initialization of default options.
   void InitEngine();
 
public:
   /// setCodeModel - Set the CodeModel that the ExecutionEngine target
   /// data is using. Defaults to target specific default
   /// "CodeModel::JITDefault".
   EngineBuilder &setCodeModel(CodeModel::Model M) {
     CMModel = M;
     return *this;
   }
 
+  /// setPICLevel - Set the PICLevel that the ExecutionEngine target is using.
+  /// Defaults to the target specific default "PICLevel::Default"
+  EngineBuilder &setPICLevel(PICLevel::Level PL) {
+    PLevel = PL;
+    return *this;
+  }
+
   /// setMArch - Override the architecture set by the Module's triple.
   EngineBuilder &setMArch(StringRef march) {
     MArch.assign(march.begin(), march.end());
     return *this;
   }
 
   /// setMCPU - Target a specific cpu type.
   EngineBuilder &setMCPU(StringRef mcpu) {

include/llvm/MC/MCCodeGenInfo.h

 
 namespace llvm {
 
   class MCCodeGenInfo {
     /// RelocationModel - Relocation model: static, pic, etc.
     ///
     Reloc::Model RelocationModel;
 
+    PICLevel::Level PLevel;
+
     /// CMModel - Code model.
     ///
     CodeModel::Model CMModel;
 
     /// OptLevel - Optimization level.
     ///
     CodeGenOpt::Level OptLevel;
 
   public:
     void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
                            CodeModel::Model CM = CodeModel::Default,
-                           CodeGenOpt::Level OL = CodeGenOpt::Default);
+                           CodeGenOpt::Level OL = CodeGenOpt::Default,
+                           PICLevel::Level PL = PICLevel::Default );
 
     Reloc::Model getRelocationModel() const { return RelocationModel; }
 
     CodeModel::Model getCodeModel() const { return CMModel; }
 
     CodeGenOpt::Level getOptLevel() const { return OptLevel; }
 
+    PICLevel::Level getPICLevel() const { return PLevel; }
+
     // Allow overriding OptLevel on a per-function basis.
     void setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; }
   };
 } // namespace llvm
 
 #endif

include/llvm/MC/MCObjectFileInfo.h

protected:
   /// COFF specific sections.
   ///
   const MCSection *DrectveSection;
   const MCSection *PDataSection;
   const MCSection *XDataSection;
 
 public:
   void InitMCObjectFileInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM,
-                            MCContext &ctx);
+                            PICLevel::Level PL, MCContext &ctx);
 
   bool getSupportsWeakOmittedEHFrame() const {
     return SupportsWeakOmittedEHFrame;
   }
   bool getSupportsCompactUnwindWithoutEHFrame() const {
     return SupportsCompactUnwindWithoutEHFrame;
   }
   bool getCommDirectiveSupportsAlignment() const {

include/llvm/Support/CodeGen.h

 
 namespace llvm {
 
   // Relocation model types.
   namespace Reloc {
     enum Model { Default, Static, PIC_, DynamicNoPIC };
   }
 
+  namespace PICLevel {
+    enum Level { Default, Small, Large };
+  };
+
   // Code model types.
   namespace CodeModel {
     enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
   }
 
   // TLS models.
   namespace TLSModel {
     enum Model {

include/llvm/Support/TargetRegistry.h

public:
 
     typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
 
     typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
                                             StringRef TT);
     typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
                                                     Reloc::Model RM,
                                                     CodeModel::Model CM,
-                                                    CodeGenOpt::Level OL);
+                                                    CodeGenOpt::Level OL,
+                                                    PICLevel::Level PL);
     typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
     typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info);
     typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
     typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
                                                         StringRef CPU,
                                                         StringRef Features);
     typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
                                                   StringRef TT,
                                                   StringRef CPU,
                                                   StringRef Features,
                                                   const TargetOptions &Options,
                                                   Reloc::Model RM,
                                                   CodeModel::Model CM,
-                                                  CodeGenOpt::Level OL);
+                                                  CodeGenOpt::Level OL,
+                                                  PICLevel::Level PL);
     typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
                                             MCStreamer &Streamer);
     typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
                                                 const MCRegisterInfo &MRI,
                                                 StringRef TT,
                                                 StringRef CPU);
     typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
         MCSubtargetInfo &STI,
MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
         return nullptr;
       return MCAsmInfoCtorFn(MRI, Triple);
     }
 
     /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
     ///
     MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
                                        CodeModel::Model CM,
-                                       CodeGenOpt::Level OL) const {
+                                       CodeGenOpt::Level OL,
+                                       PICLevel::Level PL) const {
       if (!MCCodeGenInfoCtorFn)
         return nullptr;
-      return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);
+      return MCCodeGenInfoCtorFn(Triple, RM, CM, OL, PL);
     }
 
     /// createMCInstrInfo - Create a MCInstrInfo implementation.
     ///
     MCInstrInfo *createMCInstrInfo() const {
       if (!MCInstrInfoCtorFn)
         return nullptr;
       return MCInstrInfoCtorFn();
public:
     /// \param Triple This argument is used to determine the target machine
     /// feature set; it should always be provided. Generally this should be
     /// either the target triple from the module, or the target triple of the
     /// host if that does not exist.
     TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
                              StringRef Features, const TargetOptions &Options,
                              Reloc::Model RM = Reloc::Default,
                              CodeModel::Model CM = CodeModel::Default,
-                             CodeGenOpt::Level OL = CodeGenOpt::Default) const {
+                             CodeGenOpt::Level OL = CodeGenOpt::Default,
+                             PICLevel::Level PL = PICLevel::Default) const {
       if (!TargetMachineCtorFn)
         return nullptr;
       return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,
-                                 RM, CM, OL);
+                                 RM, CM, OL, PL);
     }
 
     /// createMCAsmBackend - Create a target specific assembly parser.
     ///
     /// \param Triple The target triple string.
     MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
                                      StringRef Triple, StringRef CPU) const {
       if (!MCAsmBackendCtorFn)
namespace llvm {
   template<class MCCodeGenInfoImpl>
   struct RegisterMCCodeGenInfo {
     RegisterMCCodeGenInfo(Target &T) {
       TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
     }
   private:
     static MCCodeGenInfo *Allocator(StringRef /*TT*/, Reloc::Model /*RM*/,
                                     CodeModel::Model /*CM*/,
-                                    CodeGenOpt::Level /*OL*/) {
+                                    CodeGenOpt::Level /*OL*/,
+                                    PICLevel::Level /*PL*/) {
       return new MCCodeGenInfoImpl();
     }
   };
 
   /// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen
   /// info implementation.  This invokes the specified function to do the
   /// construction.  Usage:
   ///
struct RegisterTargetMachine {
     }
 
   private:
     static TargetMachine *Allocator(const Target &T, StringRef TT,
                                     StringRef CPU, StringRef FS,
                                     const TargetOptions &Options,
                                     Reloc::Model RM,
                                     CodeModel::Model CM,
-                                    CodeGenOpt::Level OL) {
-      return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
+                                    CodeGenOpt::Level OL,
+                                    PICLevel::Level PL) {
+      return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, PL);
     }
   };
 
   /// RegisterMCAsmBackend - Helper template for registering a target specific
   /// assembler backend. Usage:
   ///
   /// extern "C" void LLVMInitializeFooMCAsmBackend() {
   ///   extern Target TheFooTarget;

include/llvm/Target/TargetMachine.h

public:
 
   bool requiresStructuredCFG() const { return RequireStructuredCFG; }
   void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
 
   /// getRelocationModel - Returns the code generation relocation model. The
   /// choices are static, PIC, and dynamic-no-pic, and target default.
   Reloc::Model getRelocationModel() const;
 
+  /// getPICLevel - Returns the PIC level (-fpic vs -fPIC)
+  /// choices are small, large, and target default.
+  PICLevel::Level getPICLevel() const;
+
   /// getCodeModel - Returns the code model. The choices are small, kernel,
   /// medium, large, and target default.
   CodeModel::Model getCodeModel() const;
 
   /// getTLSModel - Returns the TLS model which should be used for the given
   /// global variable.
   TLSModel::Model getTLSModel(const GlobalValue *GV) const;
 

 /// LLVMTargetMachine - This class describes a target machine that is
 /// implemented with the LLVM target-independent code generator.
 ///
 class LLVMTargetMachine : public TargetMachine {
 protected: // Can only create subclasses.
   LLVMTargetMachine(const Target &T, StringRef TargetTriple,
                     StringRef CPU, StringRef FS, TargetOptions Options,
                     Reloc::Model RM, CodeModel::Model CM,
-                    CodeGenOpt::Level OL);
+                    CodeGenOpt::Level OL, PICLevel::Level PL);
 
   void initAsmInfo();
 public:
   /// \brief Register analysis passes for this target with a pass manager.
   ///
   /// This registers target independent analysis passes.
   void addAnalysisPasses(PassManagerBase &PM) override;
 

lib/CodeGen/LLVMTargetMachine.cpp

void LLVMTargetMachine::initAsmInfo() {
 
   AsmInfo = TmpAsmInfo;
 }
 
 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
                                      StringRef CPU, StringRef FS,
                                      TargetOptions Options,
                                      Reloc::Model RM, CodeModel::Model CM,
-                                     CodeGenOpt::Level OL)
+                                     CodeGenOpt::Level OL, PICLevel::Level PL)
   : TargetMachine(T, Triple, CPU, FS, Options) {
-  CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
+  CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL, PL);
 }
 
 void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
   PM.add(createBasicTargetTransformInfoPass(this));
 }
 
 /// addPassesToX helper drives creation and initialization of TargetPassConfig.
 static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,

lib/MC/MCCodeGenInfo.cpp

 // asm parsing, and asm printing. For example, relocation model.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCCodeGenInfo.h"
 using namespace llvm;
 
 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM,
-                                      CodeGenOpt::Level OL) {
+                                      CodeGenOpt::Level OL, PICLevel::Level PL) {
   RelocationModel = RM;
   CMModel = CM;
   OptLevel = OL;
+  PLevel = PL;
 }

lib/MC/MCObjectFileInfo.cpp

Ctx->getCOFFSection(".tls$",
                         COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
                         COFF::IMAGE_SCN_MEM_READ |
                         COFF::IMAGE_SCN_MEM_WRITE,
                         SectionKind::getDataRel());
 }
 
 void MCObjectFileInfo::InitMCObjectFileInfo(StringRef T, Reloc::Model relocm,
                                             CodeModel::Model cm,
+                                            PICLevel::Level pl,
                                             MCContext &ctx) {
   RelocM = relocm;
   CMModel = cm;
   Ctx = &ctx;
 
   // Common.
   CommDirectiveSupportsAlignment = true;
   SupportsWeakOmittedEHFrame = true;

lib/Object/IRObjectFile.cpp

if (!STI)
     return;
 
   std::unique_ptr<MCInstrInfo> MCII(T->createMCInstrInfo());
   if (!MCII)
     return;
 
   MCObjectFileInfo MOFI;
   MCContext MCCtx(MAI.get(), MRI.get(), &MOFI);
-  MOFI.InitMCObjectFileInfo(Triple, Reloc::Default, CodeModel::Default, MCCtx);
+  MOFI.InitMCObjectFileInfo(Triple, Reloc::Default, CodeModel::Default, PICLevel::Default, MCCtx);
   std::unique_ptr<RecordStreamer> Streamer(new RecordStreamer(MCCtx));
 
   std::unique_ptr<MemoryBuffer> Buffer(MemoryBuffer::getMemBuffer(InlineAsm));
   SourceMgr SrcMgr;
   SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc());
   std::unique_ptr<MCAsmParser> Parser(
       createMCAsmParser(SrcMgr, MCCtx, *Streamer, *MAI));
 

lib/Target/AArch64/AArch64TargetMachine.h

 class AArch64TargetMachine : public LLVMTargetMachine {
 protected:
   AArch64Subtarget Subtarget;
 
 public:
   AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL, bool IsLittleEndian);
+                       CodeGenOpt::Level OL, PICLevel::Level PL,
+                       bool IsLittleEndian);
 
   const AArch64Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   /// \brief Register AArch64 analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 // AArch64leTargetMachine - AArch64 little endian target machine.
 //
 class AArch64leTargetMachine : public AArch64TargetMachine {
   virtual void anchor();
 public:
   AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
                          Reloc::Model RM, CodeModel::Model CM,
-                         CodeGenOpt::Level OL);
+                         CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 // AArch64beTargetMachine - AArch64 big endian target machine.
 //
 class AArch64beTargetMachine : public AArch64TargetMachine {
   virtual void anchor();
 public:
   AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
                          Reloc::Model RM, CodeModel::Model CM,
-                         CodeGenOpt::Level OL);
+                         CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/AArch64/AArch64TargetMachine.cpp

 
 /// TargetMachine ctor - Create an AArch64 architecture model.
 ///
 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM, CodeModel::Model CM,
                                            CodeGenOpt::Level OL,
+                                           PICLevel::Level PL,
                                            bool LittleEndian)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this, LittleEndian) {
   initAsmInfo();
 }
 
 void AArch64leTargetMachine::anchor() { }
 
 AArch64leTargetMachine::
 AArch64leTargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL)
-  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+                       CodeGenOpt::Level OL,
+                       PICLevel::Level PL)
+  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, true) {}
 
 void AArch64beTargetMachine::anchor() { }
 
 AArch64beTargetMachine::
 AArch64beTargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL)
-  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+                       CodeGenOpt::Level OL,
+                       PICLevel::Level PL)
+  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, false) {}
 
 namespace {
 /// AArch64 Code Generator Pass Configuration Options.
 class AArch64PassConfig : public TargetPassConfig {
 public:
   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
 static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                  CodeModel::Model CM,
-                                                 CodeGenOpt::Level OL) {
+                                                 CodeGenOpt::Level OL,
+                                                 PICLevel::Level PL) {
   Triple TheTriple(TT);
   assert((TheTriple.isOSBinFormatELF() || TheTriple.isOSBinFormatMachO()) &&
          "Only expect Darwin and ELF targets");
 
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
   // The default MCJIT memory managers make no guarantees about where they can
   // find an executable page; JITed code needs to be able to refer to globals
if (TheTriple.isOSDarwin())
     RM = Reloc::PIC_;
   // On ELF platforms the default static relocation model has a smart enough
   // linker to cope with referencing external symbols defined in a shared
   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
   else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
     RM = Reloc::Static;
 
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createAArch64MCInstPrinter(const Target &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI,

lib/Target/ARM/ARMTargetMachine.h

 protected:
   ARMSubtarget        Subtarget;
 public:
   ARMBaseTargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS,
                        const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL,
+                       PICLevel::Level PL,
                        bool isLittle);
 
   const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   /// \brief Register ARM analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 
 /// ARMTargetMachine - ARM target machine.
 ///
 class ARMTargetMachine : public ARMBaseTargetMachine {
   virtual void anchor();
  public:
    ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
                     const TargetOptions &Options, Reloc::Model RM,
-                    CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
+                    CodeModel::Model CM, CodeGenOpt::Level OL, 
+                    PICLevel::Level PL, bool isLittle);
 };
 
 /// ARMLETargetMachine - ARM little endian target machine.
 ///
 class ARMLETargetMachine : public ARMTargetMachine {
   void anchor() override;
 public:
   ARMLETargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
-                     CodeGenOpt::Level OL);
+                     CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 /// ARMBETargetMachine - ARM big endian target machine.
 ///
 class ARMBETargetMachine : public ARMTargetMachine {
   void anchor() override;
 public:
   ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
                      const TargetOptions &Options, Reloc::Model RM,
-                     CodeModel::Model CM, CodeGenOpt::Level OL);
+                     CodeModel::Model CM, CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 /// ThumbTargetMachine - Thumb target machine.
 /// Due to the way architectures are handled, this represents both
 ///   Thumb-1 and Thumb-2.
 ///
 class ThumbTargetMachine : public ARMBaseTargetMachine {
   virtual void anchor();
 public:
   ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
                      const TargetOptions &Options, Reloc::Model RM,
-                     CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
+                     CodeModel::Model CM, CodeGenOpt::Level OL,
+                     PICLevel::Level PL, bool isLittle);
 };
 
 /// ThumbLETargetMachine - Thumb little endian target machine.
 ///
 class ThumbLETargetMachine : public ThumbTargetMachine {
   void anchor() override;
 public:
   ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 /// ThumbBETargetMachine - Thumb big endian target machine.
 ///
 class ThumbBETargetMachine : public ThumbTargetMachine {
   void anchor() override;
 public:
   ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/ARM/ARMTargetMachine.cpp

 
 
 /// TargetMachine ctor - Create an ARM architecture model.
 ///
 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL, bool isLittle)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                           CodeGenOpt::Level OL, PICLevel::Level PL,
+                                           bool isLittle)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this, isLittle, Options) {
 
   // Default to triple-appropriate float ABI
   if (Options.FloatABIType == FloatABI::Default)
     this->Options.FloatABIType =
         Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
 }
 
 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
   // Add first the target-independent BasicTTI pass, then our ARM pass. This
   // allows the ARM pass to delegate to the target independent layer when
   // appropriate.
   PM.add(createBasicTargetTransformInfoPass(this));
   PM.add(createARMTargetTransformInfoPass(this));
 }
 
 
 void ARMTargetMachine::anchor() { }
 
 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
                                    StringRef FS, const TargetOptions &Options,
                                    Reloc::Model RM, CodeModel::Model CM,
-                                   CodeGenOpt::Level OL, bool isLittle)
-    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
+                                   CodeGenOpt::Level OL, PICLevel::Level PL,
+                                   bool isLittle)
+    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, isLittle) {
   initAsmInfo();
   if (!Subtarget.hasARMOps())
     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
                        "support ARM mode execution!");
 }
 
 void ARMLETargetMachine::anchor() { }
 
 ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL)
-    : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+                                       CodeGenOpt::Level OL, PICLevel::Level PL)
+    : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, true) {}
 
 void ARMBETargetMachine::anchor() { }
 
 ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL)
-    : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+                                       CodeGenOpt::Level OL, PICLevel::Level PL)
+    : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, false) {}
 
 void ThumbTargetMachine::anchor() { }
 
 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL, bool isLittle)
-    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
+                                       CodeGenOpt::Level OL, PICLevel::Level PL,
+                                       bool isLittle)
+    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL,
                            isLittle) {
   initAsmInfo();
 }
 
 void ThumbLETargetMachine::anchor() { }
 
 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+                                           CodeGenOpt::Level OL, PICLevel::Level PL)
+    : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, true) {}
 
 void ThumbBETargetMachine::anchor() { }
 
 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+                                           CodeGenOpt::Level OL, PICLevel::Level PL)
+    : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, false) {}
 
 namespace {
 /// ARM Code Generator Pass Configuration Options.
 class ARMPassConfig : public TargetPassConfig {
 public:
   ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
     : TargetPassConfig(TM, PM) {}
 

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 
   return MAI;
 }
 
 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                              CodeModel::Model CM,
-                                             CodeGenOpt::Level OL) {
+                                             CodeGenOpt::Level OL,
+                                             PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     Triple TheTriple(TT);
     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
   }
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 // This is duplicated code. Refactor this.
 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
                                     MCContext &Ctx, MCAsmBackend &MAB,
                                     raw_ostream &OS,
                                     MCCodeEmitter *Emitter,

lib/Target/CppBackend/CPPTargetMachine.h

 
 class CPPSubtarget : public TargetSubtargetInfo {
 };
 
 struct CPPTargetMachine : public TargetMachine {
   CPPTargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS, const TargetOptions &Options,
                    Reloc::Model RM, CodeModel::Model CM,
-                   CodeGenOpt::Level OL)
+                   CodeGenOpt::Level OL, PICLevel::Level PL)
     : TargetMachine(T, TT, CPU, FS, Options), Subtarget() {}
 private:
   CPPSubtarget Subtarget;
 
 public:
   const CPPSubtarget *getSubtargetImpl() const override { return &Subtarget; }
   bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out,
                            CodeGenFileType FileType, bool DisableVerify,

lib/Target/Hexagon/HexagonTargetMachine.h

 
 class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
 
 public:
   HexagonTargetMachine(const Target &T, StringRef TT,StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL, PICLevel::Level PL);
 
   const HexagonSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
   static unsigned getModuleMatchQuality(const Module &M);
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 
 extern bool flag_aligned_memcpy;
 
 } // end namespace llvm
 
 #endif

lib/Target/Hexagon/HexagonTargetMachine.cpp

 ///
 
 /// Hexagon_TODO: Do I need an aggregate alignment?
 ///
 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                           CodeGenOpt::Level OL,
+                                           PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this) {
     initAsmInfo();
 }
 
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {
 public:

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
       nullptr, Hexagon::R30, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                              CodeModel::Model CM,
-                                             CodeGenOpt::Level OL) {
+                                             CodeGenOpt::Level OL,
+                                             PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   // For the time being, use static relocations, since there's really no
   // support for PIC yet.
-  X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
+  X->InitMCCodeGenInfo(Reloc::Static, CM, OL, PL);
   return X;
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeHexagonTargetMC() {
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
 

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
                                                     StringRef FS) {
   MCSubtargetInfo *X = new MCSubtargetInfo();
   InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }
 
 static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                 CodeModel::Model CM,
-                                                CodeGenOpt::Level OL) {
+                                                CodeGenOpt::Level OL,
+                                                PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createMSP430MCInstPrinter(const Target &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI,

lib/Target/MSP430/MSP430TargetMachine.h

 ///
 class MSP430TargetMachine : public LLVMTargetMachine {
   MSP430Subtarget        Subtarget;
 
 public:
   MSP430TargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS, const TargetOptions &Options,
                       Reloc::Model RM, CodeModel::Model CM,
-                      CodeGenOpt::Level OL);
+                      CodeGenOpt::Level OL, PICLevel::Level PL);
 
   const MSP430Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 }; // MSP430TargetMachine.
 
 } // end namespace llvm
 
 #endif

lib/Target/MSP430/MSP430TargetMachine.cpp

extern "C" void LLVMInitializeMSP430Target() {
   // Register the target.
   RegisterTargetMachine<MSP430TargetMachine> X(TheMSP430Target);
 }
 
 MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
                                          StringRef CPU, StringRef FS,
                                          const TargetOptions &Options,
                                          Reloc::Model RM, CodeModel::Model CM,
-                                         CodeGenOpt::Level OL)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                         CodeGenOpt::Level OL,
+                                         PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 namespace {
 /// MSP430 Code Generator Pass Configuration Options.
 class MSP430PassConfig : public TargetPassConfig {
 public:

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                               CodeModel::Model CM,
-                                              CodeGenOpt::Level OL) {
+                                              CodeGenOpt::Level OL,
+                                              PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (CM == CodeModel::JITDefault)
     RM = Reloc::Static;
   else if (RM == Reloc::Default)
     RM = Reloc::PIC_;
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
                                               unsigned SyntaxVariant,
                                               const MCAsmInfo &MAI,
                                               const MCInstrInfo &MII,
                                               const MCRegisterInfo &MRI,

lib/Target/Mips/MipsTargetMachine.h

class MipsTargetMachine : public LLVMTargetMachine {
   MipsSubtarget *Subtarget;
   MipsSubtarget DefaultSubtarget;
   MipsSubtarget NoMips16Subtarget;
   MipsSubtarget Mips16Subtarget;
 
 public:
   MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
                     const TargetOptions &Options, Reloc::Model RM,
-                    CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
+                    CodeModel::Model CM, CodeGenOpt::Level OL,
+                    PICLevel::Level PL, bool isLittle);
 
   virtual ~MipsTargetMachine() {}
 
   void addAnalysisPasses(PassManagerBase &PM) override;
 
   const MipsSubtarget *getSubtargetImpl() const override {
     if (Subtarget)
       return Subtarget;

 /// MipsebTargetMachine - Mips32/64 big endian target machine.
 ///
 class MipsebTargetMachine : public MipsTargetMachine {
   virtual void anchor();
 public:
   MipsebTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS, const TargetOptions &Options,
                       Reloc::Model RM, CodeModel::Model CM,
-                      CodeGenOpt::Level OL);
+                      CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 /// MipselTargetMachine - Mips32/64 little endian target machine.
 ///
 class MipselTargetMachine : public MipsTargetMachine {
   virtual void anchor();
 public:
   MipselTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS, const TargetOptions &Options,
                       Reloc::Model RM, CodeModel::Model CM,
-                      CodeGenOpt::Level OL);
+                      CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 } // End llvm namespace
 
 #endif

lib/Target/Mips/MipsTargetMachine.cpp

 // its pointer. Once decremented, all references are done with positive
 // offset from the stack/frame pointer, using StackGrowsUp enables
 // an easier handling.
 // Using CodeModel::Large enables different CALL behavior.
 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
                                      Reloc::Model RM, CodeModel::Model CM,
-                                     CodeGenOpt::Level OL, bool isLittle)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                     CodeGenOpt::Level OL,
+                                     PICLevel::Level PL,
+                                     bool isLittle)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, this),
       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
                         isLittle, this),
       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
                       isLittle, this) {
   Subtarget = &DefaultSubtarget;
   initAsmInfo();
 }
 
 void MipsebTargetMachine::anchor() { }
 
 MipsebTargetMachine::
 MipsebTargetMachine(const Target &T, StringRef TT,
                     StringRef CPU, StringRef FS, const TargetOptions &Options,
                     Reloc::Model RM, CodeModel::Model CM,
-                    CodeGenOpt::Level OL)
-  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+                    CodeGenOpt::Level OL, PICLevel::Level PL)
+  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, false) {}
 
 void MipselTargetMachine::anchor() { }
 
 MipselTargetMachine::
 MipselTargetMachine(const Target &T, StringRef TT,
                     StringRef CPU, StringRef FS, const TargetOptions &Options,
                     Reloc::Model RM, CodeModel::Model CM,
-                    CodeGenOpt::Level OL)
-  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+                    CodeGenOpt::Level OL, PICLevel::Level PL)
+  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, true) {}
 
 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   DEBUG(dbgs() << "resetSubtarget\n");
   AttributeSet FnAttrs = MF->getFunction()->getAttributes();
   bool Mips16Attr = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, "mips16");
   bool NoMips16Attr =
       FnAttrs.hasAttribute(AttributeSet::FunctionIndex, "nomips16");
   assert(!(Mips16Attr && NoMips16Attr) &&

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

 static MCSubtargetInfo *
 createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {
   MCSubtargetInfo *X = new MCSubtargetInfo();
   InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }
 
 static MCCodeGenInfo *createNVPTXMCCodeGenInfo(
-    StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
+    StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
+    PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createNVPTXMCInstPrinter(const Target &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI,

lib/Target/NVPTX/NVPTXTargetMachine.h

class NVPTXTargetMachine : public LLVMTargetMachine {
   NVPTXSubtarget Subtarget;
 
   // Hold Strings that can be free'd all together with NVPTXTargetMachine
   ManagedStringPool ManagedStrPool;
 
 public:
   NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
                      const TargetOptions &Options, Reloc::Model RM,
-                     CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
+                     CodeModel::Model CM, CodeGenOpt::Level OP,
+                     PICLevel::Level PL, bool is64bit);
 
   const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   ManagedStringPool *getManagedStrPool() const {
     return const_cast<ManagedStringPool *>(&ManagedStrPool);
   }
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   // Emission of machine code through MCJIT is not supported.
   bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_ostream &,
                          bool = true) override {
     return true;
   }
 
 }; // NVPTXTargetMachine.
 
 class NVPTXTargetMachine32 : public NVPTXTargetMachine {
   virtual void anchor();
 public:
   NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 class NVPTXTargetMachine64 : public NVPTXTargetMachine {
   virtual void anchor();
 public:
   NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL, PICLevel::Level PL);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/NVPTX/NVPTXTargetMachine.cpp

extern "C" void LLVMInitializeNVPTXTarget() {
   initializeNVPTXFavorNonGenericAddrSpacesPass(
     *PassRegistry::getPassRegistry());
 }
 
 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL, bool is64bit)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                       CodeGenOpt::Level OL,
+                                       PICLevel::Level PL,
+                                       bool is64bit)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this, is64bit) {
   initAsmInfo();
 }
 
 void NVPTXTargetMachine32::anchor() {}
 
 NVPTXTargetMachine32::NVPTXTargetMachine32(
     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
-    CodeGenOpt::Level OL)
-    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+    CodeGenOpt::Level OL, PICLevel::Level PL)
+    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, false) {}
 
 void NVPTXTargetMachine64::anchor() {}
 
 NVPTXTargetMachine64::NVPTXTargetMachine64(
     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
-    CodeGenOpt::Level OL)
-    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+    CodeGenOpt::Level OL, PICLevel::Level PL)
+    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, true) {}
 
 namespace {
 class NVPTXPassConfig : public TargetPassConfig {
 public:
   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 
   NVPTXTargetMachine &getNVPTXTargetMachine() const {

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
 static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                              CodeModel::Model CM,
-                                             CodeGenOpt::Level OL) {
+                                             CodeGenOpt::Level OL,
+                                             PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   if (RM == Reloc::Default) {
     Triple T(TT);
     if (T.isOSDarwin())
       RM = Reloc::DynamicNoPIC;
     else
       RM = Reloc::Static;
   }
   if (CM == CodeModel::Default) {
     Triple T(TT);
     if (!T.isOSDarwin() &&
         (T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le))
       CM = CodeModel::Medium;
   }
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  if (PL == PICLevel::Default) {
+    PL = PICLevel::Large;
+  }
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 namespace {
 class PPCTargetAsmStreamer : public PPCTargetStreamer {
   formatted_raw_ostream &OS;
 
 public:

lib/Target/PowerPC/PPCTargetMachine.h

 ///
 class PPCTargetMachine : public LLVMTargetMachine {
   PPCSubtarget        Subtarget;
 
 public:
   PPCTargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS, const TargetOptions &Options,
                    Reloc::Model RM, CodeModel::Model CM,
-                   CodeGenOpt::Level OL);
+                   CodeGenOpt::Level OL,
+                   PICLevel::Level PL);
 
   const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   /// \brief Register PPC analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 /// PPC32TargetMachine - PowerPC 32-bit target machine.
 ///
 class PPC32TargetMachine : public PPCTargetMachine {
   virtual void anchor();
 public:
   PPC32TargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
-                     CodeGenOpt::Level OL);
+                     CodeGenOpt::Level OL,
+                     PICLevel::Level PL);
 };
 
 /// PPC64TargetMachine - PowerPC 64-bit target machine.
 ///
 class PPC64TargetMachine : public PPCTargetMachine {
   virtual void anchor();
 public:
   PPC64TargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
-                     CodeGenOpt::Level OL);
+                     CodeGenOpt::Level OL,
+                     PICLevel::Level PL);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/PowerPC/PPCTargetMachine.cpp

extern "C" void LLVMInitializePowerPCTarget() {
   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
 }
 
 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
                                    StringRef FS, const TargetOptions &Options,
                                    Reloc::Model RM, CodeModel::Model CM,
-                                   CodeGenOpt::Level OL)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                   CodeGenOpt::Level OL,
+                                   PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this, OL) {
   initAsmInfo();
 }
 
 void PPC32TargetMachine::anchor() { }
 
 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL)
-  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
+                                       CodeGenOpt::Level OL,
+                                       PICLevel::Level PL)
+  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL) {
 }
 
 void PPC64TargetMachine::anchor() { }
 
 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU,  StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL)
-  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
+                                       CodeGenOpt::Level OL,
+                                       PICLevel::Level PL)
+  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL) {
 }
 
 
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
 namespace {

lib/Target/R600/AMDGPUTargetMachine.h

 
 class AMDGPUTargetMachine : public LLVMTargetMachine {
   AMDGPUSubtarget Subtarget;
   AMDGPUIntrinsicInfo IntrinsicInfo;
 
 public:
   AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
                       StringRef CPU, TargetOptions Options, Reloc::Model RM,
-                      CodeModel::Model CM, CodeGenOpt::Level OL);
+                      CodeModel::Model CM, CodeGenOpt::Level OL,
+                      PICLevel::Level PL);
   ~AMDGPUTargetMachine();
   const AMDGPUSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
   const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
     return &IntrinsicInfo;
   }
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   /// \brief Register R600 analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 } // End namespace llvm
 
 #endif

lib/Target/R600/AMDGPUTargetMachine.cpp

 static MachineSchedRegistry
 SchedCustomRegistry("r600", "Run R600's custom scheduler",
                     createR600MachineScheduler);
 
 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
                                          StringRef CPU, StringRef FS,
                                          TargetOptions Options, Reloc::Model RM,
                                          CodeModel::Model CM,
-                                         CodeGenOpt::Level OptLevel)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
+                                         CodeGenOpt::Level OptLevel,
+                                         PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel, PL),
       Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
   setRequiresStructuredCFG(true);
   initAsmInfo();
 }
 
 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
 }
 

lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp

static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
                                                    StringRef FS) {
   MCSubtargetInfo * X = new MCSubtargetInfo();
   InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }
 
 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                CodeModel::Model CM,
-                                               CodeGenOpt::Level OL) {
+                                               CodeGenOpt::Level OL,
+                                               PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI,

lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

 // abs64  Static  Large      text smaller than 2^31 bytes
 // pic13  PIC_    Small      GOT < 2^13 bytes
 // pic32  PIC_    Medium     GOT < 2^32 bytes
 //
 // All code models require that the text segment is smaller than 2GB.
 
 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                CodeModel::Model CM,
-                                               CodeGenOpt::Level OL) {
+                                               CodeGenOpt::Level OL,
+                                               PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // The default 32-bit code model is abs32/pic32 and the default 32-bit
   // code model for JIT is abs32.
   switch (CM) {
   default: break;
   case CodeModel::Default:
   case CodeModel::JITDefault: CM = CodeModel::Small; break;
   }
 
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                  CodeModel::Model CM,
-                                                 CodeGenOpt::Level OL) {
+                                                 CodeGenOpt::Level OL,
+                                                 PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // The default 64-bit code model is abs44/pic32 and the default 64-bit
   // code model for JIT is abs64.
   switch (CM) {
   default:  break;
   case CodeModel::Default:
     CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
     break;
   case CodeModel::JITDefault:
     CM = CodeModel::Large;
     break;
   }
 
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
                                     MCContext &Context, MCAsmBackend &MAB,
                                     raw_ostream &OS, MCCodeEmitter *Emitter,
                                     const MCSubtargetInfo &STI, bool RelaxAll,
                                     bool NoExecStack) {

lib/Target/Sparc/SparcTargetMachine.h

 namespace llvm {
 
 class SparcTargetMachine : public LLVMTargetMachine {
   SparcSubtarget Subtarget;
 public:
   SparcTargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
-                     CodeGenOpt::Level OL, bool is64bit);
+                     CodeGenOpt::Level OL, PICLevel::Level PL, bool is64bit);
 
   const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 
 /// SparcV8TargetMachine - Sparc 32-bit target machine
 ///
 class SparcV8TargetMachine : public SparcTargetMachine {
   virtual void anchor();
 public:
   SparcV8TargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS,
                        const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL,
+                       PICLevel::Level PL);
 };
 
 /// SparcV9TargetMachine - Sparc 64-bit target machine
 ///
 class SparcV9TargetMachine : public SparcTargetMachine {
   virtual void anchor();
 public:
   SparcV9TargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS,
                        const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL,
+                       PICLevel::Level PL);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/Sparc/SparcTargetMachine.cpp

 
 /// SparcTargetMachine ctor - Create an ILP32 architecture model
 ///
 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
                                        CodeGenOpt::Level OL,
+                                       PICLevel::Level PL,
                                        bool is64bit)
-  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
     Subtarget(TT, CPU, FS, *this, is64bit) {
   initAsmInfo();
 }
 
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
 public:

 void SparcV8TargetMachine::anchor() { }
 
 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
                                            StringRef TT, StringRef CPU,
                                            StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM,
                                            CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
+                                           CodeGenOpt::Level OL,
+                                           PICLevel::Level PL)
+  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, false) {
 }
 
 void SparcV9TargetMachine::anchor() { }
 
 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
                                            StringRef TT,  StringRef CPU,
                                            StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM,
                                            CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
+                                           CodeGenOpt::Level OL,
+                                           PICLevel::Level PL)
+  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL, true) {
 }

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT,
                                                      StringRef FS) {
   MCSubtargetInfo *X = new MCSubtargetInfo();
   InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }
 
 static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                  CodeModel::Model CM,
-                                                 CodeGenOpt::Level OL) {
+                                                 CodeGenOpt::Level OL,
+                                                 PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // Static code is suitable for use in a dynamic executable; there is no
   // separate DynamicNoPIC model.
   if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
     RM = Reloc::Static;
 
   // For SystemZ we define the models as follows:
static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM,
   //   image is less than 4GB in size.  GOT entries will likewise be
   //   in range of LARL.  However, the JIT environment has no equivalent
   //   of copy relocs, so locally-binding data symbols might not be in
   //   the range of LARL.  We need the Medium model in that case.
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
   else if (CM == CodeModel::JITDefault)
     CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createSystemZMCInstPrinter(const Target &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI,

lib/Target/SystemZ/SystemZTargetMachine.h

 
 class SystemZTargetMachine : public LLVMTargetMachine {
   SystemZSubtarget        Subtarget;
 
 public:
   SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
-                       CodeGenOpt::Level OL);
+                       CodeGenOpt::Level OL, PICLevel::Level);
 
   // Override TargetMachine.
   const SystemZSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
   // Override LLVMTargetMachine
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/SystemZTargetMachine.cpp

extern "C" void LLVMInitializeSystemZTarget() {
   // Register the target.
   RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget);
 }
 
 SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Reloc::Model RM, CodeModel::Model CM,
-                                           CodeGenOpt::Level OL)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                           CodeGenOpt::Level OL,
+                                           PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 namespace {
 /// SystemZ Code Generator Pass Configuration Options.
 class SystemZPassConfig : public TargetPassConfig {
 public:

lib/Target/TargetLoweringObjectFile.cpp

 /// Initialize - this method must be called before any actual lowering is
 /// done.  This specifies the current context for codegen, and gives the
 /// lowering implementations a chance to set up their default sections.
 void TargetLoweringObjectFile::Initialize(MCContext &ctx,
                                           const TargetMachine &TM) {
   Ctx = &ctx;
   DL = TM.getSubtargetImpl()->getDataLayout();
   InitMCObjectFileInfo(TM.getTargetTriple(),
-                       TM.getRelocationModel(), TM.getCodeModel(), *Ctx);
+                       TM.getRelocationModel(), TM.getCodeModel(), TM.getPICLevel(), *Ctx);
 }
 
 TargetLoweringObjectFile::~TargetLoweringObjectFile() {
 }
 
 static bool isSuitableForBSS(const GlobalVariable *GV, bool NoZerosInBSS) {
   const Constant *C = GV->getInitializer();
 

lib/Target/TargetMachine.cpp

 void TargetMachine::setFunctionSections(bool V) {
   Options.FunctionSections = V;
 }
 
 void TargetMachine::setDataSections(bool V) {
   Options.DataSections = V;
 }
 
+/// getPICLevel - Returns the code generation PIC level. The choices are
+/// small, large, and target default.
+PICLevel::Level TargetMachine::getPICLevel() const {
+  if (!CodeGenInfo)
+    return PICLevel::Default;
+  return CodeGenInfo->getPICLevel();
+}
+
 void TargetMachine::getNameWithPrefix(SmallVectorImpl<char> &Name,
                                       const GlobalValue *GV, Mangler &Mang,
                                       bool MayAlwaysUsePrivate) const {
   if (MayAlwaysUsePrivate || !GV->hasPrivateLinkage()) {
     // Simple case: If GV is not private, it is not important to find out if
     // private labels are legal in this case or not.
     Mang.getNameWithPrefix(Name, GV, false);
     return;

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
       nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
   MAI->addInitialFrameState(Inst2);
 
   return MAI;
 }
 
 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                              CodeModel::Model CM,
-                                             CodeGenOpt::Level OL) {
+                                             CodeGenOpt::Level OL,
+                                             PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   Triple T(TT);
   bool is64Bit = T.getArch() == Triple::x86_64;
 
   if (RM == Reloc::Default) {
     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
 
   // For static codegen, if we're not already set, use Small codegen.
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
   else if (CM == CodeModel::JITDefault)
     // 64-bit JIT places everything in the same buffer except external funcs.
     CM = is64Bit ? CodeModel::Large : CodeModel::Small;
 
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
                                     MCContext &Ctx, MCAsmBackend &MAB,
                                     raw_ostream &_OS,
                                     MCCodeEmitter *_Emitter,
                                     const MCSubtargetInfo &STI,

lib/Target/X86/X86TargetMachine.h

 class X86TargetMachine final : public LLVMTargetMachine {
   virtual void anchor();
   X86Subtarget       Subtarget;
 
 public:
   X86TargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS, const TargetOptions &Options,
                    Reloc::Model RM, CodeModel::Model CM,
-                   CodeGenOpt::Level OL);
+                   CodeGenOpt::Level OL, PICLevel::Level PL);
   const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   /// \brief Register X86 analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
 
   // Set up the pass pipeline.
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 
 } // End llvm namespace
 
 #endif

lib/Target/X86/X86TargetMachine.cpp

 
 void X86TargetMachine::anchor() { }
 
 /// X86TargetMachine ctor - Create an X86 target.
 ///
 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
                                    StringRef FS, const TargetOptions &Options,
                                    Reloc::Model RM, CodeModel::Model CM,
-                                   CodeGenOpt::Level OL)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                   CodeGenOpt::Level OL, PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
   // default to hard float ABI
   if (Options.FloatABIType == FloatABI::Default)
     this->Options.FloatABIType = FloatABI::Hard;
 
   // Windows stack unwinder gets confused when execution flow "falls through"
   // after a call to 'noreturn' function.
   // To prevent that, we emit a trap for 'unreachable' IR instructions.

lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                                CodeModel::Model CM,
-                                               CodeGenOpt::Level OL) {
+                                               CodeGenOpt::Level OL,
+                                               PICLevel::Level PL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     RM = Reloc::Static;
   }
   if (CM == CodeModel::Default) {
     CM = CodeModel::Small;
   }
   if (CM != CodeModel::Small && CM != CodeModel::Large)
     report_fatal_error("Target only supports CodeModel Small or Large");
 
-  X->InitMCCodeGenInfo(RM, CM, OL);
+  X->InitMCCodeGenInfo(RM, CM, OL, PL);
   return X;
 }
 
 static MCInstPrinter *createXCoreMCInstPrinter(const Target &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI,

lib/Target/XCore/XCoreTargetMachine.h

 namespace llvm {
 
 class XCoreTargetMachine : public LLVMTargetMachine {
   XCoreSubtarget Subtarget;
 public:
   XCoreTargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
-                     CodeGenOpt::Level OL);
+                     CodeGenOpt::Level OL, PICLevel::Level PL);
 
   const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/XCore/XCoreTargetMachine.cpp

 using namespace llvm;
 
 /// XCoreTargetMachine ctor - Create an ILP32 architecture model
 ///
 XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL)
-    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+                                       CodeGenOpt::Level OL,
+                                       PICLevel::Level PL)
+    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, PL),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 namespace {
 /// XCore Code Generator Pass Configuration Options.
 class XCorePassConfig : public TargetPassConfig {
 public:

tools/llc/llc.cpp

static int compileModule(char **argv, LLVMContext &Context) {
   TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
   Options.DisableIntegratedAS = NoIntegratedAssembler;
   Options.MCOptions.ShowMCEncoding = ShowMCEncoding;
   Options.MCOptions.MCUseDwarfDirectory = EnableDwarfDirectory;
   Options.MCOptions.AsmVerbose = AsmVerbose;
 
   std::unique_ptr<TargetMachine> target(
       TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr,
-                                     Options, RelocModel, CMModel, OLvl));
+                                     Options, RelocModel, CMModel,
+                                     OLvl, PLevel));
   assert(target.get() && "Could not allocate target machine!");
 
   // If we don't have a module then just exit now. We do this down
   // here since the CPU/Feature help is underneath the target machine
   // creation.
   if (SkipModule)
     return 0;
 

tools/llvm-mc/llvm-mc.cpp

RelocModel("relocation-model",
             clEnumValN(Reloc::Static, "static",
                        "Non-relocatable code"),
             clEnumValN(Reloc::PIC_, "pic",
                        "Fully relocatable, position independent code"),
             clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
                        "Relocatable external references, non-relocatable code"),
             clEnumValEnd));
 
+static cl::opt<PICLevel::Level>
+PLevel("pic-level",
+             cl::desc("Choose the PIC level (small or large)"),
+             cl::init(PICLevel::Default),
+             cl::values(
+            clEnumValN(PICLevel::Default, "default",
+                       "Target default PIC level"),
+            clEnumValN(PICLevel::Small, "small",
+                       "Small-model PIC (-fpic)"),
+            clEnumValN(PICLevel::Large, "large",
+                       "Large-model PIC (-fPIC)"),
+            clEnumValEnd));
+
 static cl::opt<llvm::CodeModel::Model>
 CMModel("code-model",
         cl::desc("Choose code model"),
         cl::init(CodeModel::Default),
         cl::values(clEnumValN(CodeModel::Default, "default",
                               "Target default code model"),
                    clEnumValN(CodeModel::Small, "small",
                               "Small code model"),
if (CompressDebugSections) {
     }
     MAI->setCompressDebugSections(true);
   }
 
   // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
   // MCObjectFileInfo needs a MCContext reference in order to initialize itself.
   MCObjectFileInfo MOFI;
   MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
-  MOFI.InitMCObjectFileInfo(TripleName, RelocModel, CMModel, Ctx);
+  MOFI.InitMCObjectFileInfo(TripleName, RelocModel, CMModel, PLevel, Ctx);
 
   if (SaveTempLabels)
     Ctx.setAllowTemporaryLabels(false);
 
   Ctx.setGenDwarfForAssembly(GenDwarfForAssembly);
   // Default to 4 for dwarf version.
   unsigned DwarfVersion = MCOptions.DwarfVersion ? MCOptions.DwarfVersion : 4;
   if (DwarfVersion < 2 || DwarfVersion > 4) {