arm_acle: Implement data processing intrinsics

[kongyi]

Summary

ACLE 2.0 section 9.2 defines the following "miscellaneous data processing intrinsics": __clz, __cls, __ror, __rev, __rev16, __revsh and __rbit.

__clz has already been implemented in the arm_acle.h header file. The rest are not supported yet. This patch completes ACLE data processing intrinsics.

[t.p.northover]

Hi Yi,

Thanks for working on this. I spotted a couple of issues (but I'm going away for a week tomorrow, so you may want to dig up another reviewer too):

lib/Headers/arm_acle.h

114

This is undefined behaviour when y >= 32 or == 0.

155

This seems to be off-by-1 from what I'd expect. It certainly returns an incorrect value for t == 0 (according to ACLE).

[rengolin]

Some more comments.

cheers,
--renato

lib/Headers/arm_acle.h

114

ACLE says: "y can take any value", so we need some safeguards on all these shift functions.

In this case, something like:

if (y >= 32) y %= 32;
if (y == 0) return x;
return (x >> y) | (x << 32 - y);

If that's the intended, but not explicit, semantics.

201

You could keep the order and put rbitll after rbitl.

test/CodeGen/arm_acle.c

172

Doesn't this call CLZ as well?

[kongyi]

Addressed Renato's and Tim's comments.

ROR implementation now conforms ACLE specification. CLS intrinsics are removed for now.

[rengolin]

Thanks Yi, LGTM.

--renato

lib/Headers/arm_acle.h

 
 /* 8.7 NOP */
 static __inline__ void __attribute__((always_inline, nodebug)) __nop(void) {
   __builtin_arm_nop();
 }
 
 /* 9 DATA-PROCESSING INTRINSICS */
 /* 9.2 Miscellaneous data-processing intrinsics */
+/* ROR */
+static __inline__ uint32_t __attribute__((always_inline, nodebug))
+  __ror(uint32_t x, uint32_t y) {
+  if (y == 0)  return y;
+  if (y >= 32) y %= 32;
+  return (x >> y) | (x << (32 - y));
+}
+
+static __inline__ uint64_t __attribute__((always_inline, nodebug))
+  __rorll(uint64_t x, uint32_t y) {
+  if (y == 0)  return y;
+  if (y >= 64) y %= 64;
+  return (x >> y) | (x << (64 - y));
+}
+
+static __inline__ unsigned long __attribute__((always_inline, nodebug))
+  __rorl(unsigned long x, uint32_t y) {
+#if __SIZEOF_LONG__ == 4
+  return __ror(x, y);
+#else
+  return __rorll(x, y);
+#endif
+}
+
+
+/* CLZ */
 static __inline__ uint32_t __attribute__((always_inline, nodebug))
   __clz(uint32_t t) {
   return __builtin_clz(t);
 }
 
 static __inline__ unsigned long __attribute__((always_inline, nodebug))
   __clzl(unsigned long t) {
   return __builtin_clzl(t);
 }
 
 static __inline__ uint64_t __attribute__((always_inline, nodebug))
   __clzll(uint64_t t) {
   return __builtin_clzll(t);
 }
 
+/* REV */
 static __inline__ uint32_t __attribute__((always_inline, nodebug))
   __rev(uint32_t t) {
   return __builtin_bswap32(t);
 }
 
 static __inline__ unsigned long __attribute__((always_inline, nodebug))
   __revl(unsigned long t) {
 #if __SIZEOF_LONG__ == 4
   return __builtin_bswap32(t);
 #else
   return __builtin_bswap64(t);
 #endif
 }
 
 static __inline__ uint64_t __attribute__((always_inline, nodebug))
   __revll(uint64_t t) {
   return __builtin_bswap64(t);
 }
 
+/* REV16 */
+static __inline__ uint32_t __attribute__((always_inline, nodebug))
+  __rev16(uint32_t t) {
+  return __ror(__rev(t), 16);
+}
+
+static __inline__ unsigned long __attribute__((always_inline, nodebug))
+  __rev16l(unsigned long t) {
+    return __rorl(__revl(t), sizeof(long) / 2);
+}
+
+static __inline__ uint64_t __attribute__((always_inline, nodebug))
+  __rev16ll(uint64_t t) {
+  return __rorll(__revll(t), 32);
+}
+
+/* REVSH */
+static __inline__ int16_t __attribute__((always_inline, nodebug))
+  __revsh(int16_t t) {
+  return __builtin_bswap16(t);
+}
+
+/* RBIT */
+static __inline__ uint32_t __attribute__((always_inline, nodebug))
+  __rbit(uint32_t t) {
+  return __builtin_arm_rbit(t);
+}
+
+static __inline__ uint64_t __attribute__((always_inline, nodebug))
+  __rbitll(uint64_t t) {
+#if __ARM_32BIT_STATE
+  return (((uint64_t) __builtin_arm_rbit(t)) << 32) |
+    __builtin_arm_rbit(t >> 32);
+#else
+  return __builtin_arm_rbit64(t);
+#endif
+}
+
+static __inline__ unsigned long __attribute__((always_inline, nodebug))
+  __rbitl(unsigned long t) {
+#if __SIZEOF_LONG__ == 4
+  return __rbit(t);
+#else
+  return __rbitll(t);
+#endif
+}
+
 /*
  * 9.4 Saturating intrinsics
  *
  * FIXME: Change guard to their corrosponding __ARM_FEATURE flag when Q flag
  * intrinsics are implemented and the flag is enabled.
  */
 /* 9.4.1 Width-specified saturation intrinsics */
 #if __ARM_32BIT_STATE

test/CodeGen/arm_acle.c

 // AArch32: call void @llvm.arm.hint(i32 0)
 // AArch64: call void @llvm.aarch64.hint(i32 0)
 void test_nop(void) {
   __nop();
 }
 
 /* 9 DATA-PROCESSING INTRINSICS */
 /* 9.2 Miscellaneous data-processing intrinsics */
-// ARM-LABEL: test_rev
-// ARM: call i32 @llvm.bswap.i32(i32 %t)
-uint32_t test_rev(uint32_t t) {
-  return __rev(t);
-}
-
-// ARM-LABEL: test_revl
-// AArch32: call i32 @llvm.bswap.i32(i32 %t)
-// AArch64: call i64 @llvm.bswap.i64(i64 %t)
-long test_revl(long t) {
-  return __revl(t);
-}
-
-// ARM-LABEL: test_revll
-// ARM: call i64 @llvm.bswap.i64(i64 %t)
-uint64_t test_revll(uint64_t t) {
-  return __revll(t);
+// ARM-LABEL: test_ror
+// ARM: lshr
+// ARM: sub
+// ARM: shl
+// ARM: or
+uint32_t test_ror(uint32_t x, uint32_t y) {
+  return __ror(x, y);
+}
+
+// ARM-LABEL: test_rorl
+// ARM: lshr
+// ARM: sub
+// ARM: shl
+// ARM: or
+unsigned long test_rorl(unsigned long x, uint32_t y) {
+  return __rorl(x, y);
+}
+
+// ARM-LABEL: test_rorll
+// ARM: lshr
+// ARM: sub
+// ARM: shl
+// ARM: or
+uint64_t test_rorll(uint64_t x, uint32_t y) {
+  return __rorll(x, y);
 }
 
 // ARM-LABEL: test_clz
 // ARM: call i32 @llvm.ctlz.i32(i32 %t, i1 false)
 uint32_t test_clz(uint32_t t) {
   return __clz(t);
 }
 
 // ARM-LABEL: test_clzl
 // AArch32: call i32 @llvm.ctlz.i32(i32 %t, i1 false)
 // AArch64: call i64 @llvm.ctlz.i64(i64 %t, i1 false)
 long test_clzl(long t) {
   return __clzl(t);
 }
 
 // ARM-LABEL: test_clzll
 // ARM: call i64 @llvm.ctlz.i64(i64 %t, i1 false)
 uint64_t test_clzll(uint64_t t) {
   return __clzll(t);
 }
 
+// ARM-LABEL: test_rev
+// ARM: call i32 @llvm.bswap.i32(i32 %t)
+uint32_t test_rev(uint32_t t) {
+  return __rev(t);
+}
+
+// ARM-LABEL: test_revl
+// AArch32: call i32 @llvm.bswap.i32(i32 %t)
+// AArch64: call i64 @llvm.bswap.i64(i64 %t)
+long test_revl(long t) {
+  return __revl(t);
+}
+
+// ARM-LABEL: test_revll
+// ARM: call i64 @llvm.bswap.i64(i64 %t)
+uint64_t test_revll(uint64_t t) {
+  return __revll(t);
+}
+
+// ARM-LABEL: test_rev16
+// ARM: llvm.bswap
+// ARM: lshr
+// ARM: shl
+// ARM: or
+uint32_t test_rev16(uint32_t t) {
+  return __rev16(t);
+}
+
+// ARM-LABEL: test_rev16l
+// ARM: llvm.bswap
+// ARM: lshr
+// ARM: shl
+// ARM: or
+long test_rev16l(long t) {
+  return __rev16l(t);
+}
+
+// ARM-LABEL: test_rev16ll
+// ARM: llvm.bswap
+// ARM: lshr
+// ARM: shl
+// ARM: or
+uint64_t test_rev16ll(uint64_t t) {
+  return __rev16ll(t);
+}
+
+// ARM-LABEL: test_revsh
+// ARM: call i16 @llvm.bswap.i16(i16 %t)
+int16_t test_revsh(int16_t t) {
+  return __revsh(t);
+}
+
+// ARM-LABEL: test_rbit
+// AArch32: call i32 @llvm.arm.rbit
+// AArch64: call i32 @llvm.aarch64.rbit.i32
+uint32_t test_rbit(uint32_t t) {
+  return __rbit(t);
+}
+
+// ARM-LABEL: test_rbitl
+// AArch32: call i32 @llvm.arm.rbit
+// AArch64: call i64 @llvm.aarch64.rbit.i64
+long test_rbitl(long t) {
+  return __rbitl(t);
+}
+
+// ARM-LABEL: test_rbitll
+// AArch32: call i32 @llvm.arm.rbit
+// AArch32: call i32 @llvm.arm.rbit
+// AArch64: call i64 @llvm.aarch64.rbit.i64
+uint64_t test_rbitll(uint64_t t) {
+  return __rbitll(t);
+}
+
 /* 9.4 Saturating intrinsics */
 #ifdef __ARM_32BIT_STATE
 
 /* 9.4.1 Width-specified saturation intrinsics */
 // AArch32-LABEL: test_ssat
 // AArch32: call i32 @llvm.arm.ssat(i32 %t, i32 1)
 int32_t test_ssat(int32_t t) {
   return __ssat(t, 1);