Add missing breaks to AArch64InstrInfo::is{G,F}PRCopy

[rengolin]

Summary

Silly omission in one case, future-proof in other two. Caught by Coverity.

Tim, just making sure the "silly omission" was actually not intended.

[t.p.northover]

Hi Renato,

I think this one's reasonable. The lack of tests it a bit disturbing, but fine in my opinion (constructing one would be very difficult, with a very fragile result). The change is obviously correct.

Cheers.

Tim.

[rengolin]

Thanks, r214528.

lib/Target/AArch64/AArch64InstrInfo.cpp

             AArch64::GPR64RegClass.contains(DstReg));
   }
   case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
     if (MI->getOperand(1).getReg() == AArch64::XZR) {
       assert(MI->getDesc().getNumOperands() == 4 &&
              MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
       return true;
     }
+    break;
   case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
     if (MI->getOperand(2).getImm() == 0) {
       assert(MI->getDesc().getNumOperands() == 4 &&
              MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
       return true;
     }
+    break;
   }
   return false;
 }
 
 // Return true if this instruction simply renames a general register without
 // modifying bits.
 bool AArch64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
   switch (MI->getOpcode()) {
   default:
     break;
   case TargetOpcode::COPY: {
     // FPR64 copies will by lowered to ORR.16b
     unsigned DstReg = MI->getOperand(0).getReg();
     return (AArch64::FPR64RegClass.contains(DstReg) ||
             AArch64::FPR128RegClass.contains(DstReg));
   }
   case AArch64::ORRv16i8:
     if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
       assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
              "invalid ORRv16i8 operands");
       return true;
     }
+    break;
   }
   return false;
 }
 
 unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
                                                int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: