[SKX] Enabling SKX target (Skylake server chip) in clang

[rob.khasanov]

Summary

a) add SKX support to Clang driver;
b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests

Patch by Zinovy Nis <[e-mail]>

[rob.khasanov]

ping

[delena]

LGTM

[bkramer]

This landed way back in rL214306.

include/clang/Driver/Options.td

 def mno_ssse3 : Flag<["-"], "mno-ssse3">, Group<m_x86_Features_Group>;
 def mno_aes : Flag<["-"], "mno-aes">, Group<m_x86_Features_Group>;
 def mno_avx : Flag<["-"], "mno-avx">, Group<m_x86_Features_Group>;
 def mno_avx2 : Flag<["-"], "mno-avx2">, Group<m_x86_Features_Group>;
 def mno_avx512f : Flag<["-"], "mno-avx512f">, Group<m_x86_Features_Group>;
 def mno_avx512cd : Flag<["-"], "mno-avx512cd">, Group<m_x86_Features_Group>;
 def mno_avx512er : Flag<["-"], "mno-avx512er">, Group<m_x86_Features_Group>;
 def mno_avx512pf : Flag<["-"], "mno-avx512pf">, Group<m_x86_Features_Group>;
+def mno_avx512dq : Flag<["-"], "mno-avx512dq">, Group<m_x86_Features_Group>;
+def mno_avx512bw : Flag<["-"], "mno-avx512bw">, Group<m_x86_Features_Group>;
+def mno_avx512vl : Flag<["-"], "mno-avx512vl">, Group<m_x86_Features_Group>;
 def mno_pclmul : Flag<["-"], "mno-pclmul">, Group<m_x86_Features_Group>;
 def mno_lzcnt : Flag<["-"], "mno-lzcnt">, Group<m_x86_Features_Group>;
 def mno_rdrnd : Flag<["-"], "mno-rdrnd">, Group<m_x86_Features_Group>;
 def mno_bmi : Flag<["-"], "mno-bmi">, Group<m_x86_Features_Group>;
 def mno_bmi2 : Flag<["-"], "mno-bmi2">, Group<m_x86_Features_Group>;
 def mno_popcnt : Flag<["-"], "mno-popcnt">, Group<m_x86_Features_Group>;
 def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
 def mno_fma4 : Flag<["-"], "mno-fma4">, Group<m_x86_Features_Group>;

 def mssse3 : Flag<["-"], "mssse3">, Group<m_x86_Features_Group>;
 def maes : Flag<["-"], "maes">, Group<m_x86_Features_Group>;
 def mavx : Flag<["-"], "mavx">, Group<m_x86_Features_Group>;
 def mavx2 : Flag<["-"], "mavx2">, Group<m_x86_Features_Group>;
 def mavx512f : Flag<["-"], "mavx512f">, Group<m_x86_Features_Group>;
 def mavx512cd : Flag<["-"], "mavx512cd">, Group<m_x86_Features_Group>;
 def mavx512er : Flag<["-"], "mavx512er">, Group<m_x86_Features_Group>;
 def mavx512pf : Flag<["-"], "mavx512pf">, Group<m_x86_Features_Group>;
+def mavx512dq : Flag<["-"], "mavx512dq">, Group<m_x86_Features_Group>;
+def mavx512bw : Flag<["-"], "mavx512bw">, Group<m_x86_Features_Group>;
+def mavx512vl : Flag<["-"], "mavx512vl">, Group<m_x86_Features_Group>;
 def mpclmul : Flag<["-"], "mpclmul">, Group<m_x86_Features_Group>;
 def mlzcnt : Flag<["-"], "mlzcnt">, Group<m_x86_Features_Group>;
 def mrdrnd : Flag<["-"], "mrdrnd">, Group<m_x86_Features_Group>;
 def mbmi : Flag<["-"], "mbmi">, Group<m_x86_Features_Group>;
 def mbmi2 : Flag<["-"], "mbmi2">, Group<m_x86_Features_Group>;
 def mpopcnt : Flag<["-"], "mpopcnt">, Group<m_x86_Features_Group>;
 def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
 def mfma4 : Flag<["-"], "mfma4">, Group<m_x86_Features_Group>;

lib/Basic/Targets.cpp

class X86TargetInfo : public TargetInfo {
   bool HasBMI2;
   bool HasPOPCNT;
   bool HasRTM;
   bool HasPRFCHW;
   bool HasRDSEED;
   bool HasTBM;
   bool HasFMA;
   bool HasF16C;
-  bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
+  bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL;
   bool HasSHA;
   bool HasCX16;
 
   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
   ///
   /// Each enumeration represents a particular CPU supported by Clang. These
   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
   enum CPUKind {
enum CPUKind {
     CK_CoreAVXi,
     CK_CoreAVX2,
     //@}
 
     /// \name Knights Landing
     /// Knights Landing processor.
     CK_KNL,
 
+    /// \name Skylake Server
+    /// Skylake server processor.
+    CK_SKX,
+
     /// \name K6
     /// K6 architecture processors.
     //@{
     CK_K6,
     CK_K6_2,
     CK_K6_3,
     //@}
 

 
 public:
   X86TargetInfo(const llvm::Triple &Triple)
       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
         HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
-        HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
+        HasAVX512PF(false), HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
+        HasSHA(false), HasCX16(false), CPU(CK_Generic),
         FPMath(FP_Default) {
     BigEndian = false;
     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
   }
   unsigned getFloatEvalMethod() const override {
     // X87 evaluates with 80 bits "long double" precision.
     return SSELevel == NoSSE ? 2 : 0;
   }
CPU = llvm::StringSwitch<CPUKind>(Name)
       .Case("penryn", CK_Penryn)
       .Case("atom", CK_Atom)
       .Case("slm", CK_Silvermont)
       .Case("corei7", CK_Corei7)
       .Case("corei7-avx", CK_Corei7AVX)
       .Case("core-avx-i", CK_CoreAVXi)
       .Case("core-avx2", CK_CoreAVX2)
       .Case("knl", CK_KNL)
+      .Case("skx", CK_SKX)
       .Case("k6", CK_K6)
       .Case("k6-2", CK_K6_2)
       .Case("k6-3", CK_K6_3)
       .Case("athlon", CK_Athlon)
       .Case("athlon-tbird", CK_AthlonThunderbird)
       .Case("athlon-4", CK_Athlon4)
       .Case("athlon-xp", CK_AthlonXP)
       .Case("athlon-mp", CK_AthlonMP)
bool setCPU(const std::string &Name) override {
     case CK_Penryn:
     case CK_Atom:
     case CK_Silvermont:
     case CK_Corei7:
     case CK_Corei7AVX:
     case CK_CoreAVXi:
     case CK_CoreAVX2:
     case CK_KNL:
+    case CK_SKX:
     case CK_Athlon64:
     case CK_Athlon64SSE3:
     case CK_AthlonFX:
     case CK_K8:
     case CK_K8SSE3:
     case CK_Opteron:
     case CK_OpteronSSE3:
     case CK_AMDFAM10:
case CK_KNL:
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "rdrnd", true);
     setFeatureEnabledImpl(Features, "f16c", true);
     setFeatureEnabledImpl(Features, "bmi", true);
     setFeatureEnabledImpl(Features, "bmi2", true);
     setFeatureEnabledImpl(Features, "rtm", true);
     setFeatureEnabledImpl(Features, "fma", true);
     break;
+  case CK_SKX:
+    setFeatureEnabledImpl(Features, "avx512f", true);
+    setFeatureEnabledImpl(Features, "avx512cd", true);
+    setFeatureEnabledImpl(Features, "avx512dq", true);
+    setFeatureEnabledImpl(Features, "avx512bw", true);
+    setFeatureEnabledImpl(Features, "avx512vl", true);
+    setFeatureEnabledImpl(Features, "aes", true);
+    setFeatureEnabledImpl(Features, "pclmul", true);
+    setFeatureEnabledImpl(Features, "lzcnt", true);
+    setFeatureEnabledImpl(Features, "rdrnd", true);
+    setFeatureEnabledImpl(Features, "f16c", true);
+    setFeatureEnabledImpl(Features, "bmi", true);
+    setFeatureEnabledImpl(Features, "bmi2", true);
+    setFeatureEnabledImpl(Features, "rtm", true);
+    setFeatureEnabledImpl(Features, "fma", true);
+    break;
   case CK_K6:
   case CK_WinChipC6:
     setFeatureEnabledImpl(Features, "mmx", true);
     break;
   case CK_K6_2:
   case CK_K6_3:
   case CK_WinChip2:
   case CK_C3:
void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
   case SSE42:
     Features["sse4.2"] = false;
   case AVX:
     Features["fma"] = Features["avx"] = Features["f16c"] = false;
     setXOPLevel(Features, FMA4, false);
   case AVX2:
     Features["avx2"] = false;
   case AVX512F:
-    Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
-      Features["avx512pf"] = false;
+    Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] =
+    Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false;
   }
 }
 
 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
                                 MMX3DNowEnum Level, bool Enabled) {
   if (Enabled) {
     switch (Level) {
     case AMD3DNowAthlon:
if (Name == "mmx") {
     if (Enabled)
       setSSELevel(Features, SSE2, Enabled);
   } else if (Name == "avx") {
     setSSELevel(Features, AVX, Enabled);
   } else if (Name == "avx2") {
     setSSELevel(Features, AVX2, Enabled);
   } else if (Name == "avx512f") {
     setSSELevel(Features, AVX512F, Enabled);
-  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
+  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
+          || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
     if (Enabled)
       setSSELevel(Features, AVX512F, Enabled);
   } else if (Name == "fma") {
     if (Enabled)
       setSSELevel(Features, AVX, Enabled);
   } else if (Name == "fma4") {
     setXOPLevel(Features, FMA4, Enabled);
   } else if (Name == "xop") {
if (Feature == "avx512er") {
       continue;
     }
 
     if (Feature == "avx512pf") {
       HasAVX512PF = true;
       continue;
     }
 
+    if (Feature == "avx512dq") {
+      HasAVX512DQ = true;
+      continue;
+    }
+
+    if (Feature == "avx512bw") {
+      HasAVX512BW = true;
+      continue;
+    }
+
+    if (Feature == "avx512vl") {
+      HasAVX512VL = true;
+      continue;
+    }
+
     if (Feature == "sha") {
       HasSHA = true;
       continue;
     }
 
     if (Feature == "cx16") {
       HasCX16 = true;
       continue;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_Corei7AVX:
   case CK_CoreAVXi:
   case CK_CoreAVX2:
     defineCPUMacros(Builder, "corei7");
     break;
   case CK_KNL:
     defineCPUMacros(Builder, "knl");
     break;
+  case CK_SKX:
+    defineCPUMacros(Builder, "skx");
+    break;
   case CK_K6_2:
     Builder.defineMacro("__k6_2__");
     Builder.defineMacro("__tune_k6_2__");
     // Fallthrough
   case CK_K6_3:
     if (CPU != CK_K6_2) {  // In case of fallthrough
       // FIXME: GCC may be enabling these in cases where some other k6
       // architecture is specified but -m3dnow is explicitly provided. The
if (HasF16C)
     Builder.defineMacro("__F16C__");
 
   if (HasAVX512CD)
     Builder.defineMacro("__AVX512CD__");
   if (HasAVX512ER)
     Builder.defineMacro("__AVX512ER__");
   if (HasAVX512PF)
     Builder.defineMacro("__AVX512PF__");
+  if (HasAVX512DQ)
+    Builder.defineMacro("__AVX512DQ__");
+  if (HasAVX512BW)
+    Builder.defineMacro("__AVX512BW__");
+  if (HasAVX512VL)
+    Builder.defineMacro("__AVX512VL__");
 
   if (HasSHA)
     Builder.defineMacro("__SHA__");
 
   if (HasCX16)
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
 
   // Each case falls through to the previous one here.
bool X86TargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("aes", HasAES)
       .Case("avx", SSELevel >= AVX)
       .Case("avx2", SSELevel >= AVX2)
       .Case("avx512f", SSELevel >= AVX512F)
       .Case("avx512cd", HasAVX512CD)
       .Case("avx512er", HasAVX512ER)
       .Case("avx512pf", HasAVX512PF)
+      .Case("avx512dq", HasAVX512DQ)
+      .Case("avx512bw", HasAVX512BW)
+      .Case("avx512vl", HasAVX512VL)
       .Case("bmi", HasBMI)
       .Case("bmi2", HasBMI2)
       .Case("cx16", HasCX16)
       .Case("f16c", HasF16C)
       .Case("fma", HasFMA)
       .Case("fma4", XOPLevel >= FMA4)
       .Case("tbm", HasTBM)
       .Case("lzcnt", HasLZCNT)

test/Preprocessor/predefined-arch-macros.c

 // CHECK_KNL_M32: #define __SSE__ 1
 // CHECK_KNL_M32: #define __SSSE3__ 1
 // CHECK_KNL_M32: #define __i386 1
 // CHECK_KNL_M32: #define __i386__ 1
 // CHECK_KNL_M32: #define __knl 1
 // CHECK_KNL_M32: #define __knl__ 1
 // CHECK_KNL_M32: #define __tune_knl__ 1
 // CHECK_KNL_M32: #define i386 1
+
 // RUN: %clang -march=knl -m64 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_KNL_M64
 // CHECK_KNL_M64: #define __AES__ 1
 // CHECK_KNL_M64: #define __AVX2__ 1
 // CHECK_KNL_M64: #define __AVX512CD__ 1
 // CHECK_KNL_M64: #define __AVX512ER__ 1
 // CHECK_KNL_M64: #define __AVX512F__ 1

 // CHECK_KNL_M64: #define __amd64 1
 // CHECK_KNL_M64: #define __amd64__ 1
 // CHECK_KNL_M64: #define __knl 1
 // CHECK_KNL_M64: #define __knl__ 1
 // CHECK_KNL_M64: #define __tune_knl__ 1
 // CHECK_KNL_M64: #define __x86_64 1
 // CHECK_KNL_M64: #define __x86_64__ 1
 //
+// RUN: %clang -march=skx -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck %s -check-prefix=CHECK_SKX_M32
+// CHECK_SKX_M32: #define __AES__ 1
+// CHECK_SKX_M32: #define __AVX2__ 1
+// CHECK_SKX_M32: #define __AVX512BW__ 1
+// CHECK_SKX_M32: #define __AVX512CD__ 1
+// CHECK_SKX_M32: #define __AVX512DQ__ 1
+// CHECK_SKX_M32: #define __AVX512F__ 1
+// CHECK_SKX_M32: #define __AVX512VL__ 1
+// CHECK_SKX_M32: #define __AVX__ 1
+// CHECK_SKX_M32: #define __BMI2__ 1
+// CHECK_SKX_M32: #define __BMI__ 1
+// CHECK_SKX_M32: #define __F16C__ 1
+// CHECK_SKX_M32: #define __FMA__ 1
+// CHECK_SKX_M32: #define __LZCNT__ 1
+// CHECK_SKX_M32: #define __MMX__ 1
+// CHECK_SKX_M32: #define __PCLMUL__ 1
+// CHECK_SKX_M32: #define __POPCNT__ 1
+// CHECK_SKX_M32: #define __RDRND__ 1
+// CHECK_SKX_M32: #define __RTM__ 1
+// CHECK_SKX_M32: #define __SSE2__ 1
+// CHECK_SKX_M32: #define __SSE3__ 1
+// CHECK_SKX_M32: #define __SSE4_1__ 1
+// CHECK_SKX_M32: #define __SSE4_2__ 1
+// CHECK_SKX_M32: #define __SSE__ 1
+// CHECK_SKX_M32: #define __SSSE3__ 1
+// CHECK_SKX_M32: #define __i386 1
+// CHECK_SKX_M32: #define __i386__ 1
+// CHECK_SKX_M32: #define __skx 1
+// CHECK_SKX_M32: #define __skx__ 1
+// CHECK_SKX_M32: #define __tune_skx__ 1
+// CHECK_SKX_M32: #define i386 1
+
+// RUN: %clang -march=skx -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck %s -check-prefix=CHECK_SKX_M64
+// CHECK_SKX_M64: #define __AES__ 1
+// CHECK_SKX_M64: #define __AVX2__ 1
+// CHECK_SKX_M64: #define __AVX512BW__ 1
+// CHECK_SKX_M64: #define __AVX512CD__ 1
+// CHECK_SKX_M64: #define __AVX512DQ__ 1
+// CHECK_SKX_M64: #define __AVX512F__ 1
+// CHECK_SKX_M64: #define __AVX512VL__ 1
+// CHECK_SKX_M64: #define __AVX__ 1
+// CHECK_SKX_M64: #define __BMI2__ 1
+// CHECK_SKX_M64: #define __BMI__ 1
+// CHECK_SKX_M64: #define __F16C__ 1
+// CHECK_SKX_M64: #define __FMA__ 1
+// CHECK_SKX_M64: #define __LZCNT__ 1
+// CHECK_SKX_M64: #define __MMX__ 1
+// CHECK_SKX_M64: #define __PCLMUL__ 1
+// CHECK_SKX_M64: #define __POPCNT__ 1
+// CHECK_SKX_M64: #define __RDRND__ 1
+// CHECK_SKX_M64: #define __RTM__ 1
+// CHECK_SKX_M64: #define __SSE2_MATH__ 1
+// CHECK_SKX_M64: #define __SSE2__ 1
+// CHECK_SKX_M64: #define __SSE3__ 1
+// CHECK_SKX_M64: #define __SSE4_1__ 1
+// CHECK_SKX_M64: #define __SSE4_2__ 1
+// CHECK_SKX_M64: #define __SSE_MATH__ 1
+// CHECK_SKX_M64: #define __SSE__ 1
+// CHECK_SKX_M64: #define __SSSE3__ 1
+// CHECK_SKX_M64: #define __amd64 1
+// CHECK_SKX_M64: #define __amd64__ 1
+// CHECK_SKX_M64: #define __skx 1
+// CHECK_SKX_M64: #define __skx__ 1
+// CHECK_SKX_M64: #define __tune_skx__ 1
+// CHECK_SKX_M64: #define __x86_64 1
+// CHECK_SKX_M64: #define __x86_64__ 1
+//
 // RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_ATOM_M32
 // CHECK_ATOM_M32: #define __MMX__ 1
 // CHECK_ATOM_M32: #define __SSE2__ 1
 // CHECK_ATOM_M32: #define __SSE3__ 1
 // CHECK_ATOM_M32: #define __SSE__ 1
 // CHECK_ATOM_M32: #define __SSSE3__ 1

test/Preprocessor/x86_target_features.c

 // AVX512PF: #define __SSE2__ 1
 // AVX512PF: #define __SSE3__ 1
 // AVX512PF: #define __SSE4_1__ 1
 // AVX512PF: #define __SSE4_2__ 1
 // AVX512PF: #define __SSE_MATH__ 1
 // AVX512PF: #define __SSE__ 1
 // AVX512PF: #define __SSSE3__ 1
 
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512dq -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512DQ %s
+
+// AVX512DQ: #define __AVX2__ 1
+// AVX512DQ: #define __AVX512DQ__ 1
+// AVX512DQ: #define __AVX512F__ 1
+// AVX512DQ: #define __AVX__ 1
+// AVX512DQ: #define __SSE2_MATH__ 1
+// AVX512DQ: #define __SSE2__ 1
+// AVX512DQ: #define __SSE3__ 1
+// AVX512DQ: #define __SSE4_1__ 1
+// AVX512DQ: #define __SSE4_2__ 1
+// AVX512DQ: #define __SSE_MATH__ 1
+// AVX512DQ: #define __SSE__ 1
+// AVX512DQ: #define __SSSE3__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bw -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512BW %s
+
+// AVX512BW: #define __AVX2__ 1
+// AVX512BW: #define __AVX512BW__ 1
+// AVX512BW: #define __AVX512F__ 1
+// AVX512BW: #define __AVX__ 1
+// AVX512BW: #define __SSE2_MATH__ 1
+// AVX512BW: #define __SSE2__ 1
+// AVX512BW: #define __SSE3__ 1
+// AVX512BW: #define __SSE4_1__ 1
+// AVX512BW: #define __SSE4_2__ 1
+// AVX512BW: #define __SSE_MATH__ 1
+// AVX512BW: #define __SSE__ 1
+// AVX512BW: #define __SSSE3__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vl -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512VL %s
+
+// AVX512VL: #define __AVX2__ 1
+// AVX512VL: #define __AVX512F__ 1
+// AVX512VL: #define __AVX512VL__ 1
+// AVX512VL: #define __AVX__ 1
+// AVX512VL: #define __SSE2_MATH__ 1
+// AVX512VL: #define __SSE2__ 1
+// AVX512VL: #define __SSE3__ 1
+// AVX512VL: #define __SSE4_1__ 1
+// AVX512VL: #define __SSE4_2__ 1
+// AVX512VL: #define __SSE_MATH__ 1
+// AVX512VL: #define __SSE__ 1
+// AVX512VL: #define __SSSE3__ 1
+
 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512pf -mno-avx512f -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512F2 %s
 
 // AVX512F2: #define __AVX2__ 1
 // AVX512F2-NOT: #define __AVX512F__ 1
 // AVX512F2-NOT: #define __AVX512PF__ 1
 // AVX512F2: #define __AVX__ 1
 // AVX512F2: #define __SSE2_MATH__ 1
 // AVX512F2: #define __SSE2__ 1