ARM: Implement __builtin_arm_nop intrinsic

[kongyi]

Summary

This patch implements __builtin_arm_nop intrinsic for AArch32 and AArch64, which generates hint 0x0, the alias of NOP instruction.

This intrinsic is necessary to implement ACLE __nop intrinsic.

[t.p.northover]

Hi Yi,

The code looks reasonable, but I don't think there's any real reason to separate NOP from the other hints in BuiltinsARM.def.

Cheers.

Tim.

[kongyi]

Closed by commit rL212947 (authored by @kongyi).

cfe/trunk/include/clang/Basic/BuiltinsAArch64.def

 BUILTIN(__builtin_arm_stlex, "i.", "t")
 BUILTIN(__builtin_arm_clrex, "v", "")
 
 // Bit manipulation
 BUILTIN(__builtin_arm_rbit, "UiUi", "nc")
 BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc")
 
 // HINT
+BUILTIN(__builtin_arm_nop, "v", "")
 BUILTIN(__builtin_arm_yield, "v", "")
 BUILTIN(__builtin_arm_wfe, "v", "")
 BUILTIN(__builtin_arm_wfi, "v", "")
 BUILTIN(__builtin_arm_sev, "v", "")
 BUILTIN(__builtin_arm_sevl, "v", "")
 
 // CRC32
 BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc")

cfe/trunk/include/clang/Basic/BuiltinsARM.def

 BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc")
 BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
 BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
 BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
 BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
 BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
 
 // HINT
+BUILTIN(__builtin_arm_nop, "v", "")
 BUILTIN(__builtin_arm_yield, "v", "")
 BUILTIN(__builtin_arm_wfe, "v", "")
 BUILTIN(__builtin_arm_wfi, "v", "")
 BUILTIN(__builtin_arm_sev, "v", "")
 BUILTIN(__builtin_arm_sevl, "v", "")
 
 // Data barrier
 BUILTIN(__builtin_arm_dmb, "vUi", "nc")

cfe/trunk/lib/CodeGen/CGBuiltin.cpp

static Value *packTBLDVectorList(CodeGenFunction &CGF, ArrayRef<Value *> Ops,
   return CGF.EmitNeonCall(TblF, TblOps, Name);
 }
 
 Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
                                            const CallExpr *E) {
   unsigned HintID = static_cast<unsigned>(-1);
   switch (BuiltinID) {
   default: break;
+  case ARM::BI__builtin_arm_nop:
+    HintID = 0;
+    break;
   case ARM::BI__builtin_arm_yield:
   case ARM::BI__yield:
     HintID = 1;
     break;
   case ARM::BI__builtin_arm_wfe:
   case ARM::BI__wfe:
     HintID = 2;
     break;
emitVectorWrappedScalar16Intrinsic(unsigned Int, SmallVectorImpl<Value*> &Ops,
   return Builder.CreateExtractElement(V, CI, "lane0");
 }
 
 Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
                                                const CallExpr *E) {
   unsigned HintID = static_cast<unsigned>(-1);
   switch (BuiltinID) {
   default: break;
+  case AArch64::BI__builtin_arm_nop:
+    HintID = 0;
+    break;
   case AArch64::BI__builtin_arm_yield:
     HintID = 1;
     break;
   case AArch64::BI__builtin_arm_wfe:
     HintID = 2;
     break;
   case AArch64::BI__builtin_arm_wfi:
     HintID = 3;

cfe/trunk/test/CodeGen/builtins-arm.c

 
 void test_eh_return_data_regno()
 {
   volatile int res;
   res = __builtin_eh_return_data_regno(0);  // CHECK: store volatile i32 0
   res = __builtin_eh_return_data_regno(1);  // CHECK: store volatile i32 1
 }
 
+void nop() {
+  __builtin_arm_nop();
+}
+
+// CHECK: call {{.*}} @llvm.arm.hint(i32 0)
+
 void yield() {
   __builtin_arm_yield();
 }
 
 // CHECK: call {{.*}} @llvm.arm.hint(i32 1)
 
 void wfe() {
   __builtin_arm_wfe();

cfe/trunk/test/CodeGen/builtins-arm64.c

 }
 
 // CHECK: call {{.*}} @llvm.aarch64.rbit.i64(i64 %a)
 unsigned long long rbit64(unsigned long long a) {
   return __builtin_arm_rbit64(a);
 }
 
 void hints() {
+  __builtin_arm_nop();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)
   __builtin_arm_yield();  //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)
   __builtin_arm_wfe();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)
   __builtin_arm_wfi();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3)
   __builtin_arm_sev();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4)
   __builtin_arm_sevl();   //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5)
 }