ARM: Fix TPsoft for Thumb mode

[cpirker]

Summary

Hi all,

The use of thread local storage (TLS) requires the thread pointer to access thread specific data.
LLVM generates subroutine calls to a ABI specified function "__eabi_read_tp" to get hold of the thread pointer.
Unfortunately, LLVM uses the ARM coding of the branch long instructions in Thumb mode, instead of the Thumb encoding.
This patch enables the correct encoding for the Thumb branch long instruction.

Please review, thanks,
Christian

[rengolin]

lib/Target/ARM/ARMExpandPseudoInsts.cpp

934

Is this to cope with IT blocks?

lib/Target/ARM/ARMInstrInfo.td

5118

Is this really necessary? I'd have thought that everything in here is ARM anyway, plus the instruction is different (tTPsoft instead of TPsoft).

[cpirker]

lib/Target/ARM/ARMExpandPseudoInsts.cpp

934

Yes, ARMCC::AL marks an unconditional branch.

lib/Target/ARM/ARMInstrInfo.td

5118

This pattern matches both in ARM and Thumb mode.
This predicate makes LLVM to match the tTPsoft pattern in Thumb mode.
I can change "PseudoInst" to "ARMPseudoInst" so that the predicate can be omitted, what you think?

[rengolin]

With the ARMPseudoInst change, LGTM.

Thanks!
--renato

lib/Target/ARM/ARMInstrInfo.td

5118

I can change "PseudoInst" to "ARMPseudoInst" so that the predicate can be omitted, what you think?

I think it's better, since the Thumb version use tPseudoInst.

[cpirker]

Hi Renato,

I updated the patch and committed as rL211601.

Thanks,
Christian

lib/Target/ARM/ARMExpandPseudoInsts.cpp

case ARM::RRX: {
                        .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
         .addReg(0);
       TransferImpOps(MI, MIB, MIB);
       MI.eraseFromParent();
       return true;
     }
     case ARM::tTPsoft:
     case ARM::TPsoft: {
-      MachineInstrBuilder MIB =
-        BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
+      MachineInstrBuilder MIB;
+      if (Opcode == ARM::tTPsoft)
+        MIB =  BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                       TII->get( ARM::tBL))
+               .addImm((unsigned)ARMCC::AL).addReg(0)
+               .addExternalSymbol("__aeabi_read_tp", 0);
+      else
+        MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                      TII->get( ARM::BL))
                .addExternalSymbol("__aeabi_read_tp", 0);
 
       MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
       TransferImpOps(MI, MIB, MIB);
       MI.eraseFromParent();
       return true;
     }
     case ARM::tLDRpci_pic:
     case ARM::t2LDRpci_pic: {

lib/Target/ARM/ARMInstrInfo.td

 
 //===----------------------------------------------------------------------===//
 // TLS Instructions
 //
 
 // __aeabi_read_tp preserves the registers r1-r3.
 // This is a pseudo inst so that we can get the encoding right,
 // complete with fixup for the aeabi_read_tp function.
+// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
+// is defined in "ARMInstrThumb.td".
+let Predicates = [IsARM] in {
   let isCall = 1,
     Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
     def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
                  [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
   }
+}
 
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
 //   eh_sjlj_setjmp() is an instruction sequence to store the return
 //   address and save #0 in R0 for the non-longjmp case.
 //   Since by its nature we may be coming from some other function to get
 //   here, and we're using the stack frame for the containing function to
 //   save/restore registers, we can't keep anything live in regs across

test/CodeGen/Thumb2/tpsoft.ll

+; RUN: llc  %s -mtriple=thumbv7-linux-gnueabi -o - | \
+; RUN:    FileCheck  -check-prefix=ELFASM %s
+; RUN: llc  %s -mtriple=thumbebv7-linux-gnueabi -o - | \
+; RUN:    FileCheck  -check-prefix=ELFASM %s
+; RUN: llc  %s -mtriple=thumbv7-linux-gnueabi -filetype=obj -o - | \
+; RUN:    llvm-readobj -s -sd | FileCheck  -check-prefix=ELFOBJ -check-prefix=ELFOBJ-LE %s
+; RUN: llc  %s -mtriple=thumbebv7-linux-gnueabi -filetype=obj -o - | \
+; RUN:    llvm-readobj -s -sd | FileCheck  -check-prefix=ELFOBJ -check-prefix=ELFOBJ-BE %s
+
+;; Make sure that bl __aeabi_read_tp is materialized and fixed up correctly
+;; in the obj case.
+
+@i = external thread_local global i32
+@a = external global i8
+@b = external global [10 x i8]
+
+define arm_aapcs_vfpcc i32 @main() nounwind {
+entry:
+  %0 = load i32* @i, align 4
+  switch i32 %0, label %bb2 [
+    i32 12, label %bb
+    i32 13, label %bb1
+  ]
+
+bb:                                               ; preds = %entry
+  %1 = tail call arm_aapcs_vfpcc  i32 @foo(i8* @a) nounwind
+  ret i32 %1
+; ELFASM:         bl  __aeabi_read_tp
+
+
+; ELFOBJ:      Sections [
+; ELFOBJ:        Section {
+; ELFOBJ:          Name: .text
+; ELFOBJ-LE:          SectionData (
+;;;                  BL __aeabi_read_tp is ---------+
+;;;                                                 V
+; ELFOBJ-LE-NEXT:     0000: 2DE90048 0E487844 0168FFF7 FEFF4058
+; ELFOBJ-BE:          SectionData (
+;;;                  BL __aeabi_read_tp is ---------+
+;;;                                                 V
+; ELFOBJ-BE-NEXT:     0000: E92D4800 480E4478 6801F7FF FFFE5840
+
+
+bb1:                                              ; preds = %entry
+  %2 = tail call arm_aapcs_vfpcc  i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
+  ret i32 %2
+
+bb2:                                              ; preds = %entry
+  ret i32 -1
+}
+
+declare arm_aapcs_vfpcc i32 @foo(i8*)
+
+declare arm_aapcs_vfpcc i32 @bar(i32*)