[ARM64] Improve load/store diagnostics and forbid 32-bit register addresses

[bsmith]

Summary

This patch somewhat improves load/store diagnostics (as best as possible given it's implementation which Tim is looking at changing), particularly for literal loads and disallowing 32-bit register addresses.

As with my previous patches, there is no testcase for this as it is part of the merge of MC/AArch64/basic-a64-diagnostics.s.

[t.p.northover]

Hi Bradley,

This looks reasonable.

Cheers.

Tim.

lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp

 
 /// parseMemory - Parse a memory operand for a basic load/store instruction.
 bool ARM64AsmParser::parseMemory(OperandVector &Operands) {
   assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a Left Bracket");
   SMLoc S = getLoc();
   Parser.Lex(); // Eat left bracket token.
 
   const AsmToken &BaseRegTok = Parser.getTok();
+  SMLoc BaseRegLoc = BaseRegTok.getLoc();
   if (BaseRegTok.isNot(AsmToken::Identifier))
-    return Error(BaseRegTok.getLoc(), "register expected");
+    return Error(BaseRegLoc, "register expected");
 
   int64_t Reg = tryParseRegister();
   if (Reg == -1)
-    return Error(BaseRegTok.getLoc(), "register expected");
+    return Error(BaseRegLoc, "register expected");
+
+  if (!ARM64MCRegisterClasses[ARM64::GPR64spRegClassID].contains(Reg))
+    return Error(BaseRegLoc, "invalid operand for instruction");
 
   // If there is an offset expression, parse it.
   const MCExpr *OffsetExpr = nullptr;
   SMLoc OffsetLoc;
   if (Parser.getTok().is(AsmToken::Comma)) {
     Parser.Lex(); // Eat the comma.
     OffsetLoc = getLoc();
 
if (Operands.size() == ErrorInfo + 1 &&
         !((ARM64Operand *)Operands[ErrorInfo])->isImm() &&
         !Tok.startswith("stur") && !Tok.startswith("ldur")) {
       // FIXME: Here we use a vague diagnostic for memory operand in many
       // instructions of various formats. This diagnostic can be more accurate
       // if splitting memory operand into many smaller operands to help
       // diagnose.
       MatchResult = Match_InvalidMemoryIndexed;
     }
+    else if(Operands.size() == 3 && Operands.size() == ErrorInfo + 1 &&
+            ((ARM64Operand *)Operands[ErrorInfo])->isImm()) {
+      MatchResult = Match_InvalidLabel;
+    }
     SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
     if (ErrorLoc == SMLoc())
       ErrorLoc = IDLoc;
     return showMatchError(ErrorLoc, MatchResult);
   }
   case Match_InvalidMemoryIndexed32:
   case Match_InvalidMemoryIndexed64:
   case Match_InvalidMemoryIndexed128:
     // If there is a '!' after the memory operand that failed, we really
     // want the diagnostic for the pre-indexed instruction variant instead.
     if (Operands.size() > ErrorInfo + 1 &&
         ((ARM64Operand *)Operands[ErrorInfo + 1])->isTokenEqual("!"))
       MatchResult = Match_InvalidMemoryIndexedSImm9;
   // FALL THROUGH
   case Match_InvalidCondCode:
   case Match_AddSubRegExtendSmall:
   case Match_AddSubRegExtendLarge:
   case Match_AddSubSecondSource:
   case Match_LogicalSecondSource:
   case Match_AddSubRegShift32:
   case Match_AddSubRegShift64:
   case Match_InvalidMovImm32Shift:
   case Match_InvalidMovImm64Shift:
   case Match_InvalidFPImm:
+  case Match_InvalidMemoryIndexed:
   case Match_InvalidMemoryIndexed8:
   case Match_InvalidMemoryIndexed16:
   case Match_InvalidMemoryIndexed32SImm7:
   case Match_InvalidMemoryIndexed64SImm7:
   case Match_InvalidMemoryIndexed128SImm7:
   case Match_InvalidImm0_7:
   case Match_InvalidImm0_15:
   case Match_InvalidImm0_31:

test/MC/ARM64/diags.s

 ; CHECK-ERRORS:         ldr x0, [x0, #804]
 ; CHECK-ERRORS:                 ^
 ; CHECK-ERRORS: error: invalid offset in memory address.
 ; CHECK-ERRORS:         ldr w0, [x0, #802]
 ; CHECK-ERRORS:                 ^
 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
 ; CHECK-ERRORS:         ldr x0, [x0, #804]!
 ; CHECK-ERRORS:                 ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
 ; CHECK-ERRORS:         ldr w0, [w0, #301]!
-; CHECK-ERRORS:                 ^
+; CHECK-ERRORS:                  ^
 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
 ; CHECK-ERRORS:         ldr x0, [x0], #804
 ; CHECK-ERRORS:                       ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
 ; CHECK-ERRORS:         ldr w0, [w0], #301
-; CHECK-ERRORS:                       ^
+; CHECK-ERRORS:                  ^
 ; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
 ; CHECK-ERRORS:         ldp w3, w4, [x5, #11]!
 ; CHECK-ERRORS:                     ^
 ; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
 ; CHECK-ERRORS:         ldp x3, x4, [x5, #12]!
 ; CHECK-ERRORS:                     ^
 ; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
 ; CHECK-ERRORS:         ldp q3, q4, [x5, #12]!