[ARM64] Add diagnostics for bitfield extract/insert instructions

[bsmith]

Summary

Patch to add diagnostics for bitfield extract/insert instructions.

Unfortunately, since ARM64 models all these instructions as aliases, the checks need to be done at the time the alias is seen rather then during instruction validation as AArch4 does it, hence we need to extend some of the hacks a little. It is up for debate whether the bitfield instructions should be implemented in this manner, or whether they should be modeled as separate instructions. (Although perhaps for a different patch).

As with my previous patches, there is no testcase for this as it is part of the merge of MC/AArch64/basic-a64-diagnostics.s.

[t.p.northover]

Hi Bradley,

This looks reasonable to me, at least for now.

As you say, there might be better ways to handle the bitfield instructions overall. Though I'm still not convinced AArch64 has this one any better. There are lots of pseudo-instructions there, which amount to something not much better.

Any cunning ideas you have...

Tim.

lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp

if (Tok == "bfi" || Tok == "sbfiz" || Tok == "ubfiz") {
       if (Op1->isReg() && Op3->isImm() && Op4->isImm()) {
         const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3->getImm());
         const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4->getImm());
 
         if (Op3CE && Op4CE) {
           uint64_t Op3Val = Op3CE->getValue();
           uint64_t Op4Val = Op4CE->getValue();
 
+          uint64_t RegWidth = 0;
+          if (ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
+              Op1->getReg()))
+            RegWidth = 64;
+          else
+            RegWidth = 32;
+
+          if (Op3Val >= RegWidth)
+            return Error(Op3->getStartLoc(),
+                         "expected integer in range [0, 31]");
+          if (Op4Val < 1 || Op4Val > RegWidth)
+            return Error(Op4->getStartLoc(),
+                         "expected integer in range [1, 32]");
+
           uint64_t NewOp3Val = 0;
           if (ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(
                   Op1->getReg()))
             NewOp3Val = (32 - Op3Val) & 0x1f;
           else
             NewOp3Val = (64 - Op3Val) & 0x3f;
 
           uint64_t NewOp4Val = Op4Val - 1;
 
+          if (NewOp3Val != 0 && NewOp4Val >= NewOp3Val)
+            return Error(Op4->getStartLoc(),
+                         "requested insert overflows register");
+
           const MCExpr *NewOp3 =
               MCConstantExpr::Create(NewOp3Val, getContext());
           const MCExpr *NewOp4 =
               MCConstantExpr::Create(NewOp4Val, getContext());
           Operands[3] = ARM64Operand::CreateImm(NewOp3, Op3->getStartLoc(),
                                                 Op3->getEndLoc(), getContext());
           Operands[4] = ARM64Operand::CreateImm(NewOp4, Op4->getStartLoc(),
                                                 Op4->getEndLoc(), getContext());
if (Tok == "bfi" || Tok == "sbfiz" || Tok == "ubfiz") {
 
       if (Op1->isReg() && Op3->isImm() && Op4->isImm()) {
         const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3->getImm());
         const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4->getImm());
 
         if (Op3CE && Op4CE) {
           uint64_t Op3Val = Op3CE->getValue();
           uint64_t Op4Val = Op4CE->getValue();
+
+          uint64_t RegWidth = 0;
+          if (ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
+              Op1->getReg()))
+            RegWidth = 64;
+          else
+            RegWidth = 32;
+
+          if (Op3Val >= RegWidth)
+            return Error(Op3->getStartLoc(),
+                         "expected integer in range [0, 31]");
+          if (Op4Val < 1 || Op4Val > RegWidth)
+            return Error(Op4->getStartLoc(),
+                         "expected integer in range [1, 32]");
+
           uint64_t NewOp4Val = Op3Val + Op4Val - 1;
 
-          if (NewOp4Val >= Op3Val) {
-            const MCExpr *NewOp4 =
-                MCConstantExpr::Create(NewOp4Val, getContext());
-            Operands[4] = ARM64Operand::CreateImm(
-                NewOp4, Op4->getStartLoc(), Op4->getEndLoc(), getContext());
-            if (Tok == "bfxil")
-              Operands[0] = ARM64Operand::CreateToken(
-                  "bfm", false, Op->getStartLoc(), getContext());
-            else if (Tok == "sbfx")
-              Operands[0] = ARM64Operand::CreateToken(
-                  "sbfm", false, Op->getStartLoc(), getContext());
-            else if (Tok == "ubfx")
-              Operands[0] = ARM64Operand::CreateToken(
-                  "ubfm", false, Op->getStartLoc(), getContext());
-            else
-              llvm_unreachable("No valid mnemonic for alias?");
+          if (NewOp4Val >= RegWidth || NewOp4Val < Op3Val)
+            return Error(Op4->getStartLoc(),
+                         "requested extract overflows register");
+
 
-            delete Op;
-            delete Op4;
-          }
-        }
-      }
-    }
-  }
   // FIXME: Horrible hack for tbz and tbnz with Wn register operand.
   //        InstAlias can't quite handle this since the reg classes aren't
   //        subclasses.
   if (NumOperands == 4 && (Tok == "tbz" || Tok == "tbnz")) {
     ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[2]);
     if (Op->isImm()) {
       if (const MCConstantExpr *OpCE = dyn_cast<MCConstantExpr>(Op->getImm())) {
         if (OpCE->getValue() < 32) {