[ARM64] Move register/register MOV handling into tablegen and improve diagnostics

[bsmith]

Summary

Patch to move register/register MOV handling into tablegen in order to improve diagnostics emitted as well as remove some of the AsmParser hacks.

As with my previous patches, there is no testcase for this as it is part of the merge of MC/AArch64/basic-a64-diagnostics.s.

[t.p.northover]

Hi Bradley,

This looks good to me.

Cheers.

Tim.

lib/Target/ARM64/ARM64InstrFormats.td

def logical_imm32_XFORM : SDNodeXForm<imm, [{
   uint64_t enc = ARM64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
   return CurDAG->getTargetConstant(enc, MVT::i32);
 }]>;
 def logical_imm64_XFORM : SDNodeXForm<imm, [{
   uint64_t enc = ARM64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
   return CurDAG->getTargetConstant(enc, MVT::i32);
 }]>;
 
-def LogicalImm32Operand : AsmOperandClass { let Name = "LogicalImm32"; }
-def LogicalImm64Operand : AsmOperandClass { let Name = "LogicalImm64"; }
+def LogicalImm32Operand : AsmOperandClass {
+  let Name = "LogicalImm32";
+  let DiagnosticType = "LogicalSecondSource";
+}
+def LogicalImm64Operand : AsmOperandClass {
+  let Name = "LogicalImm64";
+  let DiagnosticType = "LogicalSecondSource";
+}
 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
   return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 32);
 }], logical_imm32_XFORM> {
   let PrintMethod = "printLogicalImm32";
   let ParserMatchClass = LogicalImm32Operand;
 }
 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
   return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 64);

lib/Target/ARM64/ARM64InstrInfo.td

 def : InstAlias<"ngc $dst, $src",  (SBCXr  GPR64:$dst, XZR, GPR64:$src)>;
 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
 
 // Add/subtract
 defm ADD : AddSub<0, "add", add>;
 defm SUB : AddSub<1, "sub">;
 
+def : InstAlias<"mov $dst, $src",
+                (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
+def : InstAlias<"mov $dst, $src",
+                (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
+def : InstAlias<"mov $dst, $src",
+                (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
+def : InstAlias<"mov $dst, $src",
+                (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
+
 defm ADDS : AddSubS<0, "adds", ARM64add_flag, "cmn">;
 defm SUBS : AddSubS<1, "subs", ARM64sub_flag, "cmp">;
 
 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
           (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
           (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
defm BIC  : LogicalReg<0b00, 1, "bic",
                        BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
 defm EON  : LogicalReg<0b10, 1, "eon",
                        BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
 defm EOR  : LogicalReg<0b10, 0, "eor", xor>;
 defm ORN  : LogicalReg<0b01, 1, "orn",
                        BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
 defm ORR  : LogicalReg<0b01, 0, "orr", or>;
 
+def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
+def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
+
 def : InstAlias<"tst $src1, $src2",
                 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
 def : InstAlias<"tst $src1, $src2",
                 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
 
 def : InstAlias<"tst $src1, $src2",
                 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
 def : InstAlias<"tst $src1, $src2",

lib/Target/ARM64/ARM64RegisterInfo.td

def GPR32sp : RegisterClass<"ARM64", [i32], 32, (add GPR32common, WSP)> {
   let AltOrders = [(rotl GPR32sp, 8)];
   let AltOrderSelect = [{ return 1; }];
 }
 def GPR64sp : RegisterClass<"ARM64", [i64], 64, (add GPR64common, SP)> {
   let AltOrders = [(rotl GPR64sp, 8)];
   let AltOrderSelect = [{ return 1; }];
 }
 
+def GPR32sponly : RegisterClass<"ARM64", [i32], 32, (add WSP)>;
+def GPR64sponly : RegisterClass<"ARM64", [i64], 64, (add SP)>;
+
 // GPR register classes which include WZR/XZR AND SP/WSP. This is not a
 // constraint used by any instructions, it is used as a common super-class.
 def GPR32all : RegisterClass<"ARM64", [i32], 32, (add GPR32common, WZR, WSP)>;
 def GPR64all : RegisterClass<"ARM64", [i64], 64, (add GPR64common, XZR, SP)>;
 
 // For tail calls, we can't use callee-saved registers, as they are restored
 // to the saved value before the tail call, which would clobber a call address.
 // This is for indirect tail calls to store the address of the destination.

lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp

Operands[2] = ARM64Operand::CreateImm(NewImm, Op2->getStartLoc(),
                                         Op2->getEndLoc(), Context);
 
   Operands.push_back(ARM64Operand::CreateShifter(
       ARM64_AM::LSL, shift, Op2->getStartLoc(), Op2->getEndLoc(), Context));
   delete Op2;
   delete Op;
 }
 
-static void rewriteMOVRSP(ARM64AsmParser::OperandVector &Operands,
-                        MCContext &Context) {
-  ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
-  ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
-  Operands[0] =
-    ARM64Operand::CreateToken("add", false, Op->getStartLoc(), Context);
-
-  const MCExpr *Imm = MCConstantExpr::Create(0, Context);
-  Operands.push_back(ARM64Operand::CreateShiftedImm(Imm, 0, Op2->getStartLoc(),
-                                             Op2->getEndLoc(), Context));
-
-  delete Op;
-}
-
-static void rewriteMOVR(ARM64AsmParser::OperandVector &Operands,
-                        MCContext &Context) {
-  ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
-  ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
-  Operands[0] =
-    ARM64Operand::CreateToken("orr", false, Op->getStartLoc(), Context);
-
-  // Operands[2] becomes Operands[3].
-  Operands.push_back(Operands[2]);
-  // And Operands[2] becomes ZR.
-  unsigned ZeroReg = ARM64::XZR;
-  if (ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(
-          Operands[2]->getReg()))
-    ZeroReg = ARM64::WZR;
-
-  Operands[2] =
-    ARM64Operand::CreateReg(ZeroReg, false, Op2->getStartLoc(),
-                            Op2->getEndLoc(), Context);
-
-  delete Op;
-}
-
 bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
   switch (ErrCode) {
   case Match_MissingFeature:
     return Error(Loc,
                  "instruction requires a CPU feature not currently enabled");
   case Match_InvalidOperand:
     return Error(Loc, "invalid operand for instruction");
   case Match_InvalidSuffix:
     return Error(Loc, "invalid type suffix for instruction");
   case Match_AddSubRegExtendSmall:
     return Error(Loc,
       "expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]");
   case Match_AddSubRegExtendLarge:
     return Error(Loc,
       "expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]");
   case Match_AddSubSecondSource:
     return Error(Loc,
       "expected compatible register, symbol or integer in range [0, 4095]");
+  case Match_LogicalSecondSource:
+    return Error(Loc, "expected compatible register or logical immediate");
   case Match_AddSubRegShift32:
     return Error(Loc,
        "expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]");
   case Match_AddSubRegShift64:
     return Error(Loc,
        "expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 63]");
   case Match_InvalidMemoryIndexedSImm9:
     return Error(Loc, "index must be an integer in range [-256, 255].");
bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   unsigned NumOperands = Operands.size();
 
   if (Tok == "mov" && NumOperands == 3) {
     // The MOV mnemomic is aliased to movn/movz, depending on the value of
     // the immediate being instantiated.
     // FIXME: Catching this here is a total hack, and we should use tblgen
     // support to implement this instead as soon as it is available.
 
-    ARM64Operand *Op1 = static_cast<ARM64Operand *>(Operands[1]);
     ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
     if (Op2->isImm()) {
       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op2->getImm())) {
         uint64_t Val = CE->getValue();
         uint64_t NVal = ~Val;
 
         // If this is a 32-bit register and the value has none of the upper
         // set, clear the complemented upper 32-bits so the logic below works
if (Op2->isImm()) {
         // MOVN Rd, ~(imm << 32)
         else if ((NVal & 0xFFFF00000000ULL) == NVal)
           rewriteMOVI(Operands, "movn", NVal, 32, getContext());
 
         // MOVN Rd, ~(imm << 48)
         else if ((NVal & 0xFFFF000000000000ULL) == NVal)
           rewriteMOVI(Operands, "movn", NVal, 48, getContext());
       }
-    } else if (Op1->isReg() && Op2->isReg()) {
-      // reg->reg move.
-      unsigned Reg1 = Op1->getReg();
-      unsigned Reg2 = Op2->getReg();
-      if ((Reg1 == ARM64::SP &&
-           ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(Reg2)) ||
-          (Reg2 == ARM64::SP &&
-           ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(Reg1)) ||
-          (Reg1 == ARM64::WSP &&
-           ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(Reg2)) ||
-          (Reg2 == ARM64::WSP &&
-           ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(Reg1)))
-        rewriteMOVRSP(Operands, getContext());
-      else
-        rewriteMOVR(Operands, getContext());
     }
   } else if (NumOperands == 4) {
     if (NumOperands == 4 && Tok == "lsl") {
       ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
       ARM64Operand *Op3 = static_cast<ARM64Operand *>(Operands[3]);
       if (Op2->isReg() && Op3->isImm()) {
         const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3->getImm());
         if (Op3CE) {
case Match_InvalidMemoryIndexed128:
     // want the diagnostic for the pre-indexed instruction variant instead.
     if (Operands.size() > ErrorInfo + 1 &&
         ((ARM64Operand *)Operands[ErrorInfo + 1])->isTokenEqual("!"))
       MatchResult = Match_InvalidMemoryIndexedSImm9;
   // FALL THROUGH
   case Match_AddSubRegExtendSmall:
   case Match_AddSubRegExtendLarge:
   case Match_AddSubSecondSource:
+  case Match_LogicalSecondSource:
   case Match_AddSubRegShift32:
   case Match_AddSubRegShift64:
   case Match_InvalidMemoryIndexed8:
   case Match_InvalidMemoryIndexed16:
   case Match_InvalidMemoryIndexed32SImm7:
   case Match_InvalidMemoryIndexed64SImm7:
   case Match_InvalidMemoryIndexed128SImm7:
   case Match_InvalidImm0_7: