[ARM64] Conditionalize CPU specific system registers on subtarget features

[bsmith]

Summary

Currently there is no conditionalization on any CPU specific system registers hence they are assembled/disassembled when they are not defined (i.e. in the case of Cyclone sysregs for the generic CPU). This patch fixes this by passing the subtarget feature bits through to the system register mappers so that only systems registers valid in the current context are handled.

[t.p.northover]

Hi Bradley,

This looks reasonable to me. It may not scale that well when there are thousands of different CPUs, but we can do some refactoring when that happens.

Cheers.

Tim.

lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp

private:
 
   struct BarrierOp {
     unsigned Val; // Not the enum since not all values have names.
   };
 
   struct SysRegOp {
     const char *Data;
     unsigned Length;
+    uint64_t FeatureBits; // We need to pass through information about which
+                          // core we are compiling for so that the SysReg
+                          // Mappers can appropriately conditionalize.
   };
 
   struct SysCRImmOp {
     unsigned Val;
   };
 
   struct PrefetchOp {
     unsigned Val;
unsigned getVectorIndex() const {
     return VectorIndex.Val;
   }
 
   StringRef getSysReg() const {
     assert(Kind == k_SysReg && "Invalid access!");
     return StringRef(SysReg.Data, SysReg.Length);
   }
 
+  uint64_t getSysRegFeatureBits() const {
+    assert(Kind == k_SysReg && "Invalid access!");
+    return SysReg.FeatureBits;
+  }
+
   unsigned getSysCR() const {
     assert(Kind == k_SysCR && "Invalid access!");
     return SysCRImm.Val;
   }
 
   unsigned getPrefetch() const {
     assert(Kind == k_Prefetch && "Invalid access!");
     return Prefetch.Val;
public:
 
   bool isFPImm() const { return Kind == k_FPImm; }
   bool isBarrier() const { return Kind == k_Barrier; }
   bool isSysReg() const { return Kind == k_SysReg; }
   bool isMRSSystemRegister() const {
     if (!isSysReg()) return false;
 
     bool IsKnownRegister;
-    ARM64SysReg::MRSMapper().fromString(getSysReg(), IsKnownRegister);
+    auto Mapper = ARM64SysReg::MRSMapper(getSysRegFeatureBits());
+    Mapper.fromString(getSysReg(), IsKnownRegister);
 
     return IsKnownRegister;
   }
   bool isMSRSystemRegister() const {
     if (!isSysReg()) return false;
 
     bool IsKnownRegister;
-    ARM64SysReg::MSRMapper().fromString(getSysReg(), IsKnownRegister);
+    auto Mapper = ARM64SysReg::MSRMapper(getSysRegFeatureBits());
+    Mapper.fromString(getSysReg(), IsKnownRegister);
 
     return IsKnownRegister;
   }
   bool isSystemPStateField() const {
     if (!isSysReg()) return false;
 
     bool IsKnownRegister;
     ARM64PState::PStateMapper().fromString(getSysReg(), IsKnownRegister);
void addBarrierOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateImm(getBarrier()));
   }
 
   void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     bool Valid;
-    uint32_t Bits = ARM64SysReg::MRSMapper().fromString(getSysReg(), Valid);
+    auto Mapper = ARM64SysReg::MRSMapper(getSysRegFeatureBits());
+    uint32_t Bits = Mapper.fromString(getSysReg(), Valid);
 
     Inst.addOperand(MCOperand::CreateImm(Bits));
   }
 
   void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     bool Valid;
-    uint32_t Bits = ARM64SysReg::MSRMapper().fromString(getSysReg(), Valid);
+    auto Mapper = ARM64SysReg::MSRMapper(getSysRegFeatureBits());
+    uint32_t Bits = Mapper.fromString(getSysReg(), Valid);
 
     Inst.addOperand(MCOperand::CreateImm(Bits));
   }
 
   void addSystemPStateFieldOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     bool Valid;

   static ARM64Operand *CreateBarrier(unsigned Val, SMLoc S, MCContext &Ctx) {
     ARM64Operand *Op = new ARM64Operand(k_Barrier, Ctx);
     Op->Barrier.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
-  static ARM64Operand *CreateSysReg(StringRef Str, SMLoc S, MCContext &Ctx) {
+  static ARM64Operand *CreateSysReg(StringRef Str, SMLoc S,
+                                    uint64_t FeatureBits, MCContext &Ctx) {
     ARM64Operand *Op = new ARM64Operand(k_SysReg, Ctx);
     Op->SysReg.Data = Str.data();
     Op->SysReg.Length = Str.size();
+    Op->SysReg.FeatureBits = FeatureBits;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
   static ARM64Operand *CreateMem(unsigned BaseRegNum, const MCExpr *Off,
                                  SMLoc S, SMLoc E, SMLoc OffsetLoc,
                                  MCContext &Ctx) {

 ARM64AsmParser::OperandMatchResultTy
 ARM64AsmParser::tryParseSysReg(OperandVector &Operands) {
   const AsmToken &Tok = Parser.getTok();
 
   if (Tok.isNot(AsmToken::Identifier))
     return MatchOperand_NoMatch;
 
   Operands.push_back(ARM64Operand::CreateSysReg(Tok.getString(), getLoc(),
-                     getContext()));
+                     STI.getFeatureBits(), getContext()));
   Parser.Lex(); // Eat identifier
 
   return MatchOperand_Success;
 }
 
 /// tryParseVectorRegister - Parse a vector register operand.
 bool ARM64AsmParser::tryParseVectorRegister(OperandVector &Operands) {
   if (Parser.getTok().isNot(AsmToken::Identifier))

lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp

if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr,
                                      Inst.getOpcode() != ARM64::LDRXl, 0, 4))
     Inst.addOperand(MCOperand::CreateImm(ImmVal));
   return Success;
 }
 
 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
                                             uint64_t Address,
                                             const void *Decoder) {
+  const ARM64Disassembler *Dis =
+      static_cast<const ARM64Disassembler *>(Decoder);
+  const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
+
   Imm |= 0x8000;
   Inst.addOperand(MCOperand::CreateImm(Imm));
 
   bool ValidNamed;
-  (void)ARM64SysReg::MRSMapper().toString(Imm, ValidNamed);
+  (void)ARM64SysReg::MRSMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
 
   return ValidNamed ? Success : Fail;
 }
 
 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
                                             uint64_t Address,
                                             const void *Decoder) {
+  const ARM64Disassembler *Dis =
+      static_cast<const ARM64Disassembler *>(Decoder);
+  const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
+
   Imm |= 0x8000;
   Inst.addOperand(MCOperand::CreateImm(Imm));
 
   bool ValidNamed;
-  (void)ARM64SysReg::MSRMapper().toString(Imm, ValidNamed);
+  (void)ARM64SysReg::MSRMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
 
   return ValidNamed ? Success : Fail;
 }
 
 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
                                        unsigned Add) {
   Inst.addOperand(MCOperand::CreateImm(Add - Imm));
   return Success;

lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp

else
     O << "#" << Val;
 }
 
 void ARM64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   bool Valid;
-  auto Mapper = ARM64SysReg::MRSMapper();
+  auto Mapper = ARM64SysReg::MRSMapper(getAvailableFeatures());
   std::string Name = Mapper.toString(Val, Valid);
 
   if (Valid)
     O << StringRef(Name).upper();
 }
 
 void ARM64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   bool Valid;
-  auto Mapper = ARM64SysReg::MSRMapper();
+  auto Mapper = ARM64SysReg::MSRMapper(getAvailableFeatures());
   std::string Name = Mapper.toString(Val, Valid);
 
   if (Valid)
     O << StringRef(Name).upper();
 }
 
 void ARM64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
                                               raw_ostream &O) {

lib/Target/ARM64/Utils/ARM64BaseInfo.h

enum SysRegValues {
     ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
     ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
     ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
     ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
     ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
     ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
     ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
     ICH_LR15_EL2      = 0xe66f, // 11  100  1100  1101  111
+  };
 
-    // Cyclone specific system registers
+  enum CycloneSysRegValues {
     CPM_IOACC_CTL_EL3 = 0xff90
   };
 
   // Note that these do not inherit from ARM64NamedImmMapper. This class is
   // sufficiently different in its behaviour that I don't believe it's worth
   // burdening the common ARM64NamedImmMapper with abstractions only needed in
   // this one case.
   struct SysRegMapper {
     static const ARM64NamedImmMapper::Mapping SysRegPairs[];
+    static const ARM64NamedImmMapper::Mapping CycloneSysRegPairs[];
 
     const ARM64NamedImmMapper::Mapping *InstPairs;
     size_t NumInstPairs;
+    uint64_t FeatureBits;
 
-    SysRegMapper() {}
+    SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
     uint32_t fromString(StringRef Name, bool &Valid) const;
     std::string toString(uint32_t Bits, bool &Valid) const;
   };
 
   struct MSRMapper : SysRegMapper {
     static const ARM64NamedImmMapper::Mapping MSRPairs[];
-    MSRMapper();
+    MSRMapper(uint64_t FeatureBits);
   };
 
   struct MRSMapper : SysRegMapper {
     static const ARM64NamedImmMapper::Mapping MRSPairs[];
-    MRSMapper();
+    MRSMapper(uint64_t FeatureBits);
   };
 
   uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
 }
 
 namespace ARM64TLBI {
   enum TLBIValues {
     Invalid = -1,          // Op0 Op1  CRn   CRm   Op2

lib/Target/ARM64/Utils/ARM64BaseInfo.cpp

const ARM64NamedImmMapper::Mapping ARM64SysReg::MRSMapper::MRSPairs[] = {
   {"icc_hppir1_el1", ICC_HPPIR1_EL1},
   {"icc_hppir0_el1", ICC_HPPIR0_EL1},
   {"icc_rpr_el1", ICC_RPR_EL1},
   {"ich_vtr_el2", ICH_VTR_EL2},
   {"ich_eisr_el2", ICH_EISR_EL2},
   {"ich_elsr_el2", ICH_ELSR_EL2}
 };
 
-ARM64SysReg::MRSMapper::MRSMapper() {
+ARM64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
+  : SysRegMapper(FeatureBits) {
     InstPairs = &MRSPairs[0];
     NumInstPairs = llvm::array_lengthof(MRSPairs);
 }
 
 const ARM64NamedImmMapper::Mapping ARM64SysReg::MSRMapper::MSRPairs[] = {
   {"dbgdtrtx_el0", DBGDTRTX_EL0},
   {"oslar_el1", OSLAR_EL1},
   {"pmswinc_el0", PMSWINC_EL0},
 
   // Trace registers
   {"trcoslar", TRCOSLAR},
   {"trclar", TRCLAR},
 
   // GICv3 registers
   {"icc_eoir1_el1", ICC_EOIR1_EL1},
   {"icc_eoir0_el1", ICC_EOIR0_EL1},
   {"icc_dir_el1", ICC_DIR_EL1},
   {"icc_sgi1r_el1", ICC_SGI1R_EL1},
   {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
   {"icc_sgi0r_el1", ICC_SGI0R_EL1}
 };
 
-ARM64SysReg::MSRMapper::MSRMapper() {
+ARM64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
+  : SysRegMapper(FeatureBits) {
     InstPairs = &MSRPairs[0];
     NumInstPairs = llvm::array_lengthof(MSRPairs);
 }
 
 
 const ARM64NamedImmMapper::Mapping ARM64SysReg::SysRegMapper::SysRegPairs[] = {
   {"osdtrrx_el1", OSDTRRX_EL1},
   {"osdtrtx_el1",  OSDTRTX_EL1},
const ARM64NamedImmMapper::Mapping ARM64SysReg::SysRegMapper::SysRegPairs[] = {
   {"ich_lr7_el2", ICH_LR7_EL2},
   {"ich_lr8_el2", ICH_LR8_EL2},
   {"ich_lr9_el2", ICH_LR9_EL2},
   {"ich_lr10_el2", ICH_LR10_EL2},
   {"ich_lr11_el2", ICH_LR11_EL2},
   {"ich_lr12_el2", ICH_LR12_EL2},
   {"ich_lr13_el2", ICH_LR13_EL2},
   {"ich_lr14_el2", ICH_LR14_EL2},
-  {"ich_lr15_el2", ICH_LR15_EL2},
+  {"ich_lr15_el2", ICH_LR15_EL2}
+};
+
+const ARM64NamedImmMapper::Mapping
+ARM64SysReg::SysRegMapper::CycloneSysRegPairs[] = {
   {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3}
 };
 
 uint32_t
 ARM64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
-  // First search the registers shared by all
   std::string NameLower = Name.lower();
+
+  // First search the registers shared by all
   for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
     if (SysRegPairs[i].Name == NameLower) {
       Valid = true;
       return SysRegPairs[i].Value;
     }
   }
 
+  // Next search for target specific registers
+  if (FeatureBits & ARM64::ProcCyclone) {
+    for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
+      if (CycloneSysRegPairs[i].Name == NameLower) {
+        Valid = true;
+        return CycloneSysRegPairs[i].Value;
+      }
+    }
+  }
+
   // Now try the instruction-specific registers (either read-only or
   // write-only).
   for (unsigned i = 0; i < NumInstPairs; ++i) {
     if (InstPairs[i].Name == NameLower) {
       Valid = true;
       return InstPairs[i].Value;
     }
   }
ARM64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
   Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
 
   Valid = true;
   return Bits;
 }
 
 std::string
 ARM64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const {
+  // First search the registers shared by all
   for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
     if (SysRegPairs[i].Value == Bits) {
       Valid = true;
       return SysRegPairs[i].Name;
     }
   }
 
+  // Next search for target specific registers
+  if (FeatureBits & ARM64::ProcCyclone) {
+    for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
+      if (CycloneSysRegPairs[i].Value == Bits) {
+        Valid = true;
+        return CycloneSysRegPairs[i].Name;
+      }
+    }
+  }
+
+  // Now try the instruction-specific registers (either read-only or
+  // write-only).
   for (unsigned i = 0; i < NumInstPairs; ++i) {
     if (InstPairs[i].Value == Bits) {
       Valid = true;
       return InstPairs[i].Name;
     }
   }
 
   uint32_t Op0 = (Bits >> 14) & 0x3;

test/MC/ARM64/system-encoding.s

 ; CHECK: mrs  x3, DBGAUTHSTATUS_EL1   ; encoding: [0xc3,0x7e,0x30,0xd5]
 ; CHECK: mrs    x1, S3_2_C15_C6_4       ; encoding: [0x81,0xf6,0x3a,0xd5]
 ; CHECK: mrs  x3, S3_3_C11_C1_4       ; encoding: [0x83,0xb1,0x3b,0xd5]
 ; CHECK: mrs  x3, S3_3_C11_C1_4       ; encoding: [0x83,0xb1,0x3b,0xd5]
 
   msr RMR_EL3, x0
   msr RMR_EL2, x0
   msr RMR_EL1, x0
-  msr CPM_IOACC_CTL_EL3, x0
   msr OSLAR_EL1, x3
   msr DBGDTRTX_EL0, x3
         
 ; CHECK: msr  RMR_EL3, x0             ; encoding: [0x40,0xc0,0x1e,0xd5]
 ; CHECK: msr  RMR_EL2, x0             ; encoding: [0x40,0xc0,0x1c,0xd5]
 ; CHECK: msr  RMR_EL1, x0             ; encoding: [0x40,0xc0,0x18,0xd5]
-; CHECK: msr  CPM_IOACC_CTL_EL3, x0   ; encoding: [0x00,0xf2,0x1f,0xd5]
 ; CHECK: msr  OSLAR_EL1, x3           ; encoding: [0x83,0x10,0x10,0xd5]
 ; CHECK: msr  DBGDTRTX_EL0, x3        ; encoding: [0x03,0x05,0x13,0xd5]
         
  mrs x0, ID_PFR0_EL1
  mrs x0, ID_PFR1_EL1
  mrs x0, ID_DFR0_EL1
  mrs x0, ID_AFR0_EL1
  mrs x0, ID_ISAR0_EL1

test/MC/ARM64/target-specific-sysreg.s

+// RUN: not llvm-mc -triple arm64 -mcpu=generic -show-encoding < %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-GENERIC
+//
+// RUN: llvm-mc -triple arm64 -mcpu=cyclone -show-encoding < %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-CYCLONE
+
+msr CPM_IOACC_CTL_EL3, x0
+
+// CHECK-GENERIC: error: expected writable system register or pstate
+// CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0   // encoding: [0x00,0xf2,0x1f,0xd5]