ARM: remove @llvm.arm.sevl intrinsic

[abdulras]

Summary

With the introduction of the @llvm.arm.hint intrinsic, this is no longer needed.
The users of this intrinsic can spell this as '@llvm.arm.hint(i32 5)'.

Depends on http://reviews.llvm.org/D3495.

[t.p.northover]

Hi Saleem,

This looks good to me (obviously, once @llvm.arm.hint is committed).

Cheers.

Tim.

[abdulras]

Committed as SVN r207246.

include/llvm/IR/IntrinsicsARM.td

def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 
 //===----------------------------------------------------------------------===//
 // HINT
-def int_arm_sevl : Intrinsic<[], []>;
 
 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 
 //===----------------------------------------------------------------------===//
 // Advanced SIMD (NEON)
 
 // The following classes do not correspond directly to GCC builtins.
 class Neon_1Arg_Intrinsic

lib/Target/ARM/ARMInstrInfo.td

 
 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
 
-def : Pat<(int_arm_sevl), (HINT 5)>;
-
 def : Pat<(int_arm_hint 0), (HINT 0)>;
 def : Pat<(int_arm_hint 1), (HINT 1)>;
 def : Pat<(int_arm_hint 2), (HINT 2)>;
 def : Pat<(int_arm_hint 3), (HINT 3)>;
 def : Pat<(int_arm_hint 4), (HINT 4)>;
 def : Pat<(int_arm_hint 5), (HINT 5)>;
 
 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",

lib/Target/ARM/ARMInstrThumb.td

 def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
 def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
   let Predicates = [IsThumb2, HasV8];
 }
 
-def : T2Pat<(int_arm_sevl), (tHINT 5)>;
-
 def : T2Pat<(int_arm_hint 0), (tHINT 0)>;
 def : T2Pat<(int_arm_hint 1), (tHINT 1)>;
 def : T2Pat<(int_arm_hint 2), (tHINT 2)>;
 def : T2Pat<(int_arm_hint 3), (tHINT 3)>;
 def : T2Pat<(int_arm_hint 4), (tHINT 4)>;
 def : T2Pat<(int_arm_hint 5), (tHINT 5)>;
 
 // The imm operand $val can be used by a debugger to store more information

test/CodeGen/ARM/intrinsics-v8.ll

 ; RUN: llc < %s -mtriple=armv8 -mattr=+db | FileCheck %s
 
 define void @test() {
   ; CHECK: dmb sy
   call void @llvm.arm.dmb(i32 15)
   ; CHECK: dmb osh
   call void @llvm.arm.dmb(i32 3)
   ; CHECK: dsb sy
   call void @llvm.arm.dsb(i32 15)
   ; CHECK: dsb ishld
   call void @llvm.arm.dsb(i32 9)
   ; CHECK: sevl
-  tail call void @llvm.arm.sevl() nounwind
+  tail call void @llvm.arm.hint(i32 5) nounwind
   ret void
 }
 
 declare void @llvm.arm.dmb(i32)
 declare void @llvm.arm.dsb(i32)
-declare void @llvm.arm.sevl() nounwind
+declare void @llvm.arm.hint(i32) nounwind