Enable global merge pass

[Jiangning]

Summary

This is the patch to enable global merge pass for AArch64 and adrp instructions can be reduced accordingly. For ARM64, it also works, but it fails to reduce adrp instructions statically due to different ISEL strategy.

[t.p.northover]

Hi Jiangning,

This looks straightforward enough; go for it.

Tim.

[Jiangning]

Committed as r206861.

Thanks,
-Jiangning

2014-04-20 0:20 GMT+08:00 Tim Northover <[e-mail]>:

Hi Jiangning,

This looks straightforward enough; go for it.

Tim.

http://reviews.llvm.org/D3431

lib/Target/AArch64/AArch64ISelLowering.h

   virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                                   unsigned Intrinsic) const override;
 
+  /// getMaximalGlobalOffset - Returns the maximal possible offset which can
+  /// be used for loads / stores from the global.
+  unsigned getMaximalGlobalOffset() const override;
+
 protected:
   std::pair<const TargetRegisterClass*, uint8_t>
   findRepresentativeClass(MVT VT) const;

lib/Target/AArch64/AArch64ISelLowering.cpp

     return AM.Scale != 0 && AM.Scale != 1;
   return -1;
 }
+
+/// getMaximalGlobalOffset - Returns the maximal possible offset which can
+/// be used for loads / stores from the global.
+unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
+  return 4095;
+}
+

lib/Target/AArch64/AArch64TargetMachine.cpp

 #include "llvm/CodeGen/Passes.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/TargetRegistry.h"
+#include "llvm/Transforms/Scalar.h"
 
 using namespace llvm;
 

     return *getAArch64TargetMachine().getSubtargetImpl();
   }
 
+  bool addPreISel() override;
   virtual bool addInstSelector();
   virtual bool addPreEmitPass();
 };
 } // namespace
 
+bool AArch64PassConfig::addPreISel() {
+  if (TM->getOptLevel() != CodeGenOpt::None)
+    addPass(createGlobalMergePass(TM));
+
+  return false;
+}
+
 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
   return new AArch64PassConfig(this, PM);
 }

test/CodeGen/AArch64/global_merge_1.ll

+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+@m = internal global i32 0, align 4
+@n = internal global i32 0, align 4
+
+define void @f1(i32 %a1, i32 %a2) {
+; CHECK-LABEL: f1:
+; CHECK: adrp x{{[0-9]+}}, _MergedGlobals
+; CHECK-NOT: adrp
+  store i32 %a1, i32* @m, align 4
+  store i32 %a2, i32* @n, align 4
+  ret void
+}
+
+; CHECK:        .local _MergedGlobals
+; CHECK:        .comm  _MergedGlobals,8,8
+