[ARM] Assign cost of scaling for Cortex-R52

[javed.absar]

Summary

This patch assigns cost of the scaling used in addressing for Cortex-R52.

On Cortex-R52 a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode.

[jmolloy]

Please provide patches with full context.

The test looks like it's duplicating checks for no good reason - It looks like we could simply have one check - CHECK-NONEGOFF. Then the three runs, A53, A57 and R52 would all use that same check.

The .td change looks fine.

[javed.absar]

Hi James:
Have revised the test based on your suggestions. Please have a look if it is alright for you now.
Best Regards
Javed

[jmolloy]

LGTM, cheers!

llvm/trunk/lib/Target/ARM/ARM.td

def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
-def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52]>;
+def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52,
+                                                         FeatureFPAO]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "ARMRegisterInfo.td"
 
 include "ARMCallingConv.td"

llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll

 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 ; Should use scaled addressing mode.
 
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A53
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A57
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
 ; Should not generate negated register offset
 
 define void @sintzero(i32* %a) nounwind {
 entry:
   store i32 0, i32* %a
   br label %cond_next
 
 cond_next:    ; preds = %cond_next, %entry
   %indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ]    ; <i32> [#uses=1]
   %tmp25 = add i32 %indvar, 1   ; <i32> [#uses=3]
   %tmp36 = getelementptr i32, i32* %a, i32 %tmp25    ; <i32*> [#uses=1]
   store i32 0, i32* %tmp36
   icmp eq i32 %tmp25, -1    ; <i1>:0 [#uses=1]
   br i1 %0, label %return, label %cond_next
 
 return:   ; preds = %cond_next
   ret void
 }
 
 ; CHECK: lsl{{.*}}#2]
-; CHECK-NONEGOFF-A53: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
-; CHECK-NONEGOFF-A57: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
+; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]