This is an archive of the discontinued LLVM Phabricator instance.

Differential D23850

MIRParser/MachineFuncProperties: Rename AllVRegsAllocated->NoVRegs, compute it
ClosedPublic

Authored by MatzeB on Aug 24 2016, 1:17 PM.

Details

Reviewers
qcolombet
dexonsmith
Commits
rG1eb473680a3d: MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute…
rL279698: MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs…
Summary

Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of
running after register and simply describes that no vregs are used in
a machine function. With that we can simply compute the property and do
not need to print/parse them in .mir files.

Diff Detail

Repository
rL LLVM

Event Timeline

MatzeB updated this revision to Diff 69160.Aug 24 2016, 1:17 PM
MatzeB retitled this revision from to MIRParser/MachineFuncProperties: Rename AllVRegsAllocated->NoVRegs, compute it.
MatzeB updated this object.
MatzeB added reviewers: qcolombet, dexonsmith.
MatzeB set the repository for this revision to rL LLVM.
MatzeB added a subscriber: llvm-commits.
Herald added subscribers: nemanjai, mcrosier, jyknight and 3 others. · View Herald TranscriptAug 24 2016, 1:17 PM
MatzeB updated this object.Aug 24 2016, 1:22 PM
qcolombet accepted this revision.Aug 24 2016, 5:47 PM
qcolombet edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Aug 24 2016, 5:47 PM
Closed by commit rL279698: MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs… (authored by matze). · Explain WhyAug 24 2016, 6:35 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
CodeGen/
3 lines
6 lines
lib/
CodeGen/
2 lines
2 lines
2 lines
2 lines
2 lines
MIRParser/
6 lines
2 lines
2 lines
2 lines
11 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
Target/
AArch64/
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
ARM/
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
Hexagon/
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
Lanai/
2 lines
2 lines
MSP430/
2 lines
Mips/
2 lines
2 lines
2 lines
2 lines
PowerPC/
2 lines
2 lines
Sparc/
2 lines
SystemZ/
2 lines
2 lines
2 lines
WebAssembly/
2 lines
X86/
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
XCore/
2 lines
test/
CodeGen/
AArch64/
2 lines
1 line
ARM/
1 line
Hexagon/
1 line
MIR/
AArch64/
1 line
20 lines
ARM/
1 line
Hexagon/
1 line
Lanai/
9 lines
PowerPC/
1 line
1 line
1 line
X86/
1 line
7 lines
4 lines
12 lines
1 line
DebugInfo/
MIR/
X86/
1 line
1 line

Diff 69192

llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h

Show First 20 Lines • Show All 375 Lines • ▼ Show 20 Lines YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
StringValue()); // Don't print it out when it's empty. StringValue()); // Don't print it out when it's empty.
} }
}; };
struct MachineFunction { struct MachineFunction {
StringRef Name; StringRef Name;
unsigned Alignment = 0; unsigned Alignment = 0;
bool ExposesReturnsTwice = false; bool ExposesReturnsTwice = false;
// MachineFunctionProperties
bool AllVRegsAllocated = false;
// GISel MachineFunctionProperties. // GISel MachineFunctionProperties.
bool Legalized = false; bool Legalized = false;
bool RegBankSelected = false; bool RegBankSelected = false;
bool Selected = false; bool Selected = false;
// Register information // Register information
bool TracksRegLiveness = false; bool TracksRegLiveness = false;
std::vector<VirtualRegisterDefinition> VirtualRegisters; std::vector<VirtualRegisterDefinition> VirtualRegisters;
std::vector<MachineFunctionLiveIn> LiveIns; std::vector<MachineFunctionLiveIn> LiveIns;
Optional<std::vector<FlowStringValue>> CalleeSavedRegisters; Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
// TODO: Serialize the various register masks. // TODO: Serialize the various register masks.
// Frame information // Frame information
MachineFrameInfo FrameInfo; MachineFrameInfo FrameInfo;
std::vector<FixedMachineStackObject> FixedStackObjects; std::vector<FixedMachineStackObject> FixedStackObjects;
std::vector<MachineStackObject> StackObjects; std::vector<MachineStackObject> StackObjects;
std::vector<MachineConstantPoolValue> Constants; /// Constant pool. std::vector<MachineConstantPoolValue> Constants; /// Constant pool.
MachineJumpTable JumpTableInfo; MachineJumpTable JumpTableInfo;
BlockStringValue Body; BlockStringValue Body;
}; };
template <> struct MappingTraits<MachineFunction> { template <> struct MappingTraits<MachineFunction> {
static void mapping(IO &YamlIO, MachineFunction &MF) { static void mapping(IO &YamlIO, MachineFunction &MF) {
YamlIO.mapRequired("name", MF.Name); YamlIO.mapRequired("name", MF.Name);
YamlIO.mapOptional("alignment", MF.Alignment); YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
YamlIO.mapOptional("legalized", MF.Legalized); YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected); YamlIO.mapOptional("selected", MF.Selected);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("registers", MF.VirtualRegisters); YamlIO.mapOptional("registers", MF.VirtualRegisters);
YamlIO.mapOptional("liveins", MF.LiveIns); YamlIO.mapOptional("liveins", MF.LiveIns);
YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters); YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
YamlIO.mapOptional("frameInfo", MF.FrameInfo); YamlIO.mapOptional("frameInfo", MF.FrameInfo);
Show All 13 Lines

llvm/trunk/include/llvm/CodeGen/MachineFunction.h

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) {
return new (Allocator.Allocate<Ty>()) Ty(MF); return new (Allocator.Allocate<Ty>()) Ty(MF);
} }
}; };
/// Properties which a MachineFunction may have at a given point in time. /// Properties which a MachineFunction may have at a given point in time.
/// Each of these has checking code in the MachineVerifier, and passes can /// Each of these has checking code in the MachineVerifier, and passes can
/// require that a property be set. /// require that a property be set.
class MachineFunctionProperties { class MachineFunctionProperties {
// TODO: Add MachineVerifier checks for AllVRegsAllocated
// Possible TODO: Allow targets to extend this (perhaps by allowing the // Possible TODO: Allow targets to extend this (perhaps by allowing the
// constructor to specify the size of the bit vector) // constructor to specify the size of the bit vector)
// Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
// stated as the negative of "has vregs" // stated as the negative of "has vregs"
public: public:
// The properties are stated in "positive" form; i.e. a pass could require // The properties are stated in "positive" form; i.e. a pass could require
// that the property hold, but not that it does not hold. // that the property hold, but not that it does not hold.
// Property descriptions: // Property descriptions:
// IsSSA: True when the machine function is in SSA form and virtual registers // IsSSA: True when the machine function is in SSA form and virtual registers
// have a single def. // have a single def.
// NoPHIs: The machine function does not contain any PHI instruction. // NoPHIs: The machine function does not contain any PHI instruction.
// TracksLiveness: True when tracking register liveness accurately. // TracksLiveness: True when tracking register liveness accurately.
// While this property is set, register liveness information in basic block // While this property is set, register liveness information in basic block
// live-in lists and machine instruction operands (e.g. kill flags, implicit // live-in lists and machine instruction operands (e.g. kill flags, implicit
// defs) is accurate. This means it can be used to change the code in ways // defs) is accurate. This means it can be used to change the code in ways
// that affect the values in registers, for example by the register // that affect the values in registers, for example by the register
// scavenger. // scavenger.
// When this property is clear, liveness is no longer reliable. // When this property is clear, liveness is no longer reliable.
// AllVRegsAllocated: All virtual registers have been allocated; i.e. all // NoVRegs: The machine function does not use any virtual registers.
// register operands are physical registers.
// Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic // Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic
// instructions have been legalized; i.e., all instructions are now one of: // instructions have been legalized; i.e., all instructions are now one of:
// - generic and always legal (e.g., COPY) // - generic and always legal (e.g., COPY)
// - target-specific // - target-specific
// - legal pre-isel generic instructions. // - legal pre-isel generic instructions.
// RegBankSelected: In GlobalISel: the RegBankSelect pass ran and all generic // RegBankSelected: In GlobalISel: the RegBankSelect pass ran and all generic
// virtual registers have been assigned to a register bank. // virtual registers have been assigned to a register bank.
// Selected: In GlobalISel: the InstructionSelect pass ran and all pre-isel // Selected: In GlobalISel: the InstructionSelect pass ran and all pre-isel
// generic instructions have been eliminated; i.e., all instructions are now // generic instructions have been eliminated; i.e., all instructions are now
// target-specific or non-pre-isel generic instructions (e.g., COPY). // target-specific or non-pre-isel generic instructions (e.g., COPY).
// Since only pre-isel generic instructions can have generic virtual register // Since only pre-isel generic instructions can have generic virtual register
// operands, this also means that all generic virtual registers have been // operands, this also means that all generic virtual registers have been
// constrained to virtual registers (assigned to register classes) and that // constrained to virtual registers (assigned to register classes) and that
// all sizes attached to them have been eliminated. // all sizes attached to them have been eliminated.
enum class Property : unsigned { enum class Property : unsigned {
IsSSA, IsSSA,
NoPHIs, NoPHIs,
TracksLiveness, TracksLiveness,
AllVRegsAllocated, NoVRegs,
Legalized, Legalized,
RegBankSelected, RegBankSelected,
Selected, Selected,
LastProperty = Selected, LastProperty = Selected,
}; };
bool hasProperty(Property P) const { bool hasProperty(Property P) const {
return Properties[static_cast<unsigned>(P)]; return Properties[static_cast<unsigned>(P)];
▲ Show 20 Lines • Show All 538 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll(); AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Execution dependency fix"; return "Execution dependency fix";
} }
private: private:
iterator_range<SmallVectorImpl<int>::const_iterator> iterator_range<SmallVectorImpl<int>::const_iterator>
▲ Show 20 Lines • Show All 686 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/FuncletLayout.cpp

Show All 24 Linespublic:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
FuncletLayout() : MachineFunctionPass(ID) { FuncletLayout() : MachineFunctionPass(ID) {
initializeFuncletLayoutPass(*PassRegistry::getPassRegistry()); initializeFuncletLayoutPass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
} }
char FuncletLayout::ID = 0; char FuncletLayout::ID = 0;
char &llvm::FuncletLayoutID = FuncletLayout::ID; char &llvm::FuncletLayoutID = FuncletLayout::ID;
INITIALIZE_PASS(FuncletLayout, "funclet-layout", INITIALIZE_PASS(FuncletLayout, "funclet-layout",
"Contiguously Lay Out Funclets", false, false) "Contiguously Lay Out Funclets", false, false)
Show All 18 Lines

llvm/trunk/lib/CodeGen/IfConversion.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBranchProbabilityInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
bool ReverseBranchCondition(BBInfo &BBI) const; bool ReverseBranchCondition(BBInfo &BBI) const;
bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups, bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
BranchProbability Prediction) const; BranchProbability Prediction) const;
bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI, bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
bool FalseBranch, unsigned &Dups, bool FalseBranch, unsigned &Dups,
▲ Show 20 Lines • Show All 2,032 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Linespublic:
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<AAResultsWrapperPass>(); AU.addRequired<AAResultsWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
/// \brief Detect re-ordering hazards and dependencies. /// \brief Detect re-ordering hazards and dependencies.
/// ///
/// This class keeps track of defs and uses, and can be queried if a given /// This class keeps track of defs and uses, and can be queried if a given
/// machine instruction can be re-ordered from after the machine instructions /// machine instruction can be re-ordered from after the machine instructions
/// seen so far to before them. /// seen so far to before them.
▲ Show 20 Lines • Show All 436 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveDebugValues.cpp

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Linespublic:
LiveDebugValues(); LiveDebugValues();
/// Tell the pass manager which passes we depend on and what /// Tell the pass manager which passes we depend on and what
/// information we preserve. /// information we preserve.
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
/// Print to ostream with a message. /// Print to ostream with a message.
void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V, void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V,
const VarLocMap &VarLocIDs, const char *msg, const VarLocMap &VarLocIDs, const char *msg,
raw_ostream &Out) const; raw_ostream &Out) const;
/// Calculate the liveness information for the given machine function. /// Calculate the liveness information for the given machine function.
▲ Show 20 Lines • Show All 288 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp

Show First 20 Lines • Show All 306 Lines • ▼ Show 20 Linesvoid MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
if (!HasPHI) if (!HasPHI)
Properties.set(MachineFunctionProperties::Property::NoPHIs); Properties.set(MachineFunctionProperties::Property::NoPHIs);
MF.setHasInlineAsm(HasInlineAsm); MF.setHasInlineAsm(HasInlineAsm);
if (isSSA(MF)) if (isSSA(MF))
Properties.set(MachineFunctionProperties::Property::IsSSA); Properties.set(MachineFunctionProperties::Property::IsSSA);
else else
Properties.clear(MachineFunctionProperties::Property::IsSSA); Properties.clear(MachineFunctionProperties::Property::IsSSA);
const MachineRegisterInfo &MRI = MF.getRegInfo();
if (MRI.getNumVirtRegs() == 0)
Properties.set(MachineFunctionProperties::Property::NoVRegs);
} }
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
auto It = Functions.find(MF.getName()); auto It = Functions.find(MF.getName());
if (It == Functions.end()) if (It == Functions.end())
return error(Twine("no machine function information for function '") + return error(Twine("no machine function information for function '") +
MF.getName() + "' in the MIR file"); MF.getName() + "' in the MIR file");
// TODO: Recreate the machine function. // TODO: Recreate the machine function.
const yaml::MachineFunction &YamlMF = *It->getValue(); const yaml::MachineFunction &YamlMF = *It->getValue();
if (YamlMF.Alignment) if (YamlMF.Alignment)
MF.setAlignment(YamlMF.Alignment); MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
if (YamlMF.AllVRegsAllocated)
MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
if (YamlMF.Legalized) if (YamlMF.Legalized)
MF.getProperties().set(MachineFunctionProperties::Property::Legalized); MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
if (YamlMF.RegBankSelected) if (YamlMF.RegBankSelected)
MF.getProperties().set( MF.getProperties().set(
MachineFunctionProperties::Property::RegBankSelected); MachineFunctionProperties::Property::RegBankSelected);
if (YamlMF.Selected) if (YamlMF.Selected)
MF.getProperties().set(MachineFunctionProperties::Property::Selected); MF.getProperties().set(MachineFunctionProperties::Property::Selected);
▲ Show 20 Lines • Show All 495 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
void MIRPrinter::print(const MachineFunction &MF) { void MIRPrinter::print(const MachineFunction &MF) {
initRegisterMaskIds(MF); initRegisterMaskIds(MF);
yaml::MachineFunction YamlMF; yaml::MachineFunction YamlMF;
YamlMF.Name = MF.getName(); YamlMF.Name = MF.getName();
YamlMF.Alignment = MF.getAlignment(); YamlMF.Alignment = MF.getAlignment();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::AllVRegsAllocated);
YamlMF.Legalized = MF.getProperties().hasProperty( YamlMF.Legalized = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Legalized); MachineFunctionProperties::Property::Legalized);
YamlMF.RegBankSelected = MF.getProperties().hasProperty( YamlMF.RegBankSelected = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::RegBankSelected); MachineFunctionProperties::Property::RegBankSelected);
YamlMF.Selected = MF.getProperties().hasProperty( YamlMF.Selected = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Selected); MachineFunctionProperties::Property::Selected);
▲ Show 20 Lines • Show All 848 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
void ClobberRegister(unsigned Reg); void ClobberRegister(unsigned Reg);
void CopyPropagateBlock(MachineBasicBlock &MBB); void CopyPropagateBlock(MachineBasicBlock &MBB);
bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def); bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
/// Candidates for deletion. /// Candidates for deletion.
▲ Show 20 Lines • Show All 304 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineFunction.cpp

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines AlignAllFunctions("align-all-functions",
cl::desc("Force the alignment of all functions."), cl::desc("Force the alignment of all functions."),
cl::init(0), cl::Hidden); cl::init(0), cl::Hidden);
void MachineFunctionInitializer::anchor() {} void MachineFunctionInitializer::anchor() {}
static const char *getPropertyName(MachineFunctionProperties::Property Prop) { static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
typedef MachineFunctionProperties::Property P; typedef MachineFunctionProperties::Property P;
switch(Prop) { switch(Prop) {
case P::AllVRegsAllocated: return "AllVRegsAllocated";
case P::IsSSA: return "IsSSA"; case P::IsSSA: return "IsSSA";
case P::Legalized: return "Legalized"; case P::Legalized: return "Legalized";
case P::NoPHIs: return "NoPHIs"; case P::NoPHIs: return "NoPHIs";
case P::NoVRegs: return "NoVRegs";
case P::RegBankSelected: return "RegBankSelected"; case P::RegBankSelected: return "RegBankSelected";
case P::Selected: return "Selected"; case P::Selected: return "Selected";
case P::TracksLiveness: return "TracksLiveness"; case P::TracksLiveness: return "TracksLiveness";
} }
llvm_unreachable("Invalid machine function property"); llvm_unreachable("Invalid machine function property");
} }
void MachineFunctionProperties::print(raw_ostream &OS) const { void MachineFunctionProperties::print(raw_ostream &OS) const {
▲ Show 20 Lines • Show All 929 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 308 Lines • ▼ Show 20 Lines for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
E = Indexes->MBBIndexEnd(); I != E; ++I) { E = Indexes->MBBIndexEnd(); I != E; ++I) {
assert(!Last.isValid() || I->first > Last); assert(!Last.isValid() || I->first > Last);
Last = I->first; Last = I->first;
} }
} }
void MachineVerifier::verifyProperties(const MachineFunction &MF) { void MachineVerifier::verifyProperties(const MachineFunction &MF) {
// If a pass has introduced virtual registers without clearing the // If a pass has introduced virtual registers without clearing the
// AllVRegsAllocated property (or set it without allocating the vregs) // NoVRegs property (or set it without allocating the vregs)
// then report an error. // then report an error.
if (MF.getProperties().hasProperty( if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::AllVRegsAllocated) && MachineFunctionProperties::Property::NoVRegs) &&
MRI->getNumVirtRegs()) { MRI->getNumVirtRegs())
report( report("Function has NoVRegs property but there are VReg operands", &MF);
"Function has AllVRegsAllocated property but there are VReg operands",
&MF);
}
} }
unsigned MachineVerifier::verify(MachineFunction &MF) { unsigned MachineVerifier::verify(MachineFunction &MF) {
foundErrors = 0; foundErrors = 0;
this->MF = &MF; this->MF = &MF;
TM = &MF.getTarget(); TM = &MF.getTarget();
TII = MF.getSubtarget().getInstrInfo(); TII = MF.getSubtarget().getInstrInfo();
▲ Show 20 Lines • Show All 1,767 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/PatchableFunction.cpp

Show All 26 Linesstruct PatchableFunction : public MachineFunctionPass {
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
PatchableFunction() : MachineFunctionPass(ID) { PatchableFunction() : MachineFunctionPass(ID) {
initializePatchableFunctionPass(*PassRegistry::getPassRegistry()); initializePatchableFunctionPass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
} }
/// Returns true if instruction \p MI will not result in actual machine code /// Returns true if instruction \p MI will not result in actual machine code
/// instructions. /// instructions.
static bool doesNotGeneratecode(const MachineInstr &MI) { static bool doesNotGeneratecode(const MachineInstr &MI) {
// TODO: Introduce an MCInstrDesc flag for this // TODO: Introduce an MCInstrDesc flag for this
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addPreserved<MachineDominatorTree>(); AU.addPreserved<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>(); AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>(); AU.addPreserved<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
private: private:
bool enablePostRAScheduler( bool enablePostRAScheduler(
const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel, const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode &Mode, TargetSubtargetInfo::AntiDepBreakMode &Mode,
▲ Show 20 Lines • Show All 596 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines explicit PEI(const TargetMachine *TM = nullptr) : MachineFunctionPass(ID) {
} }
} }
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
MachineFunctionProperties MFP; MachineFunctionProperties MFP;
if (UsesCalleeSaves) if (UsesCalleeSaves)
MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated); MFP.set(MachineFunctionProperties::Property::NoVRegs);
return MFP; return MFP;
} }
/// runOnMachineFunction - Insert prolog/epilog code and replace abstract /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
/// frame indexes with appropriate references. /// frame indexes with appropriate references.
/// ///
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
▲ Show 20 Lines • Show All 1,142 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines public:
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoPHIs); MachineFunctionProperties::Property::NoPHIs);
} }
MachineFunctionProperties getSetProperties() const override { MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
void AllocateBasicBlock(); void AllocateBasicBlock();
void handleThroughOperands(MachineInstr *MI, void handleThroughOperands(MachineInstr *MI,
SmallVectorImpl<unsigned> &VirtDead); SmallVectorImpl<unsigned> &VirtDead);
int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
▲ Show 20 Lines • Show All 949 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linespublic:
StackMapLiveness(); StackMapLiveness();
/// \brief Tell the pass manager which passes we depend on and what /// \brief Tell the pass manager which passes we depend on and what
/// information we preserve. /// information we preserve.
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
/// \brief Calculate the liveness information for the given machine function. /// \brief Calculate the liveness information for the given machine function.
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
private: private:
/// \brief Performs the actual liveness calculation for the function. /// \brief Performs the actual liveness calculation for the function.
bool calculateLiveness(MachineFunction &MF); bool calculateLiveness(MachineFunction &MF);
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/VirtRegMap.cpp

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Linespublic:
static char ID; static char ID;
VirtRegRewriter() : MachineFunctionPass(ID) {} VirtRegRewriter() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override; bool runOnMachineFunction(MachineFunction&) override;
MachineFunctionProperties getSetProperties() const override { MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
} // end anonymous namespace } // end anonymous namespace
char &llvm::VirtRegRewriterID = VirtRegRewriter::ID; char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter", INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
"Virtual Register Rewriter", false, false) "Virtual Register Rewriter", false, false)
▲ Show 20 Lines • Show All 280 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linespublic:
explicit AArch64A53Fix835769() : MachineFunctionPass(ID) { explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {
initializeAArch64A53Fix835769Pass(*PassRegistry::getPassRegistry()); initializeAArch64A53Fix835769Pass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Workaround A53 erratum 835769 pass"; return "Workaround A53 erratum 835769 pass";
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Linespublic:
explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) { explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {
initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry()); initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "A57 FP Anti-dependency breaker"; return "A57 FP Anti-dependency breaker";
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
▲ Show 20 Lines • Show All 600 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Linesstruct AArch64CollectLOH : public MachineFunctionPass {
AArch64CollectLOH() : MachineFunctionPass(ID) { AArch64CollectLOH() : MachineFunctionPass(ID) {
initializeAArch64CollectLOHPass(*PassRegistry::getPassRegistry()); initializeAArch64CollectLOHPass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return AARCH64_COLLECT_LOH_NAME; return AARCH64_COLLECT_LOH_NAME;
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll(); AU.setPreservesAll();
▲ Show 20 Lines • Show All 918 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

Show All 40 Lines explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
initializeAArch64DeadRegisterDefinitionsPass( initializeAArch64DeadRegisterDefinitionsPass(
*PassRegistry::getPassRegistry()); *PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Linesstruct AArch64LoadStoreOpt : public MachineFunctionPass {
bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI); bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt); bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return AARCH64_LOAD_STORE_OPT_NAME; return AARCH64_LOAD_STORE_OPT_NAME;
} }
}; };
char AArch64LoadStoreOpt::ID = 0; char AArch64LoadStoreOpt::ID = 0;
} // namespace } // namespace
▲ Show 20 Lines • Show All 1,741 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linespublic:
AArch64RedundantCopyElimination() : MachineFunctionPass(ID) { AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
initializeAArch64RedundantCopyEliminationPass( initializeAArch64RedundantCopyEliminationPass(
*PassRegistry::getPassRegistry()); *PassRegistry::getPassRegistry());
} }
bool optimizeCopy(MachineBasicBlock *MBB); bool optimizeCopy(MachineBasicBlock *MBB);
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "AArch64 Redundant Copy Elimination"; return "AArch64 Redundant Copy Elimination";
} }
}; };
char AArch64RedundantCopyElimination::ID = 0; char AArch64RedundantCopyElimination::ID = 0;
} }
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Linesnamespace {
public: public:
static char ID; static char ID;
ARMConstantIslands() : MachineFunctionPass(ID) {} ARMConstantIslands() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "ARM constant island placement and branch shortening pass"; return "ARM constant island placement and branch shortening pass";
} }
private: private:
void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs); void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
▲ Show 20 Lines • Show All 1,966 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines public:
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
const ARMSubtarget *STI; const ARMSubtarget *STI;
ARMFunctionInfo *AFI; ARMFunctionInfo *AFI;
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "ARM pseudo instruction expansion pass"; return "ARM pseudo instruction expansion pass";
} }
private: private:
void TransferImpOps(MachineInstr &OldMI, void TransferImpOps(MachineInstr &OldMI,
▲ Show 20 Lines • Show All 1,625 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines struct ARMLoadStoreOpt : public MachineFunctionPass {
bool LiveRegsValid; bool LiveRegsValid;
bool RegClassInfoValid; bool RegClassInfoValid;
bool isThumb1, isThumb2; bool isThumb1, isThumb2;
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return ARM_LOAD_STORE_OPT_NAME; return ARM_LOAD_STORE_OPT_NAME;
} }
private: private:
/// A set of load/store MachineInstrs with same base register sorted by /// A set of load/store MachineInstrs with same base register sorted by
▲ Show 20 Lines • Show All 2,285 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMOptimizeBarriersPass.cpp

Show All 23 Lines
public: public:
static char ID; static char ID;
ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {} ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "optimise barriers pass"; return "optimise barriers pass";
} }
}; };
char ARMOptimizeBarriersPass::ID = 0; char ARMOptimizeBarriersPass::ID = 0;
} }
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

Show All 32 Lines public:
const Thumb2InstrInfo *TII; const Thumb2InstrInfo *TII;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
ARMFunctionInfo *AFI; ARMFunctionInfo *AFI;
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Thumb IT blocks insertion pass"; return "Thumb IT blocks insertion pass";
} }
private: private:
bool MoveCopyOutOfITBlock(MachineInstr *MI, bool MoveCopyOutOfITBlock(MachineInstr *MI,
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines public:
const Thumb2InstrInfo *TII; const Thumb2InstrInfo *TII;
const ARMSubtarget *STI; const ARMSubtarget *STI;
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Thumb2 instruction size reduction pass"; return "Thumb2 instruction size reduction pass";
} }
private: private:
/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable. /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
▲ Show 20 Lines • Show All 943 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linespublic:
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon CFG Optimizer"; return "Hexagon CFG Optimizer";
} }
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
char HexagonCFGOptimizer::ID = 0; char HexagonCFGOptimizer::ID = 0;
static bool IsConditionalBranch(int Opc) { static bool IsConditionalBranch(int Opc) {
switch (Opc) { switch (Opc) {
▲ Show 20 Lines • Show All 193 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linespublic:
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon Copy-To-Combine Pass"; return "Hexagon Copy-To-Combine Pass";
} }
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1, MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,
bool AllowC64); bool AllowC64);
void findPotentialNewifiableTFRs(MachineBasicBlock &); void findPotentialNewifiableTFRs(MachineBasicBlock &);
▲ Show 20 Lines • Show All 789 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines public:
HexagonFixupHwLoops() : MachineFunctionPass(ID) { HexagonFixupHwLoops() : MachineFunctionPass(ID) {
initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry()); initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon Hardware Loop Fixup"; return "Hexagon Hardware Loop Fixup";
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp

Show First 20 Lines • Show All 176 Lines • ▼ Show 20 Lines public:
static char ID; static char ID;
HexagonCallFrameInformation() : MachineFunctionPass(ID) { HexagonCallFrameInformation() : MachineFunctionPass(ID) {
PassRegistry &PR = *PassRegistry::getPassRegistry(); PassRegistry &PR = *PassRegistry::getPassRegistry();
initializeHexagonCallFrameInformationPass(PR); initializeHexagonCallFrameInformationPass(PR);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
char HexagonCallFrameInformation::ID = 0; char HexagonCallFrameInformation::ID = 0;
} }
bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) { bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering(); auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
▲ Show 20 Lines • Show All 2,232 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines const char *getPassName() const override {
return "Hexagon generate mux instructions"; return "Hexagon generate mux instructions";
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
const HexagonInstrInfo *HII; const HexagonInstrInfo *HII;
const HexagonRegisterInfo *HRI; const HexagonRegisterInfo *HRI;
struct CondsetInfo { struct CondsetInfo {
unsigned PredR; unsigned PredR;
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines public:
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon NewValueJump"; return "Hexagon NewValueJump";
} }
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
/// \brief A handle to the branch probability pass. /// \brief A handle to the branch probability pass.
const MachineBranchProbabilityInfo *MBPI; const MachineBranchProbabilityInfo *MBPI;
bool isNewValueJumpCandidate(const MachineInstr &MI) const; bool isNewValueJumpCandidate(const MachineInstr &MI) const;
}; };
▲ Show 20 Lines • Show All 617 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines public:
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon RDF optimizations"; return "Hexagon RDF optimizations";
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
static char ID; static char ID;
private: private:
MachineDominatorTree *MDT; MachineDominatorTree *MDT;
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
}; };
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {
initializeHexagonSplitConst32AndConst64Pass(R); initializeHexagonSplitConst32AndConst64Pass(R);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon Split Const32s and Const64s"; return "Hexagon Split Const32s and Const64s";
} }
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
}; };
} }
char HexagonSplitConst32AndConst64::ID = 0; char HexagonSplitConst32AndConst64::ID = 0;
INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata", INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata",
"Hexagon Split Const32s and Const64s", false, false) "Hexagon Split Const32s and Const64s", false, false)
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "Hexagon Packetizer"; return "Hexagon Packetizer";
} }
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
const HexagonInstrInfo *HII; const HexagonInstrInfo *HII;
const HexagonRegisterInfo *HRI; const HexagonRegisterInfo *HRI;
}; };
char HexagonPacketizer::ID = 0; char HexagonPacketizer::ID = 0;
▲ Show 20 Lines • Show All 1,594 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines bool runOnMachineFunction(MachineFunction &MF) override {
for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE; for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
++FI) ++FI)
Changed |= runOnMachineBasicBlock(*FI); Changed |= runOnMachineBasicBlock(*FI);
return Changed; return Changed;
} }
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
void insertDefsUses(MachineBasicBlock::instr_iterator MI, void insertDefsUses(MachineBasicBlock::instr_iterator MI,
SmallSet<unsigned, 32> &RegDefs, SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses); SmallSet<unsigned, 32> &RegUses);
bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg); bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
▲ Show 20 Lines • Show All 192 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linespublic:
const char *getPassName() const override { const char *getPassName() const override {
return "Lanai load / store optimization pass"; return "Lanai load / store optimization pass";
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB, MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB,
const MbbIterator &MemInstr, const MbbIterator &MemInstr,
bool Decrement); bool Decrement);
void insertMergedInstruction(MachineBasicBlock *BB, void insertMergedInstruction(MachineBasicBlock *BB,
const MbbIterator &MemInstr, const MbbIterator &MemInstr,
▲ Show 20 Lines • Show All 345 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp

Show All 35 Lines struct MSP430BSel : public MachineFunctionPass {
/// BlockSizes - The sizes of the basic blocks in the function. /// BlockSizes - The sizes of the basic blocks in the function.
std::vector<unsigned> BlockSizes; std::vector<unsigned> BlockSizes;
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "MSP430 Branch Selector"; return "MSP430 Branch Selector";
} }
}; };
char MSP430BSel::ID = 0; char MSP430BSel::ID = 0;
} }
▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Lines public:
const char *getPassName() const override { const char *getPassName() const override {
return "Mips Constant Islands"; return "Mips Constant Islands";
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs); void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI); CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
unsigned getCPELogAlign(const MachineInstr &CPEMI); unsigned getCPELogAlign(const MachineInstr &CPEMI);
void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs); void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
unsigned getOffsetOf(MachineInstr *MI) const; unsigned getOffsetOf(MachineInstr *MI) const;
unsigned getUserOffset(CPUser&) const; unsigned getUserOffset(CPUser&) const;
▲ Show 20 Lines • Show All 1,321 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Lines bool runOnMachineFunction(MachineFunction &F) override {
if (Changed) if (Changed)
F.getRegInfo().invalidateLiveness(); F.getRegInfo().invalidateLiveness();
return Changed; return Changed;
} }
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBranchProbabilityInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
private: private:
▲ Show 20 Lines • Show All 677 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linespublic:
MipsHazardSchedule() : MachineFunctionPass(ID) {} MipsHazardSchedule() : MachineFunctionPass(ID) {}
const char *getPassName() const override { return "Mips Hazard Schedule"; } const char *getPassName() const override { return "Mips Hazard Schedule"; }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
static char ID; static char ID;
}; };
char MipsHazardSchedule::ID = 0; char MipsHazardSchedule::ID = 0;
} // end of anonymous namespace } // end of anonymous namespace
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines public:
const char *getPassName() const override { const char *getPassName() const override {
return "Mips Long Branch"; return "Mips Long Branch";
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
void splitMBB(MachineBasicBlock *MBB); void splitMBB(MachineBasicBlock *MBB);
void initMBBInfo(); void initMBBInfo();
int64_t computeOffset(const MachineInstr *Br); int64_t computeOffset(const MachineInstr *Br);
void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL, void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
MachineBasicBlock *MBBOpnd); MachineBasicBlock *MBBOpnd);
▲ Show 20 Lines • Show All 449 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines struct PPCBSel : public MachineFunctionPass {
/// BlockSizes - The sizes of the basic blocks in the function. /// BlockSizes - The sizes of the basic blocks in the function.
std::vector<unsigned> BlockSizes; std::vector<unsigned> BlockSizes;
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "PowerPC Branch Selector"; return "PowerPC Branch Selector";
} }
}; };
char PPCBSel::ID = 0; char PPCBSel::ID = 0;
} }
▲ Show 20 Lines • Show All 181 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp

Show First 20 Lines • Show All 190 Lines • ▼ Show 20 Lines bool runOnMachineFunction(MachineFunction &MF) override {
Changed = true; Changed = true;
} }
return Changed; return Changed;
} }
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };
} }
INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE, INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
"PowerPC Early-Return Creation", false, false) "PowerPC Early-Return Creation", false, false)
char PPCEarlyReturn::ID = 0; char PPCEarlyReturn::ID = 0;
FunctionPass* FunctionPass*
llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); } llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }

llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines bool runOnMachineFunction(MachineFunction &F) override {
for (MachineFunction::iterator FI = F.begin(), FE = F.end(); for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI) FI != FE; ++FI)
Changed |= runOnMachineBasicBlock(*FI); Changed |= runOnMachineBasicBlock(*FI);
return Changed; return Changed;
} }
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
void insertCallDefsUses(MachineBasicBlock::iterator MI, void insertCallDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs, SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses); SmallSet<unsigned, 32>& RegUses);
void insertDefsUses(MachineBasicBlock::iterator MI, void insertDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs, SmallSet<unsigned, 32>& RegDefs,
▲ Show 20 Lines • Show All 439 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linespublic:
const char *getPassName() const override { const char *getPassName() const override {
return "SystemZ Comparison Elimination"; return "SystemZ Comparison Elimination";
} }
bool processBlock(MachineBasicBlock &MBB); bool processBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
Reference getRegReferences(MachineInstr &MI, unsigned Reg); Reference getRegReferences(MachineInstr &MI, unsigned Reg);
bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare, bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
SmallVectorImpl<MachineInstr *> &CCUsers); SmallVectorImpl<MachineInstr *> &CCUsers);
bool convertToLoadAndTest(MachineInstr &MI); bool convertToLoadAndTest(MachineInstr &MI);
bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare, bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
▲ Show 20 Lines • Show All 434 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Linespublic:
const char *getPassName() const override { const char *getPassName() const override {
return "SystemZ Long Branch"; return "SystemZ Long Branch";
} }
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
void skipNonTerminators(BlockPosition &Position, MBBInfo &Block); void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator, void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
bool AssumeRelaxed); bool AssumeRelaxed);
TerminatorInfo describeTerminator(MachineInstr &MI); TerminatorInfo describeTerminator(MachineInstr &MI);
uint64_t initMBBInfo(); uint64_t initMBBInfo();
▲ Show 20 Lines • Show All 312 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp

Show All 31 Linespublic:
const char *getPassName() const override { const char *getPassName() const override {
return "SystemZ Instruction Shortening"; return "SystemZ Instruction Shortening";
} }
bool processBlock(MachineBasicBlock &MBB); bool processBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F) override; bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH); bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
bool shortenOn0(MachineInstr &MI, unsigned Opcode); bool shortenOn0(MachineInstr &MI, unsigned Opcode);
bool shortenOn01(MachineInstr &MI, unsigned Opcode); bool shortenOn01(MachineInstr &MI, unsigned Opcode);
bool shortenOn001(MachineInstr &MI, unsigned Opcode); bool shortenOn001(MachineInstr &MI, unsigned Opcode);
bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode); bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
▲ Show 20 Lines • Show All 237 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

Show First 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
void WebAssemblyPassConfig::addPostRegAlloc() { void WebAssemblyPassConfig::addPostRegAlloc() {
// TODO: The following CodeGen passes don't currently support code containing // TODO: The following CodeGen passes don't currently support code containing
// virtual registers. Consider removing their restrictions and re-enabling // virtual registers. Consider removing their restrictions and re-enabling
// them. // them.
// Has no asserts of its own, but was not written to handle virtual regs. // Has no asserts of its own, but was not written to handle virtual regs.
disablePass(&ShrinkWrapID); disablePass(&ShrinkWrapID);
// These functions all require the AllVRegsAllocated property. // These functions all require the NoVRegs property.
disablePass(&MachineCopyPropagationID); disablePass(&MachineCopyPropagationID);
disablePass(&PostRASchedulerID); disablePass(&PostRASchedulerID);
disablePass(&FuncletLayoutID); disablePass(&FuncletLayoutID);
disablePass(&StackMapLivenessID); disablePass(&StackMapLivenessID);
disablePass(&LiveDebugValuesID); disablePass(&LiveDebugValuesID);
disablePass(&PatchableFunctionID); disablePass(&PatchableFunctionID);
TargetPassConfig::addPostRegAlloc(); TargetPassConfig::addPostRegAlloc();
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linespublic:
const X86RegisterInfo *TRI; const X86RegisterInfo *TRI;
const X86MachineFunctionInfo *X86FI; const X86MachineFunctionInfo *X86FI;
const X86FrameLowering *X86FL; const X86FrameLowering *X86FL;
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "X86 pseudo instruction expansion pass"; return "X86 pseudo instruction expansion pass";
} }
private: private:
bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Linespublic:
/// Loop over all of the basic blocks, replacing byte and word instructions by /// Loop over all of the basic blocks, replacing byte and word instructions by
/// equivalent 32 bit instructions where performance or code size can be /// equivalent 32 bit instructions where performance or code size can be
/// improved. /// improved.
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
MachineFunction *MF; MachineFunction *MF;
/// Machine instruction info used throughout the class. /// Machine instruction info used throughout the class.
const X86InstrInfo *TII; const X86InstrInfo *TII;
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Linespublic:
/// \brief Loop over all of the basic blocks, /// \brief Loop over all of the basic blocks,
/// replacing instructions by equivalent LEA instructions /// replacing instructions by equivalent LEA instructions
/// if needed and when possible. /// if needed and when possible.
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
// This pass runs after regalloc and doesn't support VReg operands. // This pass runs after regalloc and doesn't support VReg operands.
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
private: private:
MachineFunction *MF; MachineFunction *MF;
const X86InstrInfo *TII; // Machine instruction info. const X86InstrInfo *TII; // Machine instruction info.
bool OptIncDec; bool OptIncDec;
bool OptLEA; bool OptLEA;
}; };
▲ Show 20 Lines • Show All 312 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addPreservedID(MachineDominatorsID); AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { return "X86 FP Stackifier"; } const char *getPassName() const override { return "X86 FP Stackifier"; }
private: private:
const TargetInstrInfo *TII; // Machine instruction info. const TargetInstrInfo *TII; // Machine instruction info.
// Two CFG edges are related if they leave the same block, or enter the same // Two CFG edges are related if they leave the same block, or enter the same
▲ Show 20 Lines • Show All 1,572 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines struct PadShortFunc : public MachineFunctionPass {
static char ID; static char ID;
PadShortFunc() : MachineFunctionPass(ID) PadShortFunc() : MachineFunctionPass(ID)
, Threshold(4), STI(nullptr), TII(nullptr) {} , Threshold(4), STI(nullptr), TII(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "X86 Atom pad short functions"; return "X86 Atom pad short functions";
} }
private: private:
void findReturns(MachineBasicBlock *MBB, void findReturns(MachineBasicBlock *MBB,
▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp

Show All 34 Linesnamespace {
class VZeroUpperInserter : public MachineFunctionPass { class VZeroUpperInserter : public MachineFunctionPass {
public: public:
VZeroUpperInserter() : MachineFunctionPass(ID) {} VZeroUpperInserter() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override {return "X86 vzeroupper inserter";} const char *getPassName() const override {return "X86 vzeroupper inserter";}
private: private:
void processBasicBlock(MachineBasicBlock &MBB); void processBasicBlock(MachineBasicBlock &MBB);
void insertVZeroUpper(MachineBasicBlock::iterator I, void insertVZeroUpper(MachineBasicBlock::iterator I,
MachineBasicBlock &MBB); MachineBasicBlock &MBB);
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp

Show All 23 Lines
namespace { namespace {
struct XCoreFTAOElim : public MachineFunctionPass { struct XCoreFTAOElim : public MachineFunctionPass {
static char ID; static char ID;
XCoreFTAOElim() : MachineFunctionPass(ID) {} XCoreFTAOElim() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &Fn) override; bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated); MachineFunctionProperties::Property::NoVRegs);
} }
const char *getPassName() const override { const char *getPassName() const override {
return "XCore FRAME_TO_ARGS_OFFSET Elimination"; return "XCore FRAME_TO_ARGS_OFFSET Elimination";
} }
}; };
char XCoreFTAOElim::ID = 0; char XCoreFTAOElim::ID = 0;
} }
Show All 26 Lines

llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir

Show All 22 Lines--- |
attributes #0 = { nounwind } attributes #0 = { nounwind }
... ...
--- ---
name: promote-load-from-store name: promote-load-from-store
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: false tracksRegLiveness: false
liveins: liveins:
- { reg: '%x0' } - { reg: '%x0' }
- { reg: '%w1' } - { reg: '%w1' }
frameInfo: frameInfo:
isFrameAddressTaken: false isFrameAddressTaken: false
isReturnAddressTaken: false isReturnAddressTaken: false
hasStackMap: false hasStackMap: false
Show All 38 Lines
... ...
# CHECK-LABEL: name: promote-load-from-store # CHECK-LABEL: name: promote-load-from-store
# CHECK: STRWui killed %w1 # CHECK: STRWui killed %w1
# CHECK: UBFMWri %w1 # CHECK: UBFMWri %w1
--- ---
name: store-pair name: store-pair
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: false tracksRegLiveness: false
liveins: liveins:
- { reg: '%x0' } - { reg: '%x0' }
- { reg: '%w1' } - { reg: '%w1' }
frameInfo: frameInfo:
isFrameAddressTaken: false isFrameAddressTaken: false
isReturnAddressTaken: false isReturnAddressTaken: false
hasStackMap: false hasStackMap: false
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir

Show All 9 Lines define i32 @test_mov_0() {
ret i32 42 ret i32 42
} }
... ...
--- ---
name: test_mov_0 name: test_mov_0
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: false tracksRegLiveness: false
frameInfo: frameInfo:
isFrameAddressTaken: false isFrameAddressTaken: false
isReturnAddressTaken: false isReturnAddressTaken: false
hasStackMap: false hasStackMap: false
hasPatchPoint: false hasPatchPoint: false
stackSize: 0 stackSize: 0
offsetAdjustment: 0 offsetAdjustment: 0
Show All 17 Lines

llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines--- |
!33 = !DILocation(line: 14, scope: !4) !33 = !DILocation(line: 14, scope: !4)
!34 = !DILocation(line: 15, scope: !4) !34 = !DILocation(line: 15, scope: !4)
... ...
--- ---
name: f name: f
alignment: 1 alignment: 1
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0' } - { reg: '%r0' }
- { reg: '%r1' } - { reg: '%r1' }
- { reg: '%r2' } - { reg: '%r2' }
- { reg: '%r3' } - { reg: '%r3' }
calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
'%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir

# RUN: llc -march=hexagon -run-pass if-converter %s -o - | FileCheck %s # RUN: llc -march=hexagon -run-pass if-converter %s -o - | FileCheck %s
# Make sure that the necessary implicit uses are added to predicated # Make sure that the necessary implicit uses are added to predicated
# instructions. # instructions.
# CHECK-LABEL: name: foo # CHECK-LABEL: name: foo
--- | --- |
define void @foo() { define void @foo() {
ret void ret void
} }
... ...
--- ---
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: %r0, %r2, %p1 liveins: %r0, %r2, %p1
J2_jumpf %p1, %bb.1, implicit-def %pc J2_jumpf %p1, %bb.1, implicit-def %pc
J2_jump %bb.2, implicit-def %pc J2_jump %bb.2, implicit-def %pc
bb.1: bb.1:
successors: %bb.3 successors: %bb.3
Show All 18 Lines

llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir

Show All 27 Lines
# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to # have to be relaxed (note that we're using -aarch64-tbz-offset-bits to
# constrain the range that can be reached with the TBNZW to something smaller # constrain the range that can be reached with the TBNZW to something smaller
# than what TLSDESC_CALLSEQ is lowered to). # than what TLSDESC_CALLSEQ is lowered to).
# CHECK: TBZW killed %w0, 0, %bb.1.true # CHECK: TBZW killed %w0, 0, %bb.1.true
# CHECK: B %bb.2.false # CHECK: B %bb.2.false
name: test_tlsdesc_callseq_length name: test_tlsdesc_callseq_length
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: false tracksRegLiveness: false
liveins: liveins:
- { reg: '%w0' } - { reg: '%w0' }
frameInfo: frameInfo:
isFrameAddressTaken: false isFrameAddressTaken: false
isReturnAddressTaken: false isReturnAddressTaken: false
hasStackMap: false hasStackMap: false
hasPatchPoint: false hasPatchPoint: false
Show All 37 Lines

llvm/trunk/test/CodeGen/MIR/AArch64/machine-dead-copy.mir

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
--- | --- |
define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a } define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a } define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a } define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a } define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a }
declare i32 @foo(i32) declare i32 @foo(i32)
... ...
--- ---
# The first copy is dead copy which is not used. # The first copy is dead copy which is not used.
# CHECK-LABEL: name: copyprop1 # CHECK-LABEL: name: copyprop1
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NOT: %w20 = COPY # CHECK-NOT: %w20 = COPY
name: copyprop1 name: copyprop1
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
liveins: %w0, %w1 liveins: %w0, %w1
%w20 = COPY %w1 %w20 = COPY %w1
BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0
... ...
--- ---
# The first copy is not a dead copy which is used in the second copy after the # The first copy is not a dead copy which is used in the second copy after the
# call. # call.
# CHECK-LABEL: name: copyprop2 # CHECK-LABEL: name: copyprop2
# CHECK: bb.0: # CHECK: bb.0:
# CHECK: %w20 = COPY # CHECK: %w20 = COPY
name: copyprop2 name: copyprop2
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
liveins: %w0, %w1 liveins: %w0, %w1
%w20 = COPY %w1 %w20 = COPY %w1
BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
%w0 = COPY %w20 %w0 = COPY %w20
RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0
... ...
--- ---
# Both the first and second copy are dead copies which are not used. # Both the first and second copy are dead copies which are not used.
# CHECK-LABEL: name: copyprop3 # CHECK-LABEL: name: copyprop3
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NOT: COPY # CHECK-NOT: COPY
name: copyprop3 name: copyprop3
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
liveins: %w0, %w1 liveins: %w0, %w1
%w20 = COPY %w1 %w20 = COPY %w1
BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
%w20 = COPY %w0 %w20 = COPY %w0
RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0
... ...
# The second copy is removed as a NOP copy, after then the first copy become # The second copy is removed as a NOP copy, after then the first copy become
# dead which should be removed as well. # dead which should be removed as well.
# CHECK-LABEL: name: copyprop4 # CHECK-LABEL: name: copyprop4
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NOT: COPY # CHECK-NOT: COPY
name: copyprop4 name: copyprop4
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
liveins: %w0, %w1 liveins: %w0, %w1
%w20 = COPY %w0 %w20 = COPY %w0
%w0 = COPY %w20 %w0 = COPY %w20
BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0
... ...

llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines--- |
!33 = !DILocation(line: 14, scope: !4) !33 = !DILocation(line: 14, scope: !4)
!34 = !DILocation(line: 15, scope: !4) !34 = !DILocation(line: 15, scope: !4)
... ...
--- ---
name: f name: f
alignment: 1 alignment: 1
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0' } - { reg: '%r0' }
- { reg: '%r1' } - { reg: '%r1' }
- { reg: '%r2' } - { reg: '%r2' }
- { reg: '%r3' } - { reg: '%r3' }
calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
'%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir

# RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s # RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s
--- | --- |
declare void @check(i64, i32, i32, i64) declare void @check(i64, i32, i32, i64)
define void @foo() { define void @foo() {
ret void ret void
} }
... ...
--- ---
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
successors: successors:
liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23 liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23
%r2 = A2_add %r23, killed %r17 %r2 = A2_add %r23, killed %r17
%r6 = M2_mpyi %r16, %r16 %r6 = M2_mpyi %r16, %r16
%r22 = M2_accii %r22, killed %r2, 2 %r22 = M2_accii %r22, killed %r2, 2
%r7 = A2_tfrsi 12345678 %r7 = A2_tfrsi 12345678
Show All 14 Lines

llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines--- |
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}
... ...
--- ---
name: test0a name: test0a
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
Show All 28 Lines bb.0.entry:
%rv = COPY %5 %rv = COPY %5
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test0b name: test0b
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
liveins: liveins:
Show All 26 Lines bb.0.entry:
%rv = COPY %4 %rv = COPY %4
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test1a name: test1a
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
Show All 30 Lines bb.0.entry:
%rv = COPY %5 %rv = COPY %5
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test1b name: test1b
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
Show All 30 Lines bb.0.entry:
%rv = COPY %5 %rv = COPY %5
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test2a name: test2a
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
Show All 30 Lines bb.0.entry:
%rv = COPY %5 %rv = COPY %5
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test2b name: test2b
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
Show All 30 Lines bb.0.entry:
%rv = COPY %5 %rv = COPY %5
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test3 name: test3
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
Show All 30 Lines bb.0.entry:
%rv = COPY %5 %rv = COPY %5
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: test4 name: test4
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines bb.4.return:
%rv = COPY %0 %rv = COPY %0
RET implicit %rca, implicit %rv RET implicit %rca, implicit %rv
... ...
--- ---
name: testBB name: testBB
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
- { id: 5, class: gpr } - { id: 5, class: gpr }
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir

Show All 38 Lines--- |
attributes #0 = { nounwind "target-cpu"="pwr7" } attributes #0 = { nounwind "target-cpu"="pwr7" }
attributes #1 = { nounwind } attributes #1 = { nounwind }
... ...
--- ---
name: mm_update_next_owner name: mm_update_next_owner
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%x3' } - { reg: '%x3' }
- { reg: '%x4' } - { reg: '%x4' }
calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16', calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16',
'%f17', '%f18', '%f19', '%f20', '%f21', '%f22', '%f17', '%f18', '%f19', '%f20', '%f21', '%f22',
'%f23', '%f24', '%f25', '%f26', '%f27', '%f28', '%f23', '%f24', '%f25', '%f26', '%f27', '%f28',
'%f29', '%f30', '%f31', '%r14', '%r15', '%r16', '%f29', '%f30', '%f31', '%r14', '%r15', '%r16',
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir

Show All 20 Lines--- |
!0 = !{i32 1, !"PIC Level", i32 2} !0 = !{i32 1, !"PIC Level", i32 2}
... ...
--- ---
name: test1 name: test1
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
isFrameAddressTaken: false isFrameAddressTaken: false
isReturnAddressTaken: false isReturnAddressTaken: false
hasStackMap: false hasStackMap: false
hasPatchPoint: false hasPatchPoint: false
stackSize: 64 stackSize: 64
offsetAdjustment: 0 offsetAdjustment: 0
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir

Show All 26 Lines--- |
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }
... ...
--- ---
name: fn1 name: fn1
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: g8rc } - { id: 0, class: g8rc }
- { id: 1, class: g8rc } - { id: 1, class: g8rc }
- { id: 2, class: g8rc } - { id: 2, class: g8rc }
- { id: 3, class: g8rc } - { id: 3, class: g8rc }
- { id: 4, class: g8rc } - { id: 4, class: g8rc }
- { id: 5, class: g8rc } - { id: 5, class: g8rc }
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir

Show All 13 Lines--- |
false: false:
ret void ret void
} }
... ...
--- ---
name: foo name: foo
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %edi liveins: %edi
successors: %bb.1.false successors: %bb.1.false
NOOP implicit-def %al NOOP implicit-def %al
Show All 36 Lines

llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir

Show All 32 Lines--- |
define i16 @test_movw_impdef_gr64(i16 %a0) { define i16 @test_movw_impdef_gr64(i16 %a0) {
ret i16 %a0 ret i16 %a0
} }
... ...
--- ---
name: test_movb_killed name: test_movb_killed
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %dil ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
%al = MOV8rr killed %dil %al = MOV8rr killed %dil
RETQ killed %al RETQ killed %al
... ...
--- ---
name: test_movb_impuse name: test_movb_impuse
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %dil ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
%al = MOV8rr %dil, implicit %edi %al = MOV8rr %dil, implicit %edi
RETQ killed %al RETQ killed %al
... ...
--- ---
name: test_movb_impdef_gr64 name: test_movb_impdef_gr64
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax ; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
%al = MOV8rr %dil, implicit-def %rax %al = MOV8rr %dil, implicit-def %rax
RETQ killed %al RETQ killed %al
... ...
--- ---
name: test_movb_impdef_gr32 name: test_movb_impdef_gr32
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %dil ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
%al = MOV8rr %dil, implicit-def %eax %al = MOV8rr %dil, implicit-def %eax
RETQ killed %al RETQ killed %al
... ...
--- ---
name: test_movb_impdef_gr16 name: test_movb_impdef_gr16
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %dil ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
%al = MOV8rr %dil, implicit-def %ax %al = MOV8rr %dil, implicit-def %ax
RETQ killed %al RETQ killed %al
... ...
--- ---
name: test_movw_impdef_gr32 name: test_movw_impdef_gr32
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %di ; CHECK: %eax = MOV32rr undef %edi, implicit %di
%ax = MOV16rr %di, implicit-def %eax %ax = MOV16rr %di, implicit-def %eax
RETQ killed %ax RETQ killed %ax
... ...
--- ---
name: test_movw_impdef_gr64 name: test_movw_impdef_gr64
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %edi liveins: %edi
; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax ; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
%ax = MOV16rr %di, implicit-def %rax %ax = MOV16rr %di, implicit-def %rax
RETQ killed %ax RETQ killed %ax
... ...

llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines--- |
} }
!0 = !{} !0 = !{}
... ...
--- ---
name: imp_null_check_with_bitwise_op_0 name: imp_null_check_with_bitwise_op_0
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
alignment: 4 alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %eax = MOV32ri 2200000 # CHECK: %eax = MOV32ri 2200000
# CHECK-NEXT: %eax = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) # CHECK-NEXT: %eax = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
Show All 26 Linesbody: |
bb.4.ret_100: bb.4.ret_100:
%eax = MOV32ri 100 %eax = MOV32ri 100
RET 0, %eax RET 0, %eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_1 name: imp_null_check_with_bitwise_op_1
alignment: 4 alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
- { reg: '%rdx' } - { reg: '%rdx' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr) # CHECK: %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
# CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags # CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags
Show All 31 Lines bb.4.ret_100:
%eax = MOV32ri 100 %eax = MOV32ri 100
RET 0, %eax RET 0, %eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_2 name: imp_null_check_with_bitwise_op_2
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
alignment: 4 alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags # CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags # CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
Show All 27 Lines bb.4.ret_100:
%eax = MOV32ri 100 %eax = MOV32ri 100
RET 0, %eax RET 0, %eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_3 name: imp_null_check_with_bitwise_op_3
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
alignment: 4 alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags # CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags # CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
Show All 30 Lines

llvm/trunk/test/CodeGen/X86/machine-copy-prop.mir

Show All 19 Lines
# the kill flag of intermediate instructions. # the kill flag of intermediate instructions.
# CHECK-LABEL: name: copyprop_remove_kill0 # CHECK-LABEL: name: copyprop_remove_kill0
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rdi # CHECK-NEXT: %rax = COPY %rdi
# CHECK-NEXT: NOOP implicit %rdi # CHECK-NEXT: NOOP implicit %rdi
# CHECK-NOT: COPY # CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop_remove_kill0 name: copyprop_remove_kill0
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rdi %rax = COPY %rdi
NOOP implicit killed %rdi NOOP implicit killed %rdi
%rdi = COPY %rax %rdi = COPY %rax
NOOP implicit %rax, implicit %rdi NOOP implicit %rax, implicit %rdi
... ...
--- ---
# The second copy is redundant and will be removed, check that we also remove # The second copy is redundant and will be removed, check that we also remove
# the kill flag of intermediate instructions. # the kill flag of intermediate instructions.
# CHECK-LABEL: name: copyprop_remove_kill1 # CHECK-LABEL: name: copyprop_remove_kill1
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rdi # CHECK-NEXT: %rax = COPY %rdi
# CHECK-NEXT: NOOP implicit %edi # CHECK-NEXT: NOOP implicit %edi
# CHECK-NOT: COPY # CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop_remove_kill1 name: copyprop_remove_kill1
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rdi %rax = COPY %rdi
NOOP implicit killed %edi NOOP implicit killed %edi
%rdi = COPY %rax %rdi = COPY %rax
NOOP implicit %rax, implicit %rdi NOOP implicit %rax, implicit %rdi
... ...
--- ---
# The second copy is redundant and will be removed, check that we also remove # The second copy is redundant and will be removed, check that we also remove
# the kill flag of intermediate instructions. # the kill flag of intermediate instructions.
# CHECK-LABEL: name: copyprop_remove_kill2 # CHECK-LABEL: name: copyprop_remove_kill2
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %ax = COPY %di # CHECK-NEXT: %ax = COPY %di
# CHECK-NEXT: NOOP implicit %rdi # CHECK-NEXT: NOOP implicit %rdi
# CHECK-NOT: COPY # CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop_remove_kill2 name: copyprop_remove_kill2
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%ax = COPY %di %ax = COPY %di
NOOP implicit killed %rdi NOOP implicit killed %rdi
%di = COPY %ax %di = COPY %ax
NOOP implicit %rax, implicit %rdi NOOP implicit %rax, implicit %rdi
... ...
--- ---
# The second copy is redundant; the call preserves the source and dest register. # The second copy is redundant; the call preserves the source and dest register.
# CHECK-LABEL: name: copyprop0 # CHECK-LABEL: name: copyprop0
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rdi # CHECK-NEXT: %rax = COPY %rdi
# CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs # CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs
# CHECK-NEXT: NOOP implicit %edi # CHECK-NEXT: NOOP implicit %edi
# CHECK-NOT: COPY # CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop0 name: copyprop0
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rdi %rax = COPY %rdi
CALL64pcrel32 @foo, csr_64_rt_mostregs CALL64pcrel32 @foo, csr_64_rt_mostregs
NOOP implicit killed %edi NOOP implicit killed %edi
%rdi = COPY %rax %rdi = COPY %rax
NOOP implicit %rax, implicit %rdi NOOP implicit %rax, implicit %rdi
... ...
--- ---
# The 2nd copy is redundant; The call preserves the source and dest register. # The 2nd copy is redundant; The call preserves the source and dest register.
# CHECK-LABEL: name: copyprop1 # CHECK-LABEL: name: copyprop1
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rdi # CHECK-NEXT: %rax = COPY %rdi
# CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop1 name: copyprop1
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rdi %rax = COPY %rdi
NOOP implicit killed %rax NOOP implicit killed %rax
%rax = COPY %rdi %rax = COPY %rdi
NOOP implicit %rax, implicit %rdi NOOP implicit %rax, implicit %rdi
... ...
--- ---
# CHECK-LABEL: name: copyprop2 # CHECK-LABEL: name: copyprop2
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rdi # CHECK-NEXT: %rax = COPY %rdi
# CHECK-NEXT: NOOP implicit %ax # CHECK-NEXT: NOOP implicit %ax
# CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs # CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs
# CHECK-NOT: %rax = COPY %rdi # CHECK-NOT: %rax = COPY %rdi
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop2 name: copyprop2
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rdi %rax = COPY %rdi
NOOP implicit killed %ax NOOP implicit killed %ax
CALL64pcrel32 @foo, csr_64_rt_mostregs CALL64pcrel32 @foo, csr_64_rt_mostregs
%rax = COPY %rdi %rax = COPY %rdi
NOOP implicit %rax, implicit %rdi NOOP implicit %rax, implicit %rdi
... ...
--- ---
# The second copy is not redundant if the source register (%rax) is clobbered # The second copy is not redundant if the source register (%rax) is clobbered
# even if the dest (%rbp) is not. # even if the dest (%rbp) is not.
# CHECK-LABEL: name: nocopyprop0 # CHECK-LABEL: name: nocopyprop0
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: %rax = COPY %rbp
# CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
# CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: %rbp = COPY %rax
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop0 name: nocopyprop0
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rbp %rax = COPY %rbp
CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
%rbp = COPY %rax %rbp = COPY %rax
NOOP implicit %rax, implicit %rbp NOOP implicit %rax, implicit %rbp
... ...
--- ---
# The second copy is not redundant if the dest register (%rax) is clobbered # The second copy is not redundant if the dest register (%rax) is clobbered
# even if the source (%rbp) is not. # even if the source (%rbp) is not.
# CHECK-LABEL: name: nocopyprop1 # CHECK-LABEL: name: nocopyprop1
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: %rbp = COPY %rax
# CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
# CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: %rax = COPY %rbp
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop1 name: nocopyprop1
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rbp = COPY %rax %rbp = COPY %rax
CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
%rax = COPY %rbp %rax = COPY %rbp
NOOP implicit %rax, implicit %rbp NOOP implicit %rax, implicit %rbp
... ...
--- ---
# The second copy is not redundant if the source register (%rax) is clobbered # The second copy is not redundant if the source register (%rax) is clobbered
# even if the dest (%rbp) is not. # even if the dest (%rbp) is not.
# CHECK-LABEL: name: nocopyprop2 # CHECK-LABEL: name: nocopyprop2
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: %rax = COPY %rbp
# CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
# CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: %rax = COPY %rbp
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop2 name: nocopyprop2
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rbp %rax = COPY %rbp
CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
%rax = COPY %rbp %rax = COPY %rbp
NOOP implicit %rax, implicit %rbp NOOP implicit %rax, implicit %rbp
... ...
--- ---
# The second copy is not redundant if the dest register (%rax) is clobbered # The second copy is not redundant if the dest register (%rax) is clobbered
# even if the source (%rbp) is not. # even if the source (%rbp) is not.
# CHECK-LABEL: name: nocopyprop3 # CHECK-LABEL: name: nocopyprop3
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: %rbp = COPY %rax
# CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
# CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: %rbp = COPY %rax
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop3 name: nocopyprop3
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rbp = COPY %rax %rbp = COPY %rax
CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
%rbp = COPY %rax %rbp = COPY %rax
NOOP implicit %rax, implicit %rbp NOOP implicit %rax, implicit %rbp
... ...
--- ---
# A reserved register may change its value so the 2nd copy is not redundant. # A reserved register may change its value so the 2nd copy is not redundant.
# CHECK-LABEL: name: nocopyprop4 # CHECK-LABEL: name: nocopyprop4
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rax = COPY %rip # CHECK-NEXT: %rax = COPY %rip
# CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax
# CHECK-NEXT: %rax = COPY %rip # CHECK-NEXT: %rax = COPY %rip
# CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax
name: nocopyprop4 name: nocopyprop4
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rax = COPY %rip %rax = COPY %rip
NOOP implicit %rax NOOP implicit %rax
%rax = COPY %rip %rax = COPY %rip
NOOP implicit %rax NOOP implicit %rax
... ...
--- ---
# Writing to a reserved register may have additional effects (slightly illegal # Writing to a reserved register may have additional effects (slightly illegal
# testcase because writing to %rip like this should make the instruction a jump) # testcase because writing to %rip like this should make the instruction a jump)
# CHECK-LABEL: name: nocopyprop5 # CHECK-LABEL: name: nocopyprop5
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: %rip = COPY %rax # CHECK-NEXT: %rip = COPY %rax
# CHECK-NEXT: %rip = COPY %rax # CHECK-NEXT: %rip = COPY %rax
name: nocopyprop5 name: nocopyprop5
allVRegsAllocated: true
body: | body: |
bb.0: bb.0:
%rip = COPY %rax %rip = COPY %rax
%rip = COPY %rax %rip = COPY %rax
... ...

llvm/trunk/test/CodeGen/X86/pr27681.mir

# RUN: llc -mtriple=i386-unknown-linux-gnu -mcpu=slm -run-pass post-RA-sched -o - %s | FileCheck %s # RUN: llc -mtriple=i386-unknown-linux-gnu -mcpu=slm -run-pass post-RA-sched -o - %s | FileCheck %s
# #
# Verify that the critical antidependence breaker does not consider # Verify that the critical antidependence breaker does not consider
# a high byte register as available as a replacement register # a high byte register as available as a replacement register
# in a certain context. # in a certain context.
--- | --- |
define void @main() { ret void } define void @main() { ret void }
... ...
--- ---
# CHECK-LABEL: main # CHECK-LABEL: main
name: main name: main
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 52 stackSize: 52
fixedStack: fixedStack:
- { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%esi' } - { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%esi' }
- { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%edi' } - { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%edi' }
- { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%ebx' } - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%ebx' }
- { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%ebp' } - { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%ebp' }
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines--- |
!49 = !DILocation(line: 14, column: 7, scope: !47) !49 = !DILocation(line: 14, column: 7, scope: !47)
!50 = !DILocation(line: 17, column: 3, scope: !4) !50 = !DILocation(line: 17, column: 3, scope: !4)
... ...
--- ---
name: add name: add
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
- { reg: '%esi' } - { reg: '%esi' }
- { reg: '%edx' } - { reg: '%edx' }
- { reg: '%ecx' } - { reg: '%ecx' }
frameInfo: frameInfo:
isFrameAddressTaken: false isFrameAddressTaken: false
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines--- |
!46 = !DILocation(line: 19, column: 3, scope: !4) !46 = !DILocation(line: 19, column: 3, scope: !4)
!47 = !DILocation(line: 20, column: 3, scope: !4) !47 = !DILocation(line: 20, column: 3, scope: !4)
... ...
--- ---
name: main name: main
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
allVRegsAllocated: true
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%edi' } - { reg: '%edi' }
- { reg: '%rsi' } - { reg: '%rsi' }
calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
'%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
'%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
'%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines