[TII] add new target hook isAdd

[SjoerdMeijer]

Summary

This adds a new target hook isAdd to TargetInstrInfo. This is refactored from the Hexagon backend and is more groundwork to find induction variables and calculate loop counts on MachineLoops.

[kparzysz]

include/llvm/Target/TargetInstrInfo.h

1086 ↗

(On Diff #68320)

There should be some description about what is expected from an instruction for which this function returns "true". Something like: one output operand (0), two input operands (1 and 2), either input can be an immediate/register/global symbol/etc. Should the instruction be free from any side-effects (such as setting some flags), or it does not matter? And so on.

[qcolombet]

Hi,

If we start adding more semantic of the instructions to TargetInstrInfo, I think we need to think more broadly on how to do that. Otherwise, I am afraid the API will not be consistent on the long run. E.g., why would we have isAdd and not isSub?
To be fair, the API is probably already broken, but there is not bad time to start fixing the problems :).

I am supportive of the idea of adding semantic, I am not convince a bunch of target hooks is necessarily the best approach or at least, having to populate those target hooks by hand.
At the very least, we should be able to annotate the instruction with isAdd in the td file and generate the hook in tablegen.

Cheers,
-Quentin

[hfinkel]

In D23601#518810, @qcolombet wrote:

Hi,

If we start adding more semantic of the instructions to TargetInstrInfo, I think we need to think more broadly on how to do that. Otherwise, I am afraid the API will not be consistent on the long run. E.g., why would we have isAdd and not isSub?
To be fair, the API is probably already broken, but there is not bad time to start fixing the problems :).

I am supportive of the idea of adding semantic, I am not convince a bunch of target hooks is necessarily the best approach or at least, having to populate those target hooks by hand.
At the very least, we should be able to annotate the instruction with isAdd in the td file and generate the hook in tablegen.

Cheers,
-Quentin

I'd really like an interface that allows converting from an MI entity to something with known semantics; I think that, with the new generic opcodes being introduced for GlobalISel, we have a good opportunity here. How about the following interface (modulo bikeshedding)?

MachineOperand *Op0, *Op1, *Op2;
if (TII->convertToGenericOp(MI, Op0, Op1, Op2) == G_ADD) {
  // This MI is equivalent to Op0 = G_ADD Op1, Op2
}

[kparzysz]

In D23601#519181, @hfinkel wrote:

I'd really like an interface that allows converting from an MI entity to something with known semantics; I think that, with the new generic opcodes being introduced for GlobalISel, we have a good opportunity here. How about the following interface (modulo bikeshedding)?

MachineOperand *Op0, *Op1, *Op2;
if (TII->convertToGenericOp(MI, Op0, Op1, Op2) == G_ADD) {
  // This MI is equivalent to Op0 = G_ADD Op1, Op2
}

I've been planning to implement something along the lines of the m_xxx pattern matching for MachineInstr. There would be some set of predefined generic operations, such as add, mul, shift, etc. but an object that can match an "add" operation could also be annotated with flags indicating that the "add" should be saturating, for example. In the absence of such annotations, the matched object would acquire such annotations from the instruction that it matched.

[SjoerdMeijer]

Hi,
Thanks a lot for the feedback!
I agree that adding it to TargetInstrInfo is a bit of a hack; adding isAdd in the td file and generate the hook in tablegen makes sense and also doable.
I will follow that approach and continue with that here.
Cheers,
Sjoerd.

[SjoerdMeijer]

This is a rewrite of the previous patch. Rather than adding a new isAdd target hook to TII, isAdd is now a field in MCInstrDesc that can be queried.

[SjoerdMeijer]

ping ;-)

@qcolombet is this more like what you had in mind?

[qcolombet]

Hi Sjoerd,

Yes, that was what I had in mind.
For some reasons though, the reply I made to Hal's proposal didn't make it to phabricator so I guess you missed it. Basically, I was saying that Hal's proposal was a good way to move.

That being said, I don't what to hold on that patch, I guess we could move towards the more generic approach in a follow up patch or when we want to add more semantic.

Just one thing, please do the replacement of 1<< by 1ULL<< in a different patch that you would apply first.

Cheers,
-Quentin

[SjoerdMeijer]

Thanks for reviewing!

The 1ULL << fix has been separately committed as revision 281149.

I noticed that I missed a failing regression test: CodeGen/Hexagon/addh-sext-trunc.ll due to a change in codegen. Interestingly, it is different because now a hwloop is created.

---

Before:

.LBB0_1: // %for.inc.preheader
{

			r3:2 = combine(##262144, #0)

}
.p2align 4
.LBB0_2: // %for.inc

// =>This Inner Loop Header: Depth=1

{

			r2 = add(r2.l, r3.h)
			if (cmp.gt(r1, r2.new)) jump:t .LBB0_2

}

---

After:

LBB0_1: // %for.inc.preheader
{

			r1 = add(r1, ##262143)

}
{

			r1 = lsr(r1, #18)

}
{

			loop0(.LBB0_2, r1)

}
.p2align 4
.Ltmp0: Block address taken
.LBB0_2: %for.inc

// =>This Inner Loop Header: Depth=1

{

			nop
			nop

} :endloop0

At a first glance, this looks correct to me. But hexagon code is completely new to me, so I don't think I can make chances here and am hoping someone can confirm this is ok.

[SjoerdMeijer]

Just to be sure, I have uploaded a modified patch set that fixes failing regression test "test/CodeGen/Hexagon/addh-sext-trunc.ll". This was not a minimal test as all it is testing, as the name suggests, is an add and sign extension, but the function had loops and lots more. Please shout if there are objections, otherwise I will be committing it soon'ish.

[bcahoon]

The change to the Hexagon test looks good to me. As you mention correctly, the intent is to check that the compiler generates one of special add variants on Hexagon, so the reduced test case is a good change.

[SjoerdMeijer]

Thanks for reviewing!

[MatzeB]

It would be great if someone could add more comments of what isAdd entails. All documentation in the current llvm code is a variation of Is this instruction an add instruction?/\brief Return true if the instruction is an add instruction.. Are there any requirements on which operands of the instruction are actually added together or hold the result? Can they be immediates and register operands, load from memory?

This flag seems to only be used on 2 hexagon instructions and it makes me wonder if it shouldn't rather have been a member function in HexagonInstrInfo.

[SjoerdMeijer]

The context of this work was to recognise loop induction statements in Machine Instructions/Loops and to allow calculation of loop iteration counts. And isAdd provides more semantic information about a MI and helps recognising induction variables. Thus, this was the ground work for D27193, which was the next step to recognise loop induction. This patch was abandoned because the Quentin's comment was that the analysis was too ad-hoc and missing some formalism. The reason this is used only in the Hexagon backend, is because I refactored it and took it from the Hexagon backend. The Hexagon backend has a lot of MachineLoop/MI analysis and other goodness (sw pipeliner) that is mostly target independent and could be made available, but a few target specific hooks are required to do this.
Now, I really would like to pick up this work again because I still think it will be valuable, but need to rethink strategy after abandoning D27193. Probably that will be a some SVEC-like approach, but hopefully that can be a light-weight implementation to recognise simple loops (which is what we're doing anyway). This will probably be quite some work, so in the mean time, I really don't mind removing or moving isAdd back to the Hexagon backend. I could also dig up the exact requirements and document that if it's okay to keep it.

llvm/trunk/include/llvm/MC/MCInstrDesc.h

 /// not use these directly.  These all correspond to bitfields in the
 /// MCInstrDesc::Flags field.
 enum Flag {
   Variadic = 0,
   HasOptionalDef,
   Pseudo,
   Return,
   Call,
+  Add,
   Barrier,
   Terminator,
   Branch,
   IndirectBranch,
   Compare,
   MoveImm,
   Bitcast,
   Select,
public:
 
   /// \brief Return true if this is a pseudo instruction that doesn't
   /// correspond to a real machine instruction.
   bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
 
   /// \brief Return true if the instruction is a return.
   bool isReturn() const { return Flags & (1ULL << MCID::Return); }
 
+  /// \brief Return true if the instruction is an add instruction.
+  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
+
   /// \brief  Return true if the instruction is a call.
   bool isCall() const { return Flags & (1ULL << MCID::Call); }
 
   /// \brief Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.
   bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
 

llvm/trunk/include/llvm/Target/Target.td

class Instruction {
   bit isBranch     = 0;     // Is this instruction a branch instruction?
   bit isIndirectBranch = 0; // Is this instruction an indirect branch?
   bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isMoveImm    = 0;     // Is this instruction a move immediate instruction?
   bit isBitcast    = 0;     // Is this instruction a bitcast instruction?
   bit isSelect     = 0;     // Is this instruction a select instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
+  bit isAdd        = 0;     // Is this instruction an add instruction?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = ?;     // Is it possible for this inst to read memory?
   bit mayStore     = ?;     // Is it possible for this inst to write memory?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit isReMaterializable = 0; // Is this instruction re-materializable?
   bit isPredicable = 0;     // Is this instruction predicable?

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

def UBFX  : I<(outs GPRnopc:$Rd),
   let Inst{11-7}  = lsb;
   let Inst{3-0}   = Rn;
 }
 
 //===----------------------------------------------------------------------===//
 //  Arithmetic Instructions.
 //
 
+let isAdd = 1 in
 defm ADD  : AsI1_bin_irs<0b0100, "add",
                          IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>;
 defm SUB  : AsI1_bin_irs<0b0010, "sub",
                          IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>;
 
 // ADD and SUB with 's' bit set.
 //
 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
 // AdjustInstrPostInstrSelection where we determine whether or not to
 // set the "s" bit based on CPSR liveness.
 //
 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
 // support for an optional CPSR definition that corresponds to the DAG
 // node's second value. We can then eliminate the implicit def of CPSR.
+let isAdd = 1 in
 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
 
+let isAdd = 1 in
 defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
 defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;
 
 defm RSB  : AsI1_rbin_irs<0b0011, "rsb",
                           IIC_iALUi, IIC_iALUr, IIC_iALUsr,
                           sub>;
 
 // FIXME: Eliminate them if we can write def : Pat patterns which defines

llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
     : T1sIt<oops, iops, itin, opc, asm, pattern>,
       T1General<opA> {
   bits<3> Rdn;
   bits<8> imm8;
   let Inst{10-8} = Rdn;
   let Inst{7-0}  = imm8;
 }
 
+let isAdd = 1 in {
   // Add with carry register
   let isCommutable = 1, Uses = [CPSR] in
   def tADC :                      // A8.6.2
     T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
                   "adc", "\t$Rdn, $Rm",
                   [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
 
   // Add immediate
   def tADDi3 :                    // A8.6.4 T1
     T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                      IIC_iALUi,
                      "add", "\t$Rd, $Rm, $imm3",
                      [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
                      Sched<[WriteALU]> {
     bits<3> imm3;
     let Inst{8-6} = imm3;
   }
 
   def tADDi8 :                    // A8.6.4 T2
     T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
                       (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
                       "add", "\t$Rdn, $imm8",
                       [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
                       Sched<[WriteALU]>;
 
   // Add register
   let isCommutable = 1 in
   def tADDrr :                    // A8.6.6 T1
     T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
                   IIC_iALUr,
                   "add", "\t$Rd, $Rn, $Rm",
                   [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
 
   let hasSideEffects = 0 in
   def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
                        "add", "\t$Rdn, $Rm", []>,
                  T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
     // A8.6.6 T2
     bits<4> Rdn;
     bits<4> Rm;
     let Inst{7}   = Rdn{3};
     let Inst{6-3} = Rm;
     let Inst{2-0} = Rdn{2-0};
   }
+}
 
 // AND register
 let isCommutable = 1 in
 def tAND :                      // A8.6.12
   T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iBITr,
                 "and", "\t$Rdn, $Rm",
                 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
                        (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
 }
 
 
 //===----------------------------------------------------------------------===//
 //  Arithmetic Instructions.
 //
 
+let isAdd = 1 in
 defm t2ADD  : T2I_bin_ii12rs<0b000, "add", add, 1>;
 defm t2SUB  : T2I_bin_ii12rs<0b101, "sub", sub>;
 
 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
 //
 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
 // AdjustInstrPostInstrSelection where we determine whether or not to

llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp

for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
     // latch block, and see if is a result of an addition of form "reg+imm",
     // where the "reg" is defined by the PHI node we are looking at.
     for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
       if (Phi->getOperand(i+1).getMBB() != Latch)
         continue;
 
       unsigned PhiOpReg = Phi->getOperand(i).getReg();
       MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
-      unsigned UpdOpc = DI->getOpcode();
-      bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp);
 
-      if (isAdd) {
+      if (DI->getDesc().isAdd()) {
         // If the register operand to the add is the PHI we're looking at, this
         // meets the induction pattern.
         unsigned IndReg = DI->getOperand(1).getReg();
         MachineOperand &Opnd2 = DI->getOperand(2);
         int64_t V;
         if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
           unsigned UpdReg = DI->getOperand(0).getReg();
           IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
 
     // Have a PHI instruction.
     for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
       if (Phi->getOperand(i+1).getMBB() != Latch)
         continue;
 
       unsigned PhiReg = Phi->getOperand(i).getReg();
       MachineInstr *DI = MRI->getVRegDef(PhiReg);
-      unsigned UpdOpc = DI->getOpcode();
-      bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp);
 
-      if (isAdd) {
+      if (DI->getDesc().isAdd()) {
         // If the register operand to the add/sub is the PHI we are looking
         // at, this meets the induction pattern.
         unsigned IndReg = DI->getOperand(1).getReg();
         MachineOperand &Opnd2 = DI->getOperand(2);
         int64_t V;
         if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
           unsigned UpdReg = DI->getOperand(0).getReg();
           IndRegs.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));

llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td

let isPredicatedFalse = PredNot in {
     // Predicate new
     def NAME#new : T_Addri_Pred<PredNot, 1>;
   }
 }
 
 let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
 multiclass Addri_base<string mnemonic, SDNode OpNode> {
   let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
-    let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
+    let opExtendable = 2, opExtentBits = 16, isPredicable = 1, isAdd = 1 in
     def A2_#NAME : T_Addri<s16Ext>;
 
     let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
       defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
       defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
     }
   }
 }
class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
   let Inst{4-0} = Rd;
 }
 
 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
                     bit OpsRev, bit IsComm>
   : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
                IsComm, "">;
 
+let isAdd = 1 in
 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
 
 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
 
 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
                       bit IsNeg>

llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{H|h}})
 
 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
 target triple = "hexagon-unknown-none"
 
-%struct.aDataType = type { i16, i16, i16, i16, i16, i16*, i16*, i16*, i8*, i16*, i16*, i16*, i8* }
 
-define i8* @a_get_score(%struct.aDataType* nocapture %pData, i16 signext %gmmModelIndex, i16* nocapture %pGmmScoreL16Q4) #0 {
-entry:
-  %numSubVector = getelementptr inbounds %struct.aDataType, %struct.aDataType* %pData, i32 0, i32 3
-  %0 = load i16, i16* %numSubVector, align 2, !tbaa !0
-  %and = and i16 %0, -4
-  %b = getelementptr inbounds %struct.aDataType, %struct.aDataType* %pData, i32 0, i32 8
-  %1 = load i8*, i8** %b, align 4, !tbaa !3
+define i32 @foo(i16 %a, i32 %b) #0 {
+  %and = and i16 %a, -4
   %conv3 = sext i16 %and to i32
-  %cmp21 = icmp sgt i16 %and, 0
-  br i1 %cmp21, label %for.inc.preheader, label %for.end
-
-for.inc.preheader:                                ; preds = %entry
-  br label %for.inc
-
-for.inc:                                          ; preds = %for.inc.preheader, %for.inc
-  %j.022 = phi i32 [ %phitmp, %for.inc ], [ 0, %for.inc.preheader ]
-  %add13 = mul i32 %j.022, 65536
+  %add13 = mul i32 %b, 65536
   %sext = add i32 %add13, 262144
   %phitmp = ashr exact i32 %sext, 16
-  %cmp = icmp slt i32 %phitmp, %conv3
-  br i1 %cmp, label %for.inc, label %for.end.loopexit
-
-for.end.loopexit:                                 ; preds = %for.inc
-  br label %for.end
-
-for.end:                                          ; preds = %for.end.loopexit, %entry
-  ret i8* %1
+  ret i32 %phitmp
 }
 
+
 attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
 
 !0 = !{!"short", !1}
 !1 = !{!"omnipotent char", !2}
 !2 = !{!"Simple C/C++ TBAA"}
 !3 = !{!"any pointer", !1}

llvm/trunk/utils/TableGen/CodeGenInstruction.h

public:
     bool isBranch : 1;
     bool isIndirectBranch : 1;
     bool isCompare : 1;
     bool isMoveImm : 1;
     bool isBitcast : 1;
     bool isSelect : 1;
     bool isBarrier : 1;
     bool isCall : 1;
+    bool isAdd : 1;
     bool canFoldAsLoad : 1;
     bool mayLoad : 1;
     bool mayLoad_Unset : 1;
     bool mayStore : 1;
     bool mayStore_Unset : 1;
     bool isPredicable : 1;
     bool isConvertibleToThreeAddress : 1;
     bool isCommutable : 1;

llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   // Emit all of the target independent flags...
   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
   if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
   if (Inst.isBranch)           OS << "|(1ULL<<MCID::Branch)";
   if (Inst.isIndirectBranch)   OS << "|(1ULL<<MCID::IndirectBranch)";
   if (Inst.isCompare)          OS << "|(1ULL<<MCID::Compare)";
   if (Inst.isMoveImm)          OS << "|(1ULL<<MCID::MoveImm)";
   if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
+  if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
   if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
   if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";