MIRParser: Use shorter cfi identifiers

[MatzeB]

Summary

In an instruction like:

CFI_INSTRUCTION .cfi_def_cfa ...

we can drop the '.cfi_' prefix since that should be obvious by the
context:

CFI_INSTRUCTION def_cfa ...

While being a terser and cleaner syntax this will enable upcoming changes that re-use the '.' symbol as a separate token rather than making it part of an identifier by default.

[MatzeB]

ping

[qcolombet]

LGTM.

llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("killed", MIToken::kw_killed)
       .Case("undef", MIToken::kw_undef)
       .Case("internal", MIToken::kw_internal)
       .Case("early-clobber", MIToken::kw_early_clobber)
       .Case("debug-use", MIToken::kw_debug_use)
       .Case("tied-def", MIToken::kw_tied_def)
       .Case("frame-setup", MIToken::kw_frame_setup)
       .Case("debug-location", MIToken::kw_debug_location)
-      .Case(".cfi_same_value", MIToken::kw_cfi_same_value)
-      .Case(".cfi_offset", MIToken::kw_cfi_offset)
-      .Case(".cfi_def_cfa_register", MIToken::kw_cfi_def_cfa_register)
-      .Case(".cfi_def_cfa_offset", MIToken::kw_cfi_def_cfa_offset)
-      .Case(".cfi_def_cfa", MIToken::kw_cfi_def_cfa)
+      .Case("same_value", MIToken::kw_cfi_same_value)
+      .Case("offset", MIToken::kw_cfi_offset)
+      .Case("def_cfa_register", MIToken::kw_cfi_def_cfa_register)
+      .Case("def_cfa_offset", MIToken::kw_cfi_def_cfa_offset)
+      .Case("def_cfa", MIToken::kw_cfi_def_cfa)
       .Case("blockaddress", MIToken::kw_blockaddress)
       .Case("target-index", MIToken::kw_target_index)
       .Case("half", MIToken::kw_half)
       .Case("float", MIToken::kw_float)
       .Case("double", MIToken::kw_double)
       .Case("x86_fp80", MIToken::kw_x86_fp80)
       .Case("fp128", MIToken::kw_fp128)
       .Case("ppc_fp128", MIToken::kw_ppc_fp128)

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
   }
   printReg(Reg, OS, TRI);
 }
 
 void MIPrinter::print(const MCCFIInstruction &CFI,
                       const TargetRegisterInfo *TRI) {
   switch (CFI.getOperation()) {
   case MCCFIInstruction::OpSameValue:
-    OS << ".cfi_same_value ";
+    OS << "same_value ";
     if (CFI.getLabel())
       OS << "<mcsymbol> ";
     printCFIRegister(CFI.getRegister(), OS, TRI);
     break;
   case MCCFIInstruction::OpOffset:
-    OS << ".cfi_offset ";
+    OS << "offset ";
     if (CFI.getLabel())
       OS << "<mcsymbol> ";
     printCFIRegister(CFI.getRegister(), OS, TRI);
     OS << ", " << CFI.getOffset();
     break;
   case MCCFIInstruction::OpDefCfaRegister:
-    OS << ".cfi_def_cfa_register ";
+    OS << "def_cfa_register ";
     if (CFI.getLabel())
       OS << "<mcsymbol> ";
     printCFIRegister(CFI.getRegister(), OS, TRI);
     break;
   case MCCFIInstruction::OpDefCfaOffset:
-    OS << ".cfi_def_cfa_offset ";
+    OS << "def_cfa_offset ";
     if (CFI.getLabel())
       OS << "<mcsymbol> ";
     OS << CFI.getOffset();
     break;
   case MCCFIInstruction::OpDefCfa:
-    OS << ".cfi_def_cfa ";
+    OS << "def_cfa ";
     if (CFI.getLabel())
       OS << "<mcsymbol> ";
     printCFIRegister(CFI.getRegister(), OS, TRI);
     OS << ", " << CFI.getOffset();
     break;
   default:
     // TODO: Print the other CFI Operations.
     OS << "<unserializable cfi operation>";

llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir

bb.1:
     %r0 = t2MOVi -1, 14, _, _
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     tBX_RET 14, _, implicit %r0, debug-location !34
 
   bb.2.if.end:
     liveins: %r0, %r2, %r3, %r7, %lr
 
     %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4
-    frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset %lr, -4
+    frame-setup CFI_INSTRUCTION offset %r7, -8
     DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
     DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
     %r1 = COPY killed %r2, debug-location !32
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     %r2 = COPY killed %r3, debug-location !32
     tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
     %r0 = t2MOVi 0, 14, _, _
     %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr
     tBX_RET 14, _, implicit %r0, debug-location !34
 # Verify that the DBG_VALUE is ignored.
 # CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
 
 ...

llvm/trunk/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir

 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_def_cfa operands
+# This test ensures that the MIR parser parses the def_cfa operands
 # correctly.
 
 --- |
 
   declare void @foo()
 
   define void @trivial_fp_func() {
   entry:
     call void @foo()
     ret void
   }
 
 ...
 ---
 name:            trivial_fp_func
 body: |
   bb.0.entry:
     liveins: %lr, %fp, %lr, %fp
 
     %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
     %fp = frame-setup ADDXri %sp, 0, 0
-    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16
-    frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8
-    frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16
+    ; CHECK: CFI_INSTRUCTION def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION offset %w30, -8
+    frame-setup CFI_INSTRUCTION offset %w29, -16
     BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
     %sp, %fp, %lr = LDPXpost %sp, 2
     RET_ReallyLR
 ...

llvm/trunk/test/CodeGen/MIR/ARM/cfi-same-value.mir

stack:
   - { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4,
       callee-saved-register: '%r11' }
 body: |
   bb.0:
     successors: %bb.2, %bb.1
     liveins: %r11, %lr
 
     %sp = STMDB_UPD %sp, 14, _, %r4, %r5
-    CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    CFI_INSTRUCTION .cfi_offset %r5, -4
-    CFI_INSTRUCTION .cfi_offset %r4, -8
+    CFI_INSTRUCTION def_cfa_offset 8
+    CFI_INSTRUCTION offset %r5, -4
+    CFI_INSTRUCTION offset %r4, -8
     %r5 = MOVr %sp, 14, _, _
     %r4 = MRC 15, 0, 13, 0, 3, 14, _
     %r4 = LDRi12 %r4, 4, 14, _
     CMPrr %r4, %r5, 14, _, implicit-def %cpsr
     Bcc %bb.2, 3, %cpsr
 
   bb.1:
     successors: %bb.2
     liveins: %r11, %lr
 
     %r4 = MOVi 48, 14, _, _
     %r5 = MOVi 0, 14, _, _
     %sp = STMDB_UPD %sp, 14, _, %lr
-    CFI_INSTRUCTION .cfi_def_cfa_offset 12
-    CFI_INSTRUCTION .cfi_offset %lr, -12
+    CFI_INSTRUCTION def_cfa_offset 12
+    CFI_INSTRUCTION offset %lr, -12
     BL $__morestack, implicit-def %lr, implicit %sp
     %sp = LDMIA_UPD %sp, 14, _, %lr
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
-    CFI_INSTRUCTION .cfi_def_cfa_offset 0
+    CFI_INSTRUCTION def_cfa_offset 0
     BX_RET 14, _
 
   bb.2:
     liveins: %r11, %lr
 
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
-    CFI_INSTRUCTION .cfi_def_cfa_offset 0
-  ; CHECK:      CFI_INSTRUCTION .cfi_same_value %r4
-  ; CHECK-NEXT: CFI_INSTRUCTION .cfi_same_value %r5
-    CFI_INSTRUCTION .cfi_same_value %r4
-    CFI_INSTRUCTION .cfi_same_value %r5
+    CFI_INSTRUCTION def_cfa_offset 0
+  ; CHECK:      CFI_INSTRUCTION same_value %r4
+  ; CHECK-NEXT: CFI_INSTRUCTION same_value %r5
+    CFI_INSTRUCTION same_value %r4
+    CFI_INSTRUCTION same_value %r5
     %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r11, killed %lr
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4
-    frame-setup CFI_INSTRUCTION .cfi_offset %r11, -8
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset %lr, -4
+    frame-setup CFI_INSTRUCTION offset %r11, -8
     %sp = frame-setup SUBri killed %sp, 40, 14, _, _
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 48
+    frame-setup CFI_INSTRUCTION def_cfa_offset 48
     %r0 = MOVr %sp, 14, _, _
     %r1 = MOVi 10, 14, _, _
     BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, implicit-def %sp
     %sp = ADDri killed %sp, 40, 14, _, _
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
     MOVPCLR 14, _
 ...

llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir

bb.0.entry:
     DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
     DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
     t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     tBX_RET 3, %cpsr, implicit %r0, debug-location !34
     %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4
-    frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset %lr, -4
+    frame-setup CFI_INSTRUCTION offset %r7, -8
     DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
     DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
     %r1 = tMOVr killed %r2, 14, _, debug-location !32
     %r2 = tMOVr killed %r3, 14, _, debug-location !32
     tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
     %r0 = t2MOVi 0, 14, _, _
     %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
 
 ...

llvm/trunk/test/CodeGen/MIR/Mips/memory-operands.mir

 stack:
   - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
       callee-saved-register: '%ra' }
 body:             |
   bb.0.entry:
     liveins: %a0, %ra
 
     Save16 %ra, 24, implicit-def %sp, implicit %sp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 24
-    CFI_INSTRUCTION .cfi_offset %ra_64, -4
+    CFI_INSTRUCTION def_cfa_offset 24
+    CFI_INSTRUCTION offset %ra_64, -4
     %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp
     %v0 = SllX16 killed %v0, 16
     %v0 = AdduRxRyRz16 killed %v1, killed %v0
   ; CHECK-LABEL: name: test
   ; CHECK: %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo)
     %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo)
     %t9 = COPY %v1
     %gp = COPY killed %v0
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4,
       callee-saved-register: '%s2' }
   - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4,
       callee-saved-register: '%s0' }
 body:             |
   bb.0.entry:
     liveins: %ra, %s2, %s0, %ra, %s2, %s0
 
     SaveX16 %s0, %ra, %s2, 32, implicit-def %sp, implicit %sp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 32
-    CFI_INSTRUCTION .cfi_offset %ra_64, -4
-    CFI_INSTRUCTION .cfi_offset %s2_64, -8
-    CFI_INSTRUCTION .cfi_offset %s0_64, -12
+    CFI_INSTRUCTION def_cfa_offset 32
+    CFI_INSTRUCTION offset %ra_64, -4
+    CFI_INSTRUCTION offset %s2_64, -8
+    CFI_INSTRUCTION offset %s0_64, -12
     %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp
     %v0 = SllX16 killed %v0, 16
     %s0 = AdduRxRyRz16 killed %v1, killed %v0
     %v0 = LwRxRyOffMemX16 %s0, @g :: (load 4 from call-entry @g)
   ; CHECK-LABEL: test2
   ; CHECK: %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0 :: (load 4 from call-entry $__mips16_call_stub_sf_0)
     %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0 :: (load 4 from call-entry $__mips16_call_stub_sf_0)
     %gp = COPY %s0
     JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit %v0, implicit killed %gp, implicit-def %sp, implicit-def %v0
     %v1 = LwRxRyOffMemX16 %s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf)
     %t9 = COPY %v1
     %gp = COPY killed %s0
     JumpLinkReg16 killed %v1, csr_mips16rethelper, implicit-def %ra, implicit killed %t9, implicit %v0, implicit killed %gp, implicit-def %sp
     %s0, %ra, %s2 = RestoreX16 32, implicit-def %sp, implicit %sp
     RetRA16 implicit %v0
 ...

llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_def_cfa_offset operands
+# This test ensures that the MIR parser parses the cfi offset operands
 # correctly.
 
 --- |
 
   define void @test() {
   entry:
     %tmp = alloca [4168 x i8], align 4
     ret void
   }
 
 ...
 ---
 name:            test
 tracksRegLiveness: true
 frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
 body: |
   bb.0.entry:
     %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
-    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
-    CFI_INSTRUCTION .cfi_def_cfa_offset 4048
+    ; CHECK: CFI_INSTRUCTION def_cfa_offset 4048
+    CFI_INSTRUCTION def_cfa_offset 4048
     %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
     RETQ
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_def_cfa_register
+# This test ensures that the MIR parser parses the cfi def_cfa_register
 # operands correctly.
 
 --- |
 
   define void @func() #0 {
   entry:
     unreachable
   }
 
   attributes #0 = { "no-frame-pointer-elim"="true" }
 
 ...
 ---
 name:            func
 tracksRegLiveness: true
 frameInfo:
   stackSize:     8
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
 body: |
   bb.0.entry:
     liveins: %rbp
 
     PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
     %rbp = MOV64rr %rsp
-    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
-    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    ; CHECK: CFI_INSTRUCTION def_cfa_register %rbp
+    CFI_INSTRUCTION def_cfa_register %rbp
 ...

llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_offset operands
+# This test ensures that the MIR parser parses the cfi offset operands
 # correctly.
 
 --- |
 
   declare void @foo(i32)
 
   define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
   entry:
frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
 body: |
   bb.0.entry:
     liveins: %ecx, %edi, %edx, %esi, %rbx
 
     PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    ; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
-    CFI_INSTRUCTION .cfi_offset %rbx, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: CFI_INSTRUCTION offset %rbx, -16
+    CFI_INSTRUCTION offset %rbx, -16
     %ebx = COPY %edi, implicit-def %rbx
     %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
     %edi = COPY %ebx
     CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
     %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
     %rbx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir

frameInfo:
   stackSize:     8
   adjustsStack:  true
   hasCalls:      true
 body: |
   bb.0.entry:
     liveins: %edi, %esi
 
     frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    CFI_INSTRUCTION def_cfa_offset 16
     %ecx = COPY %edi
     %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
   ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
     INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
     %edi = COPY killed %ecx
     CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
     %rax = POP64r implicit-def %rsp, implicit %rsp
     RETQ
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir

frameInfo:
   stackSize:       8
   adjustsStack:    true
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
 body: |
   bb.0.entry:
     PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    ; CHECK: [[@LINE+1]]:38: expected ','
-    CFI_INSTRUCTION .cfi_offset %rbx -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:33: expected ','
+    CFI_INSTRUCTION offset %rbx -16
     %ebx = COPY %edi, implicit-def %rbx
     %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
     %edi = COPY %ebx
     CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
     %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
     %rbx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir

 tracksRegLiveness: true
 frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
 body: |
   bb.0.entry:
     %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
-    ; CHECK: [[@LINE+1]]:41: expected a cfi offset
-    CFI_INSTRUCTION .cfi_def_cfa_offset _
+    ; CHECK: [[@LINE+1]]:36: expected a cfi offset
+    CFI_INSTRUCTION def_cfa_offset _
     %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
     RETQ
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir

frameInfo:
   stackSize:       8
   adjustsStack:    true
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
 body: |
   bb.0.entry:
     PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    ; CHECK: [[@LINE+1]]:33: expected a cfi register
-    CFI_INSTRUCTION .cfi_offset %0, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:28: expected a cfi register
+    CFI_INSTRUCTION offset %0, -16
     %ebx = COPY %edi, implicit-def %rbx
     %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
     %edi = COPY %ebx
     CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
     %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
     %rbx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir

frameInfo:
   maxAlignment:    4
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true }
 stack:
   - { id: 0, name: b, offset: -8, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 8
+    CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK: name: test
   ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
     %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
     MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
     %edx = POP32r implicit-def %esp, implicit %esp
     RETL %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir

 tracksRegLiveness: true
 frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
 body: |
   bb.0.entry:
     %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
-    ; CHECK: [[@LINE+1]]:41: expected a 32 bit integer (the cfi offset is too large)
-    CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456
+    ; CHECK: [[@LINE+1]]:36: expected a 32 bit integer (the cfi offset is too large)
+    CFI_INSTRUCTION def_cfa_offset 123456789123456
     %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
     RETQ
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir

frameInfo:
   hasCalls:      true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
 body: |
   bb.0.entry:
     liveins: %rdi, %rsi, %rbp
 
     frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
     %rbp = frame-setup MOV64rr %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    CFI_INSTRUCTION def_cfa_register %rbp
   ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
     PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
     %rbp = POP64r implicit-def %rsp, implicit %rsp
     RETQ
 ...

llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir

frameInfo:
   adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 16
 fixedStack:
   - { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false }
 body: |
   bb.0.entry:
     %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags
-    CFI_INSTRUCTION .cfi_def_cfa_offset 32
+    CFI_INSTRUCTION def_cfa_offset 32
     LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw
   ; CHECK: name: stack_psv
   ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
     ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
     CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0
     %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags
     RETQ
 ...

llvm/trunk/test/CodeGen/X86/patchpoint-verifiable.mir

frameInfo:
   hasCalls:      true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
 body: |
   bb.0.entry:
     liveins: %rdi, %rsi, %rbp
 
     frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
     %rbp = frame-setup MOV64rr %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    CFI_INSTRUCTION def_cfa_register %rbp
   ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
     PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
     %rbp = POP64r implicit-def %rsp, implicit %rsp
     RETQ
 ...

llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir

 fixedStack:      
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
 body:             |
   bb.0.entry:
     successors: %bb.1.if.else(16), %bb.2.if.end(16)
     liveins: %edi, %rsi, %rbx
   
     frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    CFI_INSTRUCTION .cfi_offset %rbx, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbx, -16
     DBG_VALUE debug-use %edi, debug-use _, !12, !20, debug-location !21
     DBG_VALUE debug-use %rsi, debug-use _, !13, !20, debug-location !22
     %eax = MOV32rr %edi
     DBG_VALUE debug-use %eax, debug-use _, !12, !20, debug-location !21
     %edi = MOV32ri 2
     CMP32ri8 killed %eax, 2, implicit-def %eflags, debug-location !26
     JNE_1 %bb.2.if.end, implicit %eflags