ELF/AMDGPU: Add support for GOT relocations

[• tstellarAMD]

Ping.

[ruiu]

ELF/Target.cpp

1426 ↗

(On Diff #61131)

fatal() is called in relocateOne, so unknown relocations are fatal. Can we also call fatal here?

Also, please run clang-format on this patch.

[• tstellarAMD]

Use fatal() instead of error() and run clang-format.

[kzhuravl]

LGTM

[ruiu]

LGTM with a stylistic change.

ELF/Target.cpp

1434 ↗

(On Diff #61801)

fatal does not return, so remove this comment. Also, please move default: at end of this switch to make the order of the cases the same as the above switch.

lld/trunk/ELF/Target.cpp

RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 
 class AMDGPUTargetInfo final : public TargetInfo {
 public:
-  AMDGPUTargetInfo() {}
+  AMDGPUTargetInfo();
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
 };
 
 class ARMTargetInfo final : public TargetInfo {
 public:
   ARMTargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
     // Generate MOVK.
     uint32_t RegNo = read32le(Loc) & 0x1f;
     write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
     return;
   }
   llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
 }
 
+AMDGPUTargetInfo::AMDGPUTargetInfo() { GotRel = R_AMDGPU_ABS64; }
+
 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                    uint64_t Val) const {
-  assert(Type == R_AMDGPU_REL32);
+  switch (Type) {
+  case R_AMDGPU_GOTPCREL:
+  case R_AMDGPU_REL32:
     write32le(Loc, Val);
+    break;
+  default:
+    fatal("unrecognized reloc " + Twine(Type));
+  }
 }
 
 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
-  if (Type != R_AMDGPU_REL32)
-    error("do not know how to handle relocation");
+  switch (Type) {
+  case R_AMDGPU_REL32:
     return R_PC;
+  case R_AMDGPU_GOTPCREL:
+    return R_GOT_PC;
+  default:
+    fatal("do not know how to handle relocation " + Twine(Type));
+  }
 }
 
 ARMTargetInfo::ARMTargetInfo() {
   CopyRel = R_ARM_COPY;
   RelativeRel = R_ARM_RELATIVE;
   IRelativeRel = R_ARM_IRELATIVE;
   GotRel = R_ARM_GLOB_DAT;
   PltRel = R_ARM_JUMP_SLOT;

lld/trunk/test/ELF/amdgpu-relocs.s

 # RUN: llvm-mc -filetype=obj -triple=amdgcn--amdhsa -mcpu=fiji %s -o %t.o
 # RUN: ld.lld -shared %t.o -o %t.so
 # RUN: llvm-readobj -r %t.so | FileCheck %s
 
 # REQUIRES: amdgpu
 
-# Make sure that the reloc for local_var is resolved by lld.
-
   .text
 
 kernel0:
+  s_mov_b32 s0, common_var@GOTPCREL+4
+  s_mov_b32 s0, extern_var@GOTPCREL+4
   s_mov_b32 s0, local_var+4
+  s_mov_b32 s0, global_var@GOTPCREL+4
+  s_mov_b32 s0, weak_var@GOTPCREL+4
+  s_mov_b32 s0, weakref_var@GOTPCREL+4
   s_endpgm
 
-  .local local_var
+  .comm   common_var,1024,4
+  .globl  global_var
+  .local  local_var
+  .weak   weak_var
+  .weakref weakref_var, weakref_alias_var
 
+# The relocation for local_var should be resolved by the linker.
 # CHECK: Relocations [
+# CHECK: .rela.dyn {
+# CHECK-NEXT: R_AMDGPU_ABS64 common_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 extern_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 global_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 weak_var 0x0
+# CHECK-NEXT: R_AMDGPU_ABS64 weakref_alias_var 0x0
+# CHECK-NEXT: }
 # CHECK-NEXT: ]